sys/arm/allwinner/clkng/ccu_a10.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2018 Kyle Evans <kevans@FreeBSD.org>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  20  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  21  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  22  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  23  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD$
  28  */
  29
  30 #include <sys/cdefs.h>
  31 __FBSDID("$FreeBSD$");
  32
  33 #include <sys/param.h>
  34 #include <sys/systm.h>
  35 #include <sys/bus.h>
  36 #include <sys/rman.h>
  37 #include <sys/kernel.h>
  38 #include <sys/module.h>
  39 #include <machine/bus.h>
  40
  41 #include <dev/fdt/simplebus.h>
  42
  43 #include <dev/ofw/ofw_bus.h>
  44 #include <dev/ofw/ofw_bus_subr.h>
  45
  46 #include <dev/extres/clk/clk_div.h>
  47 #include <dev/extres/clk/clk_fixed.h>
  48 #include <dev/extres/clk/clk_mux.h>
  49
  50 #include <arm/allwinner/clkng/aw_ccung.h>
  51
  52 #include <gnu/dts/include/dt-bindings/clock/sun4i-a10-ccu.h>
  53 #include <gnu/dts/include/dt-bindings/clock/sun7i-a20-ccu.h>
  54 #include <gnu/dts/include/dt-bindings/reset/sun4i-a10-ccu.h>
  55
  56 /* Non-exported resets */
  57 /* Non-exported clocks */
  58 #define CLK_PLL_CORE            2
  59 #define CLK_AXI                 3
  60 #define CLK_AHB                 4
  61 #define CLK_APB0                5
  62 #define CLK_APB1                6
  63 #define CLK_PLL_VIDEO0          8
  64 #define CLK_PLL_DDR             12
  65 #define CLK_PLL_DDR_OTHER       13
  66 #define CLK_PLL6                14
  67 #define CLK_PLL_PERIPH          15
  68 #define CLK_PLL_SATA            16
  69 #define CLK_PLL_VIDEO1          17
  70
  71 /* Non-exported fixed clocks */
  72
  73 static struct aw_ccung_reset a10_ccu_resets[] = {
  74         CCU_RESET(RST_USB_PHY0, 0xcc, 0)
  75         CCU_RESET(RST_USB_PHY1, 0xcc, 1)
  76         CCU_RESET(RST_USB_PHY2, 0xcc, 2)
  77
  78         CCU_RESET(RST_GPS, 0xd0, 0)
  79
  80         CCU_RESET(RST_DE_BE0, 0x104, 30)
  81         CCU_RESET(RST_DE_BE1, 0x108, 30)
  82         CCU_RESET(RST_DE_FE0, 0x10c, 30)
  83         CCU_RESET(RST_DE_FE1, 0x110, 30)
  84         CCU_RESET(RST_DE_MP, 0x114, 30)
  85
  86         CCU_RESET(RST_TVE0, 0x118, 29)
  87         CCU_RESET(RST_TCON0, 0x118, 30)
  88
  89         CCU_RESET(RST_TVE1, 0x11c, 29)
  90         CCU_RESET(RST_TCON1, 0x11c, 30)
  91
  92         CCU_RESET(RST_CSI0, 0x134, 30)
  93         CCU_RESET(RST_CSI1, 0x138, 30)
  94
  95         CCU_RESET(RST_VE, 0x13c, 0)
  96
  97         CCU_RESET(RST_ACE, 0x148, 16)
  98
  99         CCU_RESET(RST_LVDS, 0x14c, 0)
 100
 101         CCU_RESET(RST_GPU, 0x154, 30)
 102
 103         CCU_RESET(RST_HDMI_H, 0x170, 0)
 104         CCU_RESET(RST_HDMI_SYS, 0x170, 1)
 105         CCU_RESET(RST_HDMI_AUDIO_DMA, 0x170, 2)
 106 };
 107
 108 static struct aw_ccung_gate a10_ccu_gates[] = {
 109         CCU_GATE(CLK_HOSC, "hosc", "osc24M", 0x50, 0)
 110
 111         CCU_GATE(CLK_AHB_OTG, "ahb-otg", "ahb", 0x60, 0)
 112         CCU_GATE(CLK_AHB_EHCI0, "ahb-ehci0", "ahb", 0x60, 1)
 113         CCU_GATE(CLK_AHB_OHCI0, "ahb-ohci0", "ahb", 0x60, 2)
 114         CCU_GATE(CLK_AHB_EHCI1, "ahb-ehci1", "ahb", 0x60, 3)
 115         CCU_GATE(CLK_AHB_OHCI1, "ahb-ohci1", "ahb", 0x60, 4)
 116         CCU_GATE(CLK_AHB_SS, "ahb-ss", "ahb", 0x60, 5)
 117         CCU_GATE(CLK_AHB_DMA, "ahb-dma", "ahb", 0x60, 6)
 118         CCU_GATE(CLK_AHB_BIST, "ahb-bist", "ahb", 0x60, 7)
 119         CCU_GATE(CLK_AHB_MMC0, "ahb-mmc0", "ahb", 0x60, 8)
 120         CCU_GATE(CLK_AHB_MMC1, "ahb-mmc1", "ahb", 0x60, 9)
 121         CCU_GATE(CLK_AHB_MMC2, "ahb-mmc2", "ahb", 0x60, 10)
 122         CCU_GATE(CLK_AHB_MMC3, "ahb-mmc3", "ahb", 0x60, 11)
 123         CCU_GATE(CLK_AHB_MS, "ahb-ms", "ahb", 0x60, 12)
 124         CCU_GATE(CLK_AHB_NAND, "ahb-nand", "ahb", 0x60, 13)
 125         CCU_GATE(CLK_AHB_SDRAM, "ahb-sdram", "ahb", 0x60, 14)
 126         CCU_GATE(CLK_AHB_ACE, "ahb-ace", "ahb", 0x60, 16)
 127         CCU_GATE(CLK_AHB_EMAC, "ahb-emac", "ahb", 0x60, 17)
 128         CCU_GATE(CLK_AHB_TS, "ahb-ts", "ahb", 0x60, 18)
 129         CCU_GATE(CLK_AHB_SPI0, "ahb-spi0", "ahb", 0x60, 20)
 130         CCU_GATE(CLK_AHB_SPI1, "ahb-spi1", "ahb", 0x60, 21)
 131         CCU_GATE(CLK_AHB_SPI2, "ahb-spi2", "ahb", 0x60, 22)
 132         CCU_GATE(CLK_AHB_SPI3, "ahb-spi3", "ahb", 0x60, 23)
 133         CCU_GATE(CLK_AHB_SATA, "ahb-sata", "ahb", 0x60, 25)
 134
 135         CCU_GATE(CLK_AHB_VE, "ahb-ve", "ahb", 0x64, 0)
 136         CCU_GATE(CLK_AHB_TVD, "ahb-tvd", "ahb", 0x64, 1)
 137         CCU_GATE(CLK_AHB_TVE0, "ahb-tve0", "ahb", 0x64, 2)
 138         CCU_GATE(CLK_AHB_TVE1, "ahb-tve1", "ahb", 0x64, 3)
 139         CCU_GATE(CLK_AHB_LCD0, "ahb-lcd0", "ahb", 0x64, 4)
 140         CCU_GATE(CLK_AHB_LCD1, "ahb-lcd1", "ahb", 0x64, 5)
 141         CCU_GATE(CLK_AHB_CSI0, "ahb-csi0", "ahb", 0x64, 8)
 142         CCU_GATE(CLK_AHB_CSI1, "ahb-csi1", "ahb", 0x64, 9)
 143         CCU_GATE(CLK_AHB_HDMI1, "ahb-hdmi1", "ahb", 0x64, 10)
 144         CCU_GATE(CLK_AHB_HDMI0, "ahb-hdmi0", "ahb", 0x64, 11)
 145         CCU_GATE(CLK_AHB_DE_BE0, "ahb-de_be0", "ahb", 0x64, 12)
 146         CCU_GATE(CLK_AHB_DE_BE1, "ahb-de_be1", "ahb", 0x64, 13)
 147         CCU_GATE(CLK_AHB_DE_FE0, "ahb-de_fe0", "ahb", 0x64, 14)
 148         CCU_GATE(CLK_AHB_DE_FE1, "ahb-de_fe1", "ahb", 0x64, 15)
 149         CCU_GATE(CLK_AHB_GMAC, "ahb-gmac", "ahb", 0x64, 17)
 150         CCU_GATE(CLK_AHB_MP, "ahb-mp", "ahb", 0x64, 18)
 151         CCU_GATE(CLK_AHB_GPU, "ahb-gpu", "ahb", 0x64, 20)
 152
 153         CCU_GATE(CLK_APB0_CODEC, "apb0-codec", "apb0", 0x68, 0)
 154         CCU_GATE(CLK_APB0_SPDIF, "apb0-spdif", "apb0", 0x68, 1)
 155         CCU_GATE(CLK_APB0_AC97, "apb0-ac97", "apb0", 0x68, 2)
 156         CCU_GATE(CLK_APB0_I2S0, "apb0-i2s0", "apb0", 0x68, 3)
 157         CCU_GATE(CLK_APB0_I2S1, "apb0-i2s1", "apb0", 0x68, 4)
 158         CCU_GATE(CLK_APB0_PIO, "apb0-pi0", "apb0", 0x68, 5)
 159         CCU_GATE(CLK_APB0_IR0, "apb0-ir0", "apb0", 0x68, 6)
 160         CCU_GATE(CLK_APB0_IR1, "apb0-ir1", "apb0", 0x68, 7)
 161         CCU_GATE(CLK_APB0_I2S2, "apb0-i2s2", "apb0",0x68, 8)
 162         CCU_GATE(CLK_APB0_KEYPAD, "apb0-keypad", "apb0", 0x68, 10)
 163
 164         CCU_GATE(CLK_APB1_I2C0, "apb1-i2c0", "apb1", 0x6c, 0)
 165         CCU_GATE(CLK_APB1_I2C1, "apb1-i2c1", "apb1",0x6c, 1)
 166         CCU_GATE(CLK_APB1_I2C2, "apb1-i2c2", "apb1",0x6c, 2)
 167         CCU_GATE(CLK_APB1_I2C3, "apb1-i2c3", "apb1",0x6c, 3)
 168         CCU_GATE(CLK_APB1_CAN, "apb1-can", "apb1",0x6c, 4)
 169         CCU_GATE(CLK_APB1_SCR, "apb1-scr", "apb1",0x6c, 5)
 170         CCU_GATE(CLK_APB1_PS20, "apb1-ps20", "apb1",0x6c, 6)
 171         CCU_GATE(CLK_APB1_PS21, "apb1-ps21", "apb1",0x6c, 7)
 172         CCU_GATE(CLK_APB1_I2C4, "apb1-i2c4", "apb1", 0x6c, 15)
 173         CCU_GATE(CLK_APB1_UART0, "apb1-uart0", "apb1",0x6c, 16)
 174         CCU_GATE(CLK_APB1_UART1, "apb1-uart1", "apb1",0x6c, 17)
 175         CCU_GATE(CLK_APB1_UART2, "apb1-uart2", "apb1",0x6c, 18)
 176         CCU_GATE(CLK_APB1_UART3, "apb1-uart3", "apb1",0x6c, 19)
 177         CCU_GATE(CLK_APB1_UART4, "apb1-uart4", "apb1",0x6c, 20)
 178         CCU_GATE(CLK_APB1_UART5, "apb1-uart5", "apb1",0x6c, 21)
 179         CCU_GATE(CLK_APB1_UART6, "apb1-uart6", "apb1",0x6c, 22)
 180         CCU_GATE(CLK_APB1_UART7, "apb1-uart7", "apb1",0x6c, 23)
 181
 182         CCU_GATE(CLK_USB_OHCI0, "usb-ohci0", "ahb", 0xcc, 6)
 183         CCU_GATE(CLK_USB_OHCI1, "usb-ohci1", "ahb", 0xcc, 7)
 184         CCU_GATE(CLK_USB_PHY, "usb-phy", "ahb", 0xcc, 8)
 185
 186         CCU_GATE(CLK_DRAM_VE, "dram-ve", "pll_ddr", 0x100, 0)
 187         CCU_GATE(CLK_DRAM_CSI0, "dram-csi0", "pll_ddr", 0x100, 1)
 188         CCU_GATE(CLK_DRAM_CSI1, "dram-csi1", "pll_ddr", 0x100, 2)
 189         CCU_GATE(CLK_DRAM_TS, "dram-ts", "pll_ddr", 0x100, 3)
 190         CCU_GATE(CLK_DRAM_TVD, "dram-tvd", "pll_ddr", 0x100, 4)
 191         CCU_GATE(CLK_DRAM_TVE0, "dram-tve0", "pll_ddr", 0x100, 5)
 192         CCU_GATE(CLK_DRAM_TVE1, "dram-tve1", "pll_ddr", 0x100, 6)
 193         CCU_GATE(CLK_DRAM_OUT, "dram-out", "pll_ddr", 0x100, 15)
 194         CCU_GATE(CLK_DRAM_DE_FE1, "dram-de_fe1", "pll_ddr", 0x100, 24)
 195         CCU_GATE(CLK_DRAM_DE_FE0, "dram-de_fe0", "pll_ddr", 0x100, 25)
 196         CCU_GATE(CLK_DRAM_DE_BE0, "dram-de_be0", "pll_ddr", 0x100, 26)
 197         CCU_GATE(CLK_DRAM_DE_BE1, "dram-de_be1", "pll_ddr", 0x100, 27)
 198         CCU_GATE(CLK_DRAM_MP, "dram-de_mp", "pll_ddr", 0x100, 28)
 199         CCU_GATE(CLK_DRAM_ACE, "dram-ace", "pll_ddr", 0x100, 29)
 200 };
 201
 202 static const char *pll_parents[] = {"osc24M"};
 203 NKMP_CLK(pll_core_clk,
 204     CLK_PLL_CORE,                               /* id */
 205     "pll_core", pll_parents,                    /* name, parents */
 206     0x00,                                       /* offset */
 207     8, 5, 0, AW_CLK_FACTOR_ZERO_IS_ONE,         /* n factor */
 208     4, 2, 0, 0,                                 /* k factor */
 209     0, 2, 0, 0,                                 /* m factor */
 210     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* p factor */
 211     31,                                         /* gate */
 212     0, 0,                                       /* lock */
 213     AW_CLK_HAS_GATE);                           /* flags */
 214
 215 FRAC_CLK(pll_video0_clk,
 216     CLK_PLL_VIDEO0,                             /* id */
 217     "pll_video0", pll_parents,                  /* name, parents */
 218     0x10,                                       /* offset */
 219     0, 7, 0, 0,                                 /* n factor */
 220     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* m factor (fake) */
 221     31, 0, 0,                                   /* gate, lock, lock retries */
 222     AW_CLK_HAS_GATE,                            /* flags */
 223     270000000, 297000000,                       /* freq0, freq1 */
 224     15, 14);                                    /* mode sel, freq sel */
 225 static const char *pll_video0_2x_parents[] = {"pll_video0"};
 226 FIXED_CLK(pll_video0_2x_clk,
 227     CLK_PLL_VIDEO0_2X,                          /* id */
 228     "pll_video0-2x", pll_video0_2x_parents,     /* name, parents */
 229     0,                                          /* freq */
 230     2,                                          /* mult */
 231     1,                                          /* div */
 232     0);                                         /* flags */
 233
 234 FRAC_CLK(pll_video1_clk,
 235     CLK_PLL_VIDEO1,                             /* id */
 236     "pll_video1", pll_parents,                  /* name, parents */
 237     0x30,                                       /* offset */
 238     0, 7, 0, 0,                                 /* n factor */
 239     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* m factor (fake) */
 240     31, 0, 0,                                   /* gate, lock, lock retries */
 241     AW_CLK_HAS_GATE,                            /* flags */
 242     270000000, 297000000,                       /* freq0, freq1 */
 243     15, 14);                                    /* mode sel, freq sel */
 244 static const char *pll_video1_2x_parents[] = {"pll_video1"};
 245 FIXED_CLK(pll_video1_2x_clk,
 246     CLK_PLL_VIDEO1_2X,                          /* id */
 247     "pll_video1-2x", pll_video1_2x_parents,     /* name, parents */
 248     0,                                          /* freq */
 249     2,                                          /* mult */
 250     1,                                          /* div */
 251     0);                                         /* flags */
 252
 253 static const char *cpu_parents[] = {"osc32k", "osc24M", "pll_core", "pll_periph"};
 254 static const char *axi_parents[] = {"cpu"};
 255 static const char *ahb_parents[] = {"axi", "pll_periph", "pll6"};
 256 static const char *apb0_parents[] = {"ahb"};
 257 static const char *apb1_parents[] = {"osc24M", "pll_periph", "osc32k"};
 258 MUX_CLK(cpu_clk,
 259     CLK_CPU,                                    /* id */
 260     "cpu", cpu_parents,                         /* name, parents */
 261     0x54, 16, 2);                               /* offset, shift, width */
 262 NM_CLK(axi_clk,
 263     CLK_AXI,                                    /* id */
 264     "axi", axi_parents,                         /* name, parents */
 265     0x54,                                       /* offset */
 266     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 267     0, 2, 0, 0,                                 /* m factor */
 268     0, 0,                                       /* mux */
 269     0,                                          /* gate */
 270     0);                                         /* flags */
 271 NM_CLK(ahb_clk,
 272     CLK_AHB,                                    /* id */
 273     "ahb", ahb_parents,                         /* name, parents */
 274     0x54,                                       /* offset */
 275     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 276     4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,        /* m factor */
 277     6, 2,                                       /* mux */
 278     0,                                          /* gate */
 279     AW_CLK_HAS_MUX);                            /* flags */
 280 NM_CLK(apb0_clk,
 281     CLK_APB0,                                   /* id */
 282     "apb0", apb0_parents,                       /* name, parents */
 283     0x54,                                       /* offset */
 284     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 285     8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO |
 286     AW_CLK_FACTOR_ZERO_IS_ONE,                  /* m factor */
 287     0, 0,                                       /* mux */
 288     0,                                          /* gate */
 289     0);                                         /* flags */
 290
 291 NM_CLK(apb1_clk,
 292     CLK_APB1,                                   /* id */
 293     "apb1", apb1_parents,                       /* name, parents */
 294     0x58,                                       /* offset */
 295     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 296     0, 5, 0, 0,                                 /* m factor */
 297     24, 2,                                      /* mux */
 298     0,                                          /* gate */
 299     AW_CLK_HAS_MUX);                            /* flags */
 300
 301
 302 NKMP_CLK(pll_ddr_other_clk,
 303     CLK_PLL_DDR_OTHER,                          /* id */
 304     "pll_ddr_other", pll_parents,               /* name, parents */
 305     0x20,                                       /* offset */
 306     8, 5, 0, AW_CLK_FACTOR_ZERO_BASED,          /* n factor */
 307     4, 2, 0, 0,                                 /* k factor */
 308     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* m factor (fake) */
 309     2, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,        /* p factor */
 310     31,                                         /* gate */
 311     0, 0,                                       /* lock */
 312     AW_CLK_HAS_GATE);                           /* flags */
 313 NKMP_CLK(pll_ddr_clk,
 314     CLK_PLL_DDR,                                /* id */
 315     "pll_ddr", pll_parents,                     /* name, parents */
 316     0x20,                                       /* offset */
 317     8, 5, 0, AW_CLK_FACTOR_ZERO_BASED,          /* n factor */
 318     4, 2, 0, 0,                                 /* k factor */
 319     0, 2, 0, 0,                                 /* m factor */
 320     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* p factor (fake) */
 321     31,                                         /* gate */
 322     0, 0,                                       /* lock */
 323     AW_CLK_HAS_GATE);                           /* flags */
 324
 325 NKMP_CLK(pll6_clk,
 326     CLK_PLL6,                                   /* id */
 327     "pll6", pll_parents,                        /* name, parents */
 328     0x28,                                       /* offset */
 329     8, 5, 0, AW_CLK_FACTOR_ZERO_BASED,          /* n factor */
 330     4, 2, 0, 0,                                 /* k factor */
 331     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* m factor (fake) */
 332     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* p factor (fake) */
 333     31,                                         /* gate */
 334     0, 0,                                       /* lock */
 335     AW_CLK_HAS_GATE);                           /* flags */
 336
 337 static const char *pll6_parents[] = {"pll6"};
 338 FIXED_CLK(pll_periph_clk,
 339     CLK_PLL_PERIPH,                             /* id */
 340     "pll_periph", pll6_parents,                 /* name, parents */
 341     0,                                          /* freq */
 342     1,                                          /* mult */
 343     2,                                          /* div */
 344     0);                                         /* flags */
 345 NKMP_CLK(pll_periph_sata_clk,
 346     CLK_PLL_SATA,                               /* id */
 347     "pll_periph_sata", pll6_parents,            /* name, parents */
 348     0x28,                                       /* offset */
 349     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 350     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* k factor (fake) */
 351     0, 2, 0, 0,                                 /* m factor */
 352     0, 0, 6, AW_CLK_FACTOR_FIXED,               /* p factor (fake, 6) */
 353     14,                                         /* gate */
 354     0, 0,                                       /* lock */
 355     AW_CLK_HAS_GATE);                           /* flags */
 356
 357 static const char *mod_parents[] = {"osc24M", "pll_periph", "pll_ddr_other"};
 358 NM_CLK(nand_clk,
 359     CLK_NAND,                                   /* id */
 360     "nand", mod_parents,                        /* name, parents */
 361     0x80,                                       /* offset */
 362     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 363     0, 4, 0, 0,                                 /* m factor */
 364     24, 2,                                      /* mux */
 365     31,                                         /* gate */
 366     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 367
 368 NM_CLK(ms_clk,
 369     CLK_MS,                                     /* id */
 370     "ms", mod_parents,                          /* name, parents */
 371     0x84,                                       /* offset */
 372     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 373     0, 4, 0, 0,                                 /* m factor */
 374     24, 2,                                      /* mux */
 375     31,                                         /* gate */
 376     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 377
 378 NM_CLK(mmc0_clk,
 379     CLK_MMC0,                                   /* id */
 380     "mmc0", mod_parents,                        /* name, parents */
 381     0x88,                                       /* offset */
 382     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 383     0, 4, 0, 0,                                 /* m factor */
 384     24, 2,                                      /* mux */
 385     31,                                         /* gate */
 386     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE |
 387     AW_CLK_REPARENT);                           /* flags */
 388
 389 NM_CLK(mmc1_clk,
 390     CLK_MMC1,                                   /* id */
 391     "mmc1", mod_parents,                        /* name, parents */
 392     0x8c,                                       /* offset */
 393     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 394     0, 4, 0, 0,                                 /* m factor */
 395     24, 2,                                      /* mux */
 396     31,                                         /* gate */
 397     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE |
 398     AW_CLK_REPARENT);                           /* flags */
 399
 400 NM_CLK(mmc2_clk,
 401     CLK_MMC2,                                   /* id */
 402     "mmc2", mod_parents,                        /* name, parents */
 403     0x90,                                       /* offset */
 404     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 405     0, 4, 0, 0,                                 /* m factor */
 406     24, 2,                                      /* mux */
 407     31,                                         /* gate */
 408     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE |
 409     AW_CLK_REPARENT);                           /* flags */
 410
 411 NM_CLK(mmc3_clk,
 412     CLK_MMC3,                                   /* id */
 413     "mmc3", mod_parents,                        /* name, parents */
 414     0x94,                                       /* offset */
 415     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 416     0, 4, 0, 0,                                 /* m factor */
 417     24, 2,                                      /* mux */
 418     31,                                         /* gate */
 419     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE |
 420     AW_CLK_REPARENT);                           /* flags */
 421
 422 NM_CLK(ts_clk,
 423     CLK_TS,                                     /* id */
 424     "ts", mod_parents,                          /* name, parents */
 425     0x94,                                       /* offset */
 426     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 427     0, 4, 0, 0,                                 /* m factor */
 428     24, 2,                                      /* mux */
 429     31,                                         /* gate */
 430     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 431
 432 NM_CLK(ss_clk,
 433     CLK_SS,                                     /* id */
 434     "ss", mod_parents,                          /* name, parents */
 435     0x9c,                                       /* offset */
 436     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 437     0, 4, 0, 0,                                 /* m factor */
 438     24, 2,                                      /* mux */
 439     31,                                         /* gate */
 440     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 441
 442 NM_CLK(spi0_clk,
 443     CLK_SPI0,                                   /* id */
 444     "spi0", mod_parents,                        /* name, parents */
 445     0xa0,                                       /* offset */
 446     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 447     0, 4, 0, 0,                                 /* m factor */
 448     24, 2,                                      /* mux */
 449     31,                                         /* gate */
 450     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 451
 452 NM_CLK(spi1_clk,
 453     CLK_SPI1,                                   /* id */
 454     "spi1", mod_parents,                        /* name, parents */
 455     0xa4,                                       /* offset */
 456     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 457     0, 4, 0, 0,                                 /* m factor */
 458     24, 2,                                      /* mux */
 459     31,                                         /* gate */
 460     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 461
 462 NM_CLK(spi2_clk,
 463     CLK_SPI2,                                   /* id */
 464     "spi2", mod_parents,                        /* name, parents */
 465     0xa8,                                       /* offset */
 466     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 467     0, 4, 0, 0,                                 /* m factor */
 468     24, 2,                                      /* mux */
 469     31,                                         /* gate */
 470     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 471
 472 /* MISSING CLK_PATA */
 473
 474 NM_CLK(ir0_clk,
 475     CLK_IR0,                                    /* id */
 476     "ir0", mod_parents,                         /* name, parents */
 477     0xb0,                                       /* offset */
 478     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 479     0, 4, 0, 0,                                 /* m factor */
 480     24, 2,                                      /* mux */
 481     31,                                         /* gate */
 482     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 483
 484 NM_CLK(ir1_clk,
 485     CLK_IR1,                                    /* id */
 486     "ir1", mod_parents,                         /* name, parents */
 487     0xb4,                                       /* offset */
 488     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 489     0, 4, 0, 0,                                 /* m factor */
 490     24, 2,                                      /* mux */
 491     31,                                         /* gate */
 492     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 493
 494 /* MISSING CLK_I2S0, CLK_AC97, CLK_SPDIF */
 495
 496 static const char *keypad_parents[] = {"osc24M", "osc24M", "osc32k"};
 497 NM_CLK(keypad_clk,
 498     CLK_KEYPAD,                                 /* id */
 499     "keypad", keypad_parents,                   /* name, parents */
 500     0xc4,                                       /* offset */
 501     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 502     0, 5, 0, 0,                                 /* m factor */
 503     24, 2,                                      /* mux */
 504     31,                                         /* gate */
 505     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 506
 507 static const char *sata_parents[] = {"pll_periph_sata", "osc32k"};
 508 NM_CLK(sata_clk,
 509     CLK_SATA,                                   /* id */
 510     "sata", sata_parents,                       /* name, parents */
 511     0xc8,                                       /* offset */
 512     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 513     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* m factor (fake) */
 514     24, 1,                                      /* mux */
 515     31,                                         /* gate */
 516     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 517
 518 NM_CLK(spi3_clk,
 519     CLK_SPI3,                                   /* id */
 520     "spi3", mod_parents,                                /* name, parents */
 521     0xd4,                                       /* offset */
 522     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 523     0, 4, 0, 0,                                 /* m factor */
 524     24, 2,                                      /* mux */
 525     31,                                         /* gate */
 526     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 527
 528 /* MISSING CLK_I2S1, CLK_I2S2, DE Clocks */
 529
 530 static struct aw_ccung_clk a10_ccu_clks[] = {
 531         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_core_clk},
 532         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_other_clk},
 533         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_clk},
 534         { .type = AW_CLK_NKMP, .clk.nkmp = &pll6_clk},
 535         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph_sata_clk},
 536         { .type = AW_CLK_NM, .clk.nm = &axi_clk},
 537         { .type = AW_CLK_NM, .clk.nm = &ahb_clk},
 538         { .type = AW_CLK_NM, .clk.nm = &apb0_clk},
 539         { .type = AW_CLK_NM, .clk.nm = &apb1_clk},
 540         { .type = AW_CLK_FRAC, .clk.frac = &pll_video0_clk},
 541         { .type = AW_CLK_FRAC, .clk.frac = &pll_video1_clk},
 542         { .type = AW_CLK_NM, .clk.nm = &nand_clk},
 543         { .type = AW_CLK_NM, .clk.nm = &ms_clk},
 544         { .type = AW_CLK_NM, .clk.nm = &mmc0_clk},
 545         { .type = AW_CLK_NM, .clk.nm = &mmc1_clk},
 546         { .type = AW_CLK_NM, .clk.nm = &mmc2_clk},
 547         { .type = AW_CLK_NM, .clk.nm = &mmc3_clk},
 548         { .type = AW_CLK_NM, .clk.nm = &ts_clk},
 549         { .type = AW_CLK_NM, .clk.nm = &ss_clk},
 550         { .type = AW_CLK_NM, .clk.nm = &spi0_clk},
 551         { .type = AW_CLK_NM, .clk.nm = &spi1_clk},
 552         { .type = AW_CLK_NM, .clk.nm = &spi2_clk},
 553         { .type = AW_CLK_NM, .clk.nm = &ir0_clk},
 554         { .type = AW_CLK_NM, .clk.nm = &ir1_clk},
 555         { .type = AW_CLK_NM, .clk.nm = &keypad_clk},
 556         { .type = AW_CLK_NM, .clk.nm = &sata_clk},
 557         { .type = AW_CLK_NM, .clk.nm = &spi3_clk},
 558         { .type = AW_CLK_MUX, .clk.mux = &cpu_clk},
 559         { .type = AW_CLK_FIXED, .clk.fixed = &pll_periph_clk},
 560         { .type = AW_CLK_FIXED, .clk.fixed = &pll_video0_2x_clk},
 561         { .type = AW_CLK_FIXED, .clk.fixed = &pll_video1_2x_clk},
 562 };
 563
 564 static struct aw_clk_init a10_init_clks[] = {
 565 };
 566
 567 static struct ofw_compat_data compat_data[] = {
 568 #if defined(SOC_ALLWINNER_A10)
 569         { "allwinner,sun4i-a10-ccu", 1 },
 570 #endif
 571 #if defined(SOC_ALLWINNER_A20)
 572         { "allwinner,sun7i-a20-ccu", 1 },
 573 #endif
 574         { NULL, 0},
 575 };
 576
 577 static int
 578 ccu_a10_probe(device_t dev)
 579 {
 580
 581         if (!ofw_bus_status_okay(dev))
 582                 return (ENXIO);
 583
 584         if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
 585                 return (ENXIO);
 586
 587         device_set_desc(dev, "Allwinner A10/A20 Clock Control Unit NG");
 588         return (BUS_PROBE_DEFAULT);
 589 }
 590
 591 static int
 592 ccu_a10_attach(device_t dev)
 593 {
 594         struct aw_ccung_softc *sc;
 595
 596         sc = device_get_softc(dev);
 597
 598         sc->resets = a10_ccu_resets;
 599         sc->nresets = nitems(a10_ccu_resets);
 600         sc->gates = a10_ccu_gates;
 601         sc->ngates = nitems(a10_ccu_gates);
 602         sc->clks = a10_ccu_clks;
 603         sc->nclks = nitems(a10_ccu_clks);
 604         sc->clk_init = a10_init_clks;
 605         sc->n_clk_init = nitems(a10_init_clks);
 606
 607         return (aw_ccung_attach(dev));
 608 }
 609
 610 static device_method_t ccu_a10ng_methods[] = {
 611         /* Device interface */
 612         DEVMETHOD(device_probe,         ccu_a10_probe),
 613         DEVMETHOD(device_attach,        ccu_a10_attach),
 614
 615         DEVMETHOD_END
 616 };
 617
 618 static devclass_t ccu_a10ng_devclass;
 619
 620 DEFINE_CLASS_1(ccu_a10ng, ccu_a10ng_driver, ccu_a10ng_methods,
 621   sizeof(struct aw_ccung_softc), aw_ccung_driver);
 622
 623 EARLY_DRIVER_MODULE(ccu_a10ng, simplebus, ccu_a10ng_driver,
 624     ccu_a10ng_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);