sys/arm/allwinner/clkng/ccu_a13.c

   1 /*-
   2  * Copyright (c) 2017 Emmanuel Vadot <manu@freebsd.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  15  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  16  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  17  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  18  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  19  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  20  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  21  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  22  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  * $FreeBSD$
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __FBSDID("$FreeBSD$");
  31
  32 #include <sys/param.h>
  33 #include <sys/systm.h>
  34 #include <sys/bus.h>
  35
  36 #include <dev/extres/clk/clk_div.h>
  37 #include <dev/extres/clk/clk_fixed.h>
  38 #include <dev/extres/clk/clk_mux.h>
  39
  40 #include <arm/allwinner/clkng/aw_ccung.h>
  41 #include <arm/allwinner/clkng/aw_clk.h>
  42 #include <arm/allwinner/clkng/aw_clk_nm.h>
  43 #include <arm/allwinner/clkng/aw_clk_nkmp.h>
  44 #include <arm/allwinner/clkng/aw_clk_prediv_mux.h>
  45
  46 #include <dt-bindings/clock/sun5i-ccu.h>
  47 #include <dt-bindings/reset/sun5i-ccu.h>
  48
  49 #include "ccu_a13.h"
  50
  51 /* Non-exported clocks */
  52
  53 #define CLK_PLL_CORE            2
  54 #define CLK_PLL_AUDIO_BASE      3
  55 #define CLK_PLL_AUDIO           4
  56 #define CLK_PLL_AUDIO_2X        5
  57 #define CLK_PLL_AUDIO_4X        6
  58 #define CLK_PLL_AUDIO_8X        7
  59 #define CLK_PLL_VIDEO0          8
  60
  61 #define CLK_PLL_VE              10
  62 #define CLK_PLL_DDR_BASE        11
  63 #define CLK_PLL_DDR             12
  64 #define CLK_PLL_DDR_OTHER       13
  65 #define CLK_PLL_PERIPH          14
  66 #define CLK_PLL_VIDEO1          15
  67
  68 #define CLK_AXI                 18
  69 #define CLK_AHB                 19
  70 #define CLK_APB0                20
  71 #define CLK_APB1                21
  72 #define CLK_DRAM_AXI            22
  73
  74 #define CLK_TCON_CH1_SCLK       91
  75
  76 #define CLK_MBUS                99
  77
  78 static struct aw_ccung_reset a13_ccu_resets[] = {
  79         CCU_RESET(RST_USB_PHY0, 0xcc, 0)
  80         CCU_RESET(RST_USB_PHY1, 0xcc, 1)
  81
  82         CCU_RESET(RST_GPS, 0xd0, 30)
  83
  84         CCU_RESET(RST_DE_BE, 0x104, 30)
  85
  86         CCU_RESET(RST_DE_FE, 0x10c, 30)
  87
  88         CCU_RESET(RST_TVE, 0x118, 29)
  89         CCU_RESET(RST_LCD, 0x118, 30)
  90
  91         CCU_RESET(RST_CSI, 0x134, 30)
  92
  93         CCU_RESET(RST_VE, 0x13c, 0)
  94         CCU_RESET(RST_GPU, 0x154, 30)
  95         CCU_RESET(RST_IEP, 0x160, 30)
  96
  97 };
  98
  99 static struct aw_ccung_gate a13_ccu_gates[] = {
 100         CCU_GATE(CLK_HOSC, "hosc", "osc24M", 0x50, 0)
 101
 102         CCU_GATE(CLK_DRAM_AXI, "axi-dram", "axi", 0x5c, 0)
 103
 104         CCU_GATE(CLK_AHB_OTG, "ahb-otg", "ahb", 0x60, 0)
 105         CCU_GATE(CLK_AHB_EHCI, "ahb-ehci", "ahb", 0x60, 1)
 106         CCU_GATE(CLK_AHB_OHCI, "ahb-ohci", "ahb", 0x60, 2)
 107         CCU_GATE(CLK_AHB_SS, "ahb-ss", "ahb", 0x60, 5)
 108         CCU_GATE(CLK_AHB_DMA, "ahb-dma", "ahb", 0x60, 6)
 109         CCU_GATE(CLK_AHB_BIST, "ahb-bist", "ahb", 0x60, 7)
 110         CCU_GATE(CLK_AHB_MMC0, "ahb-mmc0", "ahb", 0x60, 8)
 111         CCU_GATE(CLK_AHB_MMC1, "ahb-mmc1", "ahb", 0x60, 9)
 112         CCU_GATE(CLK_AHB_MMC2, "ahb-mmc2", "ahb", 0x60, 10)
 113         CCU_GATE(CLK_AHB_NAND, "ahb-nand", "ahb", 0x60, 13)
 114         CCU_GATE(CLK_AHB_SDRAM, "ahb-sdram", "ahb", 0x60, 14)
 115         CCU_GATE(CLK_AHB_SPI0, "ahb-spi0", "ahb", 0x60, 20)
 116         CCU_GATE(CLK_AHB_SPI1, "ahb-spi1", "ahb", 0x60, 21)
 117         CCU_GATE(CLK_AHB_SPI2, "ahb-spi2", "ahb", 0x60, 22)
 118         CCU_GATE(CLK_AHB_GPS, "ahb-gps", "ahb", 0x60, 26)
 119         CCU_GATE(CLK_AHB_HSTIMER, "ahb-hstimer", "ahb", 0x60, 28)
 120
 121         CCU_GATE(CLK_AHB_VE, "ahb-ve", "ahb", 0x64, 0)
 122         CCU_GATE(CLK_AHB_LCD, "ahb-lcd", "ahb", 0x64, 4)
 123         CCU_GATE(CLK_AHB_CSI, "ahb-csi", "ahb", 0x64, 8)
 124         CCU_GATE(CLK_AHB_DE_BE, "ahb-de-be", "ahb", 0x64, 12)
 125         CCU_GATE(CLK_AHB_DE_FE, "ahb-de-fe", "ahb", 0x64, 14)
 126         CCU_GATE(CLK_AHB_IEP, "ahb-iep", "ahb", 0x64, 19)
 127         CCU_GATE(CLK_AHB_GPU, "ahb-gpu", "ahb", 0x64, 20)
 128
 129         CCU_GATE(CLK_APB0_CODEC, "apb0-codec", "apb0", 0x68, 0)
 130         CCU_GATE(CLK_APB0_PIO, "apb0-pio", "apb0", 0x68, 5)
 131         CCU_GATE(CLK_APB0_IR, "apb0-ir", "apb0", 0x68, 6)
 132
 133         CCU_GATE(CLK_APB1_I2C0, "apb1-i2c0", "apb1", 0x6c, 0)
 134         CCU_GATE(CLK_APB1_I2C1, "apb1-i2c1", "apb1", 0x6c, 1)
 135         CCU_GATE(CLK_APB1_I2C2, "apb1-i2c2", "apb1", 0x6c, 2)
 136         CCU_GATE(CLK_APB1_UART1, "apb1-uart1", "apb1", 0x6c, 17)
 137         CCU_GATE(CLK_APB1_UART3, "apb1-uart3", "apb1", 0x6c, 19)
 138
 139         CCU_GATE(CLK_DRAM_VE, "dram-ve", "pll-ddr", 0x100, 0)
 140         CCU_GATE(CLK_DRAM_CSI, "dram-csi", "pll-ddr", 0x100, 1)
 141         CCU_GATE(CLK_DRAM_DE_FE, "dram-de-fe", "pll-ddr", 0x100, 25)
 142         CCU_GATE(CLK_DRAM_DE_BE, "dram-de-be", "pll-ddr", 0x100, 26)
 143         CCU_GATE(CLK_DRAM_ACE, "dram-ace", "pll-ddr", 0x100, 29)
 144         CCU_GATE(CLK_DRAM_IEP, "dram-iep", "pll-ddr", 0x100, 31)
 145
 146         CCU_GATE(CLK_CODEC, "codec", "pll-audio", 0x140, 31)
 147
 148         CCU_GATE(CLK_AVS, "avs", "hosc", 0x144, 31)
 149 };
 150
 151 static const char *pll_parents[] = {"hosc"};
 152 static struct aw_clk_nkmp_def pll_core = {
 153         .clkdef = {
 154                 .id = CLK_PLL_CORE,
 155                 .name = "pll-core",
 156                 .parent_names = pll_parents,
 157                 .parent_cnt = nitems(pll_parents),
 158         },
 159         .offset = 0x00,
 160         .n = {.shift = 8, .width = 5},
 161         .k = {.shift = 4, .width = 2},
 162         .m = {.shift = 0, .width = 2},
 163         .p = {.shift = 16, .width = 2},
 164         .gate_shift = 31,
 165         .flags = AW_CLK_HAS_GATE,
 166 };
 167
 168 /*
 169  * We only implement pll-audio for now
 170  * For pll-audio-2/4/8 x we need a way to change the frequency
 171  * of the parent clocks
 172  */
 173 static struct aw_clk_nkmp_def pll_audio = {
 174         .clkdef = {
 175                 .id = CLK_PLL_AUDIO,
 176                 .name = "pll-audio",
 177                 .parent_names = pll_parents,
 178                 .parent_cnt = nitems(pll_parents),
 179         },
 180         .offset = 0x08,
 181         .n = {.shift = 8, .width = 7},
 182         .k = {.value = 1, .flags = AW_CLK_FACTOR_FIXED},
 183         .m = {.shift = 0, .width = 5},
 184         .p = {.shift = 26, .width = 4},
 185         .gate_shift = 31,
 186         .flags = AW_CLK_HAS_GATE,
 187 };
 188
 189 /* Missing PLL3-Video */
 190 /* Missing PLL4-VE */
 191
 192 static struct aw_clk_nkmp_def pll_ddr_base = {
 193         .clkdef = {
 194                 .id = CLK_PLL_DDR_BASE,
 195                 .name = "pll-ddr-base",
 196                 .parent_names = pll_parents,
 197                 .parent_cnt = nitems(pll_parents),
 198         },
 199         .offset = 0x20,
 200         .n = {.shift = 8, .width = 5},
 201         .k = {.shift = 4, .width = 2},
 202         .m = {.value = 1, .flags = AW_CLK_FACTOR_FIXED},
 203         .p = {.value = 1, .flags = AW_CLK_FACTOR_FIXED},
 204         .gate_shift = 31,
 205         .flags = AW_CLK_HAS_GATE,
 206 };
 207
 208 static const char *pll_ddr_parents[] = {"pll-ddr-base"};
 209 static struct clk_div_def pll_ddr = {
 210         .clkdef = {
 211                 .id = CLK_PLL_DDR,
 212                 .name = "pll-ddr",
 213                 .parent_names = pll_ddr_parents,
 214                 .parent_cnt = nitems(pll_ddr_parents),
 215         },
 216         .offset = 0x20,
 217         .i_shift = 0,
 218         .i_width = 2,
 219 };
 220
 221 static const char *pll_ddr_other_parents[] = {"pll-ddr-base"};
 222 static struct clk_div_def pll_ddr_other = {
 223         .clkdef = {
 224                 .id = CLK_PLL_DDR_OTHER,
 225                 .name = "pll-ddr-other",
 226                 .parent_names = pll_ddr_other_parents,
 227                 .parent_cnt = nitems(pll_ddr_other_parents),
 228         },
 229         .offset = 0x20,
 230         .i_shift = 16,
 231         .i_width = 2,
 232 };
 233
 234 static struct aw_clk_nkmp_def pll_periph = {
 235         .clkdef = {
 236                 .id = CLK_PLL_PERIPH,
 237                 .name = "pll-periph",
 238                 .parent_names = pll_parents,
 239                 .parent_cnt = nitems(pll_parents),
 240         },
 241         .offset = 0x28,
 242         .n = {.shift = 8, .width = 5},
 243         .k = {.shift = 4, .width = 2},
 244         .m = {.shift = 0, .width = 2},
 245         .p = {.value = 2, .flags = AW_CLK_FACTOR_FIXED},
 246         .gate_shift = 31,
 247         .flags = AW_CLK_HAS_GATE,
 248 };
 249
 250 /* Missing PLL7-VIDEO1 */
 251
 252 static const char *cpu_parents[] = {"osc32k", "hosc", "pll-core", "pll-periph"};
 253 static struct aw_clk_prediv_mux_def cpu_clk = {
 254         .clkdef = {
 255                 .id = CLK_CPU,
 256                 .name = "cpu",
 257                 .parent_names = cpu_parents,
 258                 .parent_cnt = nitems(cpu_parents),
 259         },
 260         .offset = 0x54,
 261         .mux_shift = 16, .mux_width = 2,
 262         .prediv = {
 263                 .value = 6,
 264                 .flags = AW_CLK_FACTOR_FIXED,
 265                 .cond_shift = 16,
 266                 .cond_width = 2,
 267                 .cond_value = 3,
 268         },
 269 };
 270
 271 static const char *axi_parents[] = {"cpu"};
 272 static struct clk_div_def axi_clk = {
 273         .clkdef = {
 274                 .id = CLK_AXI,
 275                 .name = "axi",
 276                 .parent_names = axi_parents,
 277                 .parent_cnt = nitems(axi_parents),
 278         },
 279         .offset = 0x50,
 280         .i_shift = 0, .i_width = 2,
 281 };
 282
 283 static const char *ahb_parents[] = {"axi", "cpu", "pll-periph"};
 284 static struct aw_clk_prediv_mux_def ahb_clk = {
 285         .clkdef = {
 286                 .id = CLK_AHB,
 287                 .name = "ahb",
 288                 .parent_names = ahb_parents,
 289                 .parent_cnt = nitems(ahb_parents),
 290         },
 291         .offset = 0x54,
 292         .mux_shift = 6,
 293         .mux_width = 2,
 294         .div = {
 295                 .shift = 4,
 296                 .width = 2,
 297                 .flags = AW_CLK_FACTOR_POWER_OF_TWO
 298         },
 299         .prediv = {
 300                 .value = 2,
 301                 .flags = AW_CLK_FACTOR_FIXED,
 302                 .cond_shift = 6,
 303                 .cond_width = 2,
 304                 .cond_value = 2,
 305         },
 306 };
 307
 308 static const char *apb0_parents[] = {"ahb"};
 309 static struct clk_div_table apb0_div_table[] = {
 310         { .value = 0, .divider = 2, },
 311         { .value = 1, .divider = 2, },
 312         { .value = 2, .divider = 4, },
 313         { .value = 3, .divider = 8, },
 314         { },
 315 };
 316 static struct clk_div_def apb0_clk = {
 317         .clkdef = {
 318                 .id = CLK_APB0,
 319                 .name = "apb0",
 320                 .parent_names = apb0_parents,
 321                 .parent_cnt = nitems(apb0_parents),
 322         },
 323         .offset = 0x54,
 324         .i_shift = 8, .i_width = 2,
 325         .div_flags = CLK_DIV_WITH_TABLE,
 326         .div_table = apb0_div_table,
 327 };
 328
 329 static const char *apb1_parents[] = {"hosc", "pll-periph", "osc32k"};
 330 static struct aw_clk_nm_def apb1_clk = {
 331         .clkdef = {
 332                 .id = CLK_APB1,
 333                 .name = "apb1",
 334                 .parent_names = apb1_parents,
 335                 .parent_cnt = nitems(apb1_parents),
 336         },
 337         .offset = 0x58,
 338         .n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, },
 339         .m = {.shift = 0, .width = 5},
 340         .mux_shift = 24,
 341         .mux_width = 2,
 342         .flags = AW_CLK_HAS_MUX,
 343 };
 344
 345 static const char *mod_parents[] = {"hosc", "pll-periph", "pll-ddr-other"};
 346
 347 static struct aw_clk_nm_def nand_clk = {
 348         .clkdef = {
 349                 .id = CLK_NAND,
 350                 .name = "nand",
 351                 .parent_names = mod_parents,
 352                 .parent_cnt = nitems(mod_parents),
 353         },
 354         .offset = 0x80,
 355         .n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, },
 356         .m = {.shift = 0, .width = 4},
 357         .mux_shift = 24,
 358         .mux_width = 2,
 359         .gate_shift = 31,
 360         .flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT
 361 };
 362
 363 static struct aw_clk_nm_def mmc0_clk = {
 364         .clkdef = {
 365                 .id = CLK_MMC0,
 366                 .name = "mmc0",
 367                 .parent_names = mod_parents,
 368                 .parent_cnt = nitems(mod_parents),
 369         },
 370         .offset = 0x88,
 371         .n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, },
 372         .m = {.shift = 0, .width = 4},
 373         .mux_shift = 24,
 374         .mux_width = 2,
 375         .gate_shift = 31,
 376         .flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT
 377 };
 378
 379 static struct aw_clk_nm_def mmc1_clk = {
 380         .clkdef = {
 381                 .id = CLK_MMC1,
 382                 .name = "mmc1",
 383                 .parent_names = mod_parents,
 384                 .parent_cnt = nitems(mod_parents),
 385         },
 386         .offset = 0x8C,
 387         .n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, },
 388         .m = {.shift = 0, .width = 4},
 389         .mux_shift = 24,
 390         .mux_width = 2,
 391         .gate_shift = 31,
 392         .flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT
 393 };
 394
 395 static struct aw_clk_nm_def mmc2_clk = {
 396         .clkdef = {
 397                 .id = CLK_MMC2,
 398                 .name = "mmc2",
 399                 .parent_names = mod_parents,
 400                 .parent_cnt = nitems(mod_parents),
 401         },
 402         .offset = 0x90,
 403         .n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, },
 404         .m = {.shift = 0, .width = 4},
 405         .mux_shift = 24,
 406         .mux_width = 2,
 407         .gate_shift = 31,
 408         .flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT
 409 };
 410
 411 static struct aw_clk_nm_def ss_clk = {
 412         .clkdef = {
 413                 .id = CLK_SS,
 414                 .name = "ss",
 415                 .parent_names = mod_parents,
 416                 .parent_cnt = nitems(mod_parents),
 417         },
 418         .offset = 0x9C,
 419         .n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, },
 420         .m = {.shift = 0, .width = 4},
 421         .mux_shift = 24,
 422         .mux_width = 2,
 423         .gate_shift = 31,
 424         .flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT
 425 };
 426
 427 static struct aw_clk_nm_def spi0_clk = {
 428         .clkdef = {
 429                 .id = CLK_SPI0,
 430                 .name = "spi0",
 431                 .parent_names = mod_parents,
 432                 .parent_cnt = nitems(mod_parents),
 433         },
 434         .offset = 0xA0,
 435         .n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, },
 436         .m = {.shift = 0, .width = 4},
 437         .mux_shift = 24,
 438         .mux_width = 2,
 439         .gate_shift = 31,
 440         .flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT
 441 };
 442
 443 static struct aw_clk_nm_def spi1_clk = {
 444         .clkdef = {
 445                 .id = CLK_SPI1,
 446                 .name = "spi1",
 447                 .parent_names = mod_parents,
 448                 .parent_cnt = nitems(mod_parents),
 449         },
 450         .offset = 0xA4,
 451         .n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, },
 452         .m = {.shift = 0, .width = 4},
 453         .mux_shift = 24,
 454         .mux_width = 2,
 455         .gate_shift = 31,
 456         .flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT
 457 };
 458
 459 static struct aw_clk_nm_def spi2_clk = {
 460         .clkdef = {
 461                 .id = CLK_SPI2,
 462                 .name = "spi2",
 463                 .parent_names = mod_parents,
 464                 .parent_cnt = nitems(mod_parents),
 465         },
 466         .offset = 0xA8,
 467         .n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, },
 468         .m = {.shift = 0, .width = 4},
 469         .mux_shift = 24,
 470         .mux_width = 2,
 471         .gate_shift = 31,
 472         .flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT
 473 };
 474
 475 static struct aw_clk_nm_def ir_clk = {
 476         .clkdef = {
 477                 .id = CLK_IR,
 478                 .name = "ir",
 479                 .parent_names = mod_parents,
 480                 .parent_cnt = nitems(mod_parents),
 481         },
 482         .offset = 0xB0,
 483         .n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, },
 484         .m = {.shift = 0, .width = 4},
 485         .mux_shift = 24,
 486         .mux_width = 2,
 487         .gate_shift = 31,
 488         .flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT
 489 };
 490
 491 /* Missing DE-BE clock */
 492 /* Missing DE-FE clock */
 493 /* Missing LCD CH1 clock */
 494 /* Missing CSI clock */
 495 /* Missing VE clock */
 496
 497
 498 /* Clocks list */
 499
 500 static struct aw_clk_nkmp_def *nkmp_clks[] = {
 501         &pll_core,
 502         &pll_audio,
 503         &pll_ddr_base,
 504         &pll_periph,
 505 };
 506
 507 static struct aw_clk_nm_def *nm_clks[] = {
 508         &apb1_clk,
 509         &nand_clk,
 510         &mmc0_clk,
 511         &mmc1_clk,
 512         &mmc2_clk,
 513         &ss_clk,
 514         &spi0_clk,
 515         &spi1_clk,
 516         &spi2_clk,
 517         &ir_clk,
 518 };
 519
 520 static struct aw_clk_prediv_mux_def *prediv_mux_clks[] = {
 521         &cpu_clk,
 522         &ahb_clk,
 523 };
 524
 525 static struct clk_div_def *div_clks[] = {
 526         &pll_ddr,
 527         &pll_ddr_other,
 528         &axi_clk,
 529         &apb0_clk,
 530 };
 531
 532 static struct clk_mux_def *mux_clks[] = {
 533 };
 534
 535 static struct clk_fixed_def *fixed_factor_clks[] = {
 536 };
 537
 538 static struct aw_clk_init init_clks[] = {
 539 };
 540
 541 void
 542 ccu_a13_register_clocks(struct aw_ccung_softc *sc)
 543 {
 544         int i;
 545
 546         sc->resets = a13_ccu_resets;
 547         sc->nresets = nitems(a13_ccu_resets);
 548         sc->gates = a13_ccu_gates;
 549         sc->ngates = nitems(a13_ccu_gates);
 550         sc->clk_init = init_clks;
 551         sc->n_clk_init = nitems(init_clks);
 552
 553         for (i = 0; i < nitems(nkmp_clks); i++)
 554                 aw_clk_nkmp_register(sc->clkdom, nkmp_clks[i]);
 555         for (i = 0; i < nitems(nm_clks); i++)
 556                 aw_clk_nm_register(sc->clkdom, nm_clks[i]);
 557         for (i = 0; i < nitems(prediv_mux_clks); i++)
 558                 aw_clk_prediv_mux_register(sc->clkdom, prediv_mux_clks[i]);
 559
 560         for (i = 0; i < nitems(mux_clks); i++)
 561                 clknode_mux_register(sc->clkdom, mux_clks[i]);
 562         for (i = 0; i < nitems(div_clks); i++)
 563                 clknode_div_register(sc->clkdom, div_clks[i]);
 564         for (i = 0; i < nitems(fixed_factor_clks); i++)
 565                 clknode_fixed_register(sc->clkdom, fixed_factor_clks[i]);
 566 }