2 * Copyright (c) 2017 Emmanuel Vadot <manu@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #define A31_RST_USB_PHY0 0
33 #define A31_RST_USB_PHY1 1
34 #define A31_RST_USB_PHY2 2
35 #define A31_RST_AHB1_MIPI_DSI 3
36 #define A31_RST_AHB1_SS 4
37 #define A31_RST_AHB1_DMA 5
38 #define A31_RST_AHB1_MMC0 6
39 #define A31_RST_AHB1_MMC1 7
40 #define A31_RST_AHB1_MMC2 8
41 #define A31_RST_AHB1_MMC3 9
42 #define A31_RST_AHB1_NAND1 10
43 #define A31_RST_AHB1_NAND0 11
44 #define A31_RST_AHB1_SDRAM 12
45 #define A31_RST_AHB1_EMAC 13
46 #define A31_RST_AHB1_TS 14
47 #define A31_RST_AHB1_HSTIMER 15
48 #define A31_RST_AHB1_SPI0 16
49 #define A31_RST_AHB1_SPI1 17
50 #define A31_RST_AHB1_SPI2 18
51 #define A31_RST_AHB1_SPI3 19
52 #define A31_RST_AHB1_OTG 20
53 #define A31_RST_AHB1_EHCI0 21
54 #define A31_RST_AHB1_EHCI1 22
55 #define A31_RST_AHB1_OHCI0 23
56 #define A31_RST_AHB1_OHCI1 24
57 #define A31_RST_AHB1_OHCI2 25
58 #define A31_RST_AHB1_VE 26
59 #define A31_RST_AHB1_LCD0 27
60 #define A31_RST_AHB1_LCD1 28
61 #define A31_RST_AHB1_CSI 29
62 #define A31_RST_AHB1_HDMI 30
63 #define A31_RST_AHB1_BE0 31
64 #define A31_RST_AHB1_BE1 32
65 #define A31_RST_AHB1_FE0 33
66 #define A31_RST_AHB1_FE1 34
67 #define A31_RST_AHB1_MP 35
68 #define A31_RST_AHB1_GPU 36
69 #define A31_RST_AHB1_DEU0 37
70 #define A31_RST_AHB1_DEU1 38
71 #define A31_RST_AHB1_DRC0 39
72 #define A31_RST_AHB1_DRC1 40
73 #define A31_RST_AHB1_LVDS 41
74 #define A31_RST_APB1_CODEC 42
75 #define A31_RST_APB1_SPDIF 43
76 #define A31_RST_APB1_DIGITAL_MIC 44
77 #define A31_RST_APB1_DAUDIO0 45
78 #define A31_RST_APB1_DAUDIO1 46
79 #define A31_RST_APB2_I2C0 47
80 #define A31_RST_APB2_I2C1 48
81 #define A31_RST_APB2_I2C2 49
82 #define A31_RST_APB2_I2C3 50
83 #define A31_RST_APB2_UART0 51
84 #define A31_RST_APB2_UART1 52
85 #define A31_RST_APB2_UART2 53
86 #define A31_RST_APB2_UART3 54
87 #define A31_RST_APB2_UART4 55
88 #define A31_RST_APB2_UART5 56
90 #define A31_CLK_PLL_CPU 0
91 #define A31_CLK_PLL_AUDIO_BASE 1
92 #define A31_CLK_PLL_AUDIO 2
93 #define A31_CLK_PLL_AUDIO_2X 3
94 #define A31_CLK_PLL_AUDIO_4X 4
95 #define A31_CLK_PLL_AUDIO_8X 5
96 #define A31_CLK_PLL_VIDEO0 6
97 #define A31_CLK_PLL_VIDEO0_2X 7
98 #define A31_CLK_PLL_VE 8
99 #define A31_CLK_PLL_DDR 9
100 #define A31_CLK_PLL_PERIPH 10
101 #define A31_CLK_PLL_PERIPH_2X 11
102 #define A31_CLK_PLL_VIDEO1 12
103 #define A31_CLK_PLL_VIDEO1_2X 13
104 #define A31_CLK_PLL_GPU 14
105 #define A31_CLK_PLL_MIPI 15
106 #define A31_CLK_PLL9 16
107 #define A31_CLK_PLL10 17
108 #define A31_CLK_CPU 18
109 #define A31_CLK_AXI 19
110 #define A31_CLK_AHB1 20
111 #define A31_CLK_APB1 21
112 #define A31_CLK_APB2 22
113 #define A31_CLK_AHB1_MIPIDSI 23
114 #define A31_CLK_AHB1_SS 24
115 #define A31_CLK_AHB1_DMA 25
116 #define A31_CLK_AHB1_MMC0 26
117 #define A31_CLK_AHB1_MMC1 27
118 #define A31_CLK_AHB1_MMC2 28
119 #define A31_CLK_AHB1_MMC3 29
120 #define A31_CLK_AHB1_NAND1 30
121 #define A31_CLK_AHB1_NAND0 31
122 #define A31_CLK_AHB1_SDRAM 32
123 #define A31_CLK_AHB1_EMAC 33
124 #define A31_CLK_AHB1_TS 34
125 #define A31_CLK_AHB1_HSTIMER 35
126 #define A31_CLK_AHB1_SPI0 36
127 #define A31_CLK_AHB1_SPI1 37
128 #define A31_CLK_AHB1_SPI2 38
129 #define A31_CLK_AHB1_SPI3 39
130 #define A31_CLK_AHB1_OTG 40
131 #define A31_CLK_AHB1_EHCI0 41
132 #define A31_CLK_AHB1_EHCI1 42
133 #define A31_CLK_AHB1_OHCI0 43
134 #define A31_CLK_AHB1_OHCI1 44
135 #define A31_CLK_AHB1_OHCI2 45
136 #define A31_CLK_AHB1_VE 46
137 #define A31_CLK_AHB1_LCD0 47
138 #define A31_CLK_AHB1_LCD1 48
139 #define A31_CLK_AHB1_CSI 49
140 #define A31_CLK_AHB1_HDMI 50
141 #define A31_CLK_AHB1_BE0 51
142 #define A31_CLK_AHB1_BE1 52
143 #define A31_CLK_AHB1_FE0 53
144 #define A31_CLK_AHB1_FE1 54
145 #define A31_CLK_AHB1_MP 55
146 #define A31_CLK_AHB1_GPU 56
147 #define A31_CLK_AHB1_DEU0 57
148 #define A31_CLK_AHB1_DEU1 58
149 #define A31_CLK_AHB1_DRC0 59
150 #define A31_CLK_AHB1_DRC1 60
151 #define A31_CLK_APB1_CODEC 61
152 #define A31_CLK_APB1_SPDIF 62
153 #define A31_CLK_APB1_DIGITAL_MIC 63
154 #define A31_CLK_APB1_PIO 64
155 #define A31_CLK_APB1_DAUDIO0 65
156 #define A31_CLK_APB1_DAUDIO1 66
157 #define A31_CLK_APB2_I2C0 67
158 #define A31_CLK_APB2_I2C1 68
159 #define A31_CLK_APB2_I2C2 69
160 #define A31_CLK_APB2_I2C3 70
161 #define A31_CLK_APB2_UART0 71
162 #define A31_CLK_APB2_UART1 72
163 #define A31_CLK_APB2_UART2 73
164 #define A31_CLK_APB2_UART3 74
165 #define A31_CLK_APB2_UART4 75
166 #define A31_CLK_APB2_UART5 76
167 #define A31_CLK_NAND0 77
168 #define A31_CLK_NAND1 78
169 #define A31_CLK_MMC0 79
170 #define A31_CLK_MMC0_SAMPLE 80
171 #define A31_CLK_MMC0_OUTPUT 81
172 #define A31_CLK_MMC1 82
173 #define A31_CLK_MMC1_SAMPLE 83
174 #define A31_CLK_MMC1_OUTPUT 84
175 #define A31_CLK_MMC2 85
176 #define A31_CLK_MMC2_SAMPLE 86
177 #define A31_CLK_MMC2_OUTPUT 87
178 #define A31_CLK_MMC3 88
179 #define A31_CLK_MMC3_SAMPLE 89
180 #define A31_CLK_MMC3_OUTPUT 90
181 #define A31_CLK_TS 91
182 #define A31_CLK_SS 92
183 #define A31_CLK_SPI0 93
184 #define A31_CLK_SPI1 94
185 #define A31_CLK_SPI2 95
186 #define A31_CLK_SPI3 96
187 #define A31_CLK_DAUDIO0 97
188 #define A31_CLK_DAUDIO1 98
189 #define A31_CLK_SPDIF 99
190 #define A31_CLK_USB_PHY0 100
191 #define A31_CLK_USB_PHY1 101
192 #define A31_CLK_USB_PHY2 102
193 #define A31_CLK_USB_OHCI0 103
194 #define A31_CLK_USB_OHCI1 104
195 #define A31_CLK_USB_OHCI2 105
196 #define A31_CLK_MDFS 107
197 #define A31_CLK_SDRAM0 108
198 #define A31_CLK_SDRAM1 109
199 #define A31_CLK_DRAM_VE 110
200 #define A31_CLK_DRAM_CSI_ISP 111
201 #define A31_CLK_DRAM_TS 112
202 #define A31_CLK_DRAM_DRC0 113
203 #define A31_CLK_DRAM_DRC1 114
204 #define A31_CLK_DRAM_DEU0 115
205 #define A31_CLK_DRAM_DEU1 116
206 #define A31_CLK_DRAM_FE0 117
207 #define A31_CLK_DRAM_FE1 118
208 #define A31_CLK_DRAM_BE0 119
209 #define A31_CLK_DRAM_BE1 120
210 #define A31_CLK_DRAM_MP 121
211 #define A31_CLK_BE0 122
212 #define A31_CLK_BE1 123
213 #define A31_CLK_FE0 124
214 #define A31_CLK_FE1 125
215 #define A31_CLK_MP 126
216 #define A31_CLK_LCD0_CH0 127
217 #define A31_CLK_LCD1_CH0 128
218 #define A31_CLK_LCD0_CH1 129
219 #define A31_CLK_LCD1_CH1 130
220 #define A31_CLK_CSI0_SCLK 131
221 #define A31_CLK_CSI0_MCLK 132
222 #define A31_CLK_CSI1_MCLK 133
223 #define A31_CLK_VE 134
224 #define A31_CLK_CODEC 135
225 #define A31_CLK_AVS 136
226 #define A31_CLK_DIGITAL_MIC 137
227 #define A31_CLK_HDMI 138
228 #define A31_CLK_HDMI_DDC 139
229 #define A31_CLK_PS 140
230 #define A31_CLK_MBUS0 141
231 #define A31_CLK_MBUS1 142
232 #define A31_CLK_MIPI_DSI 143
233 #define A31_CLK_MIPI_DSI_DPHY 144
234 #define A31_CLK_MIPI_CSI_DPHY 145
235 #define A31_CLK_IEP_DRC0 146
236 #define A31_CLK_IEP_DRC1 147
237 #define A31_CLK_IEP_DEU0 148
238 #define A31_CLK_IEP_DEU1 149
239 #define A31_CLK_GPU_CORE 150
240 #define A31_CLK_GPU_MEMORY 151
241 #define A31_CLK_GPU_HYD 152
242 #define A31_CLK_ATS 153
243 #define A31_CLK_TRACE 154
244 #define A31_CLK_OUT_A 155
245 #define A31_CLK_OUT_B 156
246 #define A31_CLK_OUT_C 157
248 void ccu_a31_register_clocks(struct aw_ccung_softc *sc);
250 #endif /* __CCU_A31 H__ */