sys/arm/allwinner/clkng/ccu_a64.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2017,2018 Emmanuel Vadot <manu@freebsd.org>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  20  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  21  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  22  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  23  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD$
  28  */
  29
  30 #include <sys/cdefs.h>
  31 __FBSDID("$FreeBSD$");
  32
  33 #include <sys/param.h>
  34 #include <sys/systm.h>
  35 #include <sys/bus.h>
  36 #include <sys/rman.h>
  37 #include <sys/kernel.h>
  38 #include <sys/module.h>
  39 #include <machine/bus.h>
  40
  41 #include <dev/fdt/simplebus.h>
  42
  43 #include <dev/ofw/ofw_bus.h>
  44 #include <dev/ofw/ofw_bus_subr.h>
  45
  46 #include <dev/extres/clk/clk_div.h>
  47 #include <dev/extres/clk/clk_fixed.h>
  48 #include <dev/extres/clk/clk_mux.h>
  49
  50 #include <arm/allwinner/clkng/aw_ccung.h>
  51
  52 #include <gnu/dts/include/dt-bindings/clock/sun50i-a64-ccu.h>
  53 #include <gnu/dts/include/dt-bindings/reset/sun50i-a64-ccu.h>
  54
  55 /* Non-exported clocks */
  56
  57 #define CLK_OSC_12M                     0
  58 #define CLK_PLL_CPUX                    1
  59 #define CLK_PLL_AUDIO_BASE              2
  60 #define CLK_PLL_AUDIO           3
  61 #define CLK_PLL_AUDIO_2X                4
  62 #define CLK_PLL_AUDIO_4X                5
  63 #define CLK_PLL_AUDIO_8X                6
  64 #define CLK_PLL_VIDEO0          7
  65 #define CLK_PLL_VIDEO0_2X               8
  66 #define CLK_PLL_VE                      9
  67 #define CLK_PLL_DDR0            10
  68 #define CLK_PLL_PERIPH0_2X              12
  69 #define CLK_PLL_PERIPH1         13
  70 #define CLK_PLL_PERIPH1_2X              14
  71 #define CLK_PLL_VIDEO1          15
  72 #define CLK_PLL_GPU                     16
  73 #define CLK_PLL_HSIC            18
  74 #define CLK_PLL_DE                      19
  75 #define CLK_PLL_DDR1            20
  76 #define CLK_CPUX                        21
  77 #define CLK_AXI                 22
  78 #define CLK_APB                 23
  79 #define CLK_AHB1                        24
  80 #define CLK_APB1                        25
  81 #define CLK_APB2                        26
  82 #define CLK_AHB2                        27
  83 #define CLK_DRAM                        94
  84
  85 #define CLK_MBUS                        112
  86
  87 static struct aw_ccung_reset a64_ccu_resets[] = {
  88         CCU_RESET(RST_USB_PHY0, 0x0cc, 0)
  89         CCU_RESET(RST_USB_PHY1, 0x0cc, 1)
  90         CCU_RESET(RST_USB_HSIC, 0x0cc, 2)
  91
  92         CCU_RESET(RST_BUS_MIPI_DSI, 0x2c0, 1)
  93         CCU_RESET(RST_BUS_CE, 0x2c0, 5)
  94         CCU_RESET(RST_BUS_DMA, 0x2c0, 6)
  95         CCU_RESET(RST_BUS_MMC0, 0x2c0, 8)
  96         CCU_RESET(RST_BUS_MMC1, 0x2c0, 9)
  97         CCU_RESET(RST_BUS_MMC2, 0x2c0, 10)
  98         CCU_RESET(RST_BUS_NAND, 0x2c0, 13)
  99         CCU_RESET(RST_BUS_DRAM, 0x2c0, 14)
 100         CCU_RESET(RST_BUS_EMAC, 0x2c0, 17)
 101         CCU_RESET(RST_BUS_TS, 0x2c0, 18)
 102         CCU_RESET(RST_BUS_HSTIMER, 0x2c0, 19)
 103         CCU_RESET(RST_BUS_SPI0, 0x2c0, 20)
 104         CCU_RESET(RST_BUS_SPI1, 0x2c0, 21)
 105         CCU_RESET(RST_BUS_OTG, 0x2c0, 23)
 106         CCU_RESET(RST_BUS_EHCI0, 0x2c0, 24)
 107         CCU_RESET(RST_BUS_EHCI1, 0x2c0, 25)
 108         CCU_RESET(RST_BUS_OHCI0, 0x2c0, 28)
 109         CCU_RESET(RST_BUS_OHCI1, 0x2c0, 29)
 110
 111         CCU_RESET(RST_BUS_VE, 0x2c4, 0)
 112         CCU_RESET(RST_BUS_TCON0, 0x2c4, 3)
 113         CCU_RESET(RST_BUS_TCON1, 0x2c4, 4)
 114         CCU_RESET(RST_BUS_DEINTERLACE, 0x2c4, 5)
 115         CCU_RESET(RST_BUS_CSI, 0x2c4, 8)
 116         CCU_RESET(RST_BUS_HDMI0, 0x2c4, 10)
 117         CCU_RESET(RST_BUS_HDMI1, 0x2c4, 11)
 118         CCU_RESET(RST_BUS_DE, 0x2c4, 12)
 119         CCU_RESET(RST_BUS_GPU, 0x2c4, 20)
 120         CCU_RESET(RST_BUS_MSGBOX, 0x2c4, 21)
 121         CCU_RESET(RST_BUS_SPINLOCK, 0x2c4, 22)
 122         CCU_RESET(RST_BUS_DBG, 0x2c4, 31)
 123
 124         CCU_RESET(RST_BUS_LVDS, 0x2C8, 31)
 125
 126         CCU_RESET(RST_BUS_CODEC, 0x2D0, 0)
 127         CCU_RESET(RST_BUS_SPDIF, 0x2D0, 1)
 128         CCU_RESET(RST_BUS_THS, 0x2D0, 8)
 129         CCU_RESET(RST_BUS_I2S0, 0x2D0, 12)
 130         CCU_RESET(RST_BUS_I2S1, 0x2D0, 13)
 131         CCU_RESET(RST_BUS_I2S2, 0x2D0, 14)
 132
 133         CCU_RESET(RST_BUS_I2C0, 0x2D8, 0)
 134         CCU_RESET(RST_BUS_I2C1, 0x2D8, 1)
 135         CCU_RESET(RST_BUS_I2C2, 0x2D8, 2)
 136         CCU_RESET(RST_BUS_SCR, 0x2D8, 5)
 137         CCU_RESET(RST_BUS_UART0, 0x2D8, 16)
 138         CCU_RESET(RST_BUS_UART1, 0x2D8, 17)
 139         CCU_RESET(RST_BUS_UART2, 0x2D8, 18)
 140         CCU_RESET(RST_BUS_UART3, 0x2D8, 19)
 141         CCU_RESET(RST_BUS_UART4, 0x2D8, 20)
 142 };
 143
 144 static struct aw_ccung_gate a64_ccu_gates[] = {
 145         CCU_GATE(CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 0x60, 1)
 146         CCU_GATE(CLK_BUS_CE, "bus-ce", "ahb1", 0x60, 5)
 147         CCU_GATE(CLK_BUS_DMA, "bus-dma", "ahb1", 0x60, 6)
 148         CCU_GATE(CLK_BUS_MMC0, "bus-mmc0", "ahb1", 0x60, 8)
 149         CCU_GATE(CLK_BUS_MMC1, "bus-mmc1", "ahb1", 0x60, 9)
 150         CCU_GATE(CLK_BUS_MMC2, "bus-mmc2", "ahb1", 0x60, 10)
 151         CCU_GATE(CLK_BUS_NAND, "bus-nand", "ahb1", 0x60, 13)
 152         CCU_GATE(CLK_BUS_DRAM, "bus-dram", "ahb1", 0x60, 14)
 153         CCU_GATE(CLK_BUS_EMAC, "bus-emac", "ahb2", 0x60, 16)
 154         CCU_GATE(CLK_BUS_TS, "bus-ts", "ahb1", 0x60, 18)
 155         CCU_GATE(CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 0x60, 19)
 156         CCU_GATE(CLK_BUS_SPI0, "bus-spi0", "ahb1", 0x60, 20)
 157         CCU_GATE(CLK_BUS_SPI1, "bus-spi1", "ahb1", 0x60, 21)
 158         CCU_GATE(CLK_BUS_OTG, "bus-otg", "ahb1", 0x60, 23)
 159         CCU_GATE(CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 0x60, 24)
 160         CCU_GATE(CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 0x60, 25)
 161         CCU_GATE(CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 0x60, 28)
 162         CCU_GATE(CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 0x60, 29)
 163
 164         CCU_GATE(CLK_BUS_VE, "bus-ve", "ahb1", 0x64, 0)
 165         CCU_GATE(CLK_BUS_TCON0, "bus-tcon0", "ahb1", 0x64, 3)
 166         CCU_GATE(CLK_BUS_TCON1, "bus-tcon1", "ahb1", 0x64, 4)
 167         CCU_GATE(CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 0x64, 5)
 168         CCU_GATE(CLK_BUS_CSI, "bus-csi", "ahb1", 0x64, 8)
 169         CCU_GATE(CLK_BUS_HDMI, "bus-hdmi", "ahb1", 0x64, 11)
 170         CCU_GATE(CLK_BUS_DE, "bus-de", "ahb1", 0x64, 12)
 171         CCU_GATE(CLK_BUS_GPU, "bus-gpu", "ahb1", 0x64, 20)
 172         CCU_GATE(CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 0x64, 21)
 173         CCU_GATE(CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 0x64, 22)
 174
 175         CCU_GATE(CLK_BUS_CODEC, "bus-codec", "apb1", 0x68, 0)
 176         CCU_GATE(CLK_BUS_SPDIF, "bus-spdif", "apb1", 0x68, 1)
 177         CCU_GATE(CLK_BUS_PIO, "bus-pio", "apb1", 0x68, 5)
 178         CCU_GATE(CLK_BUS_THS, "bus-ths", "apb1", 0x68, 8)
 179         CCU_GATE(CLK_BUS_I2S0, "bus-i2s0", "apb1", 0x68, 12)
 180         CCU_GATE(CLK_BUS_I2S1, "bus-i2s1", "apb1", 0x68, 13)
 181         CCU_GATE(CLK_BUS_I2S2, "bus-i2s2", "apb1", 0x68, 14)
 182
 183         CCU_GATE(CLK_BUS_I2C0, "bus-i2c0", "apb2", 0x6C, 0)
 184         CCU_GATE(CLK_BUS_I2C1, "bus-i2c1", "apb2", 0x6C, 1)
 185         CCU_GATE(CLK_BUS_I2C2, "bus-i2c2", "apb2", 0x6C, 2)
 186         CCU_GATE(CLK_BUS_SCR, "bus-src", "apb2", 0x6C, 5)
 187         CCU_GATE(CLK_BUS_UART0, "bus-uart0", "apb2", 0x6C, 16)
 188         CCU_GATE(CLK_BUS_UART1, "bus-uart1", "apb2", 0x6C, 17)
 189         CCU_GATE(CLK_BUS_UART2, "bus-uart2", "apb2", 0x6C, 18)
 190         CCU_GATE(CLK_BUS_UART3, "bus-uart3", "apb2", 0x6C, 19)
 191         CCU_GATE(CLK_BUS_UART4, "bus-uart4", "apb2", 0x6C, 20)
 192
 193         CCU_GATE(CLK_BUS_DBG, "bus-dbg", "ahb1", 0x70, 7)
 194
 195         CCU_GATE(CLK_THS, "ths", "thsdiv", 0x74, 31)
 196
 197         CCU_GATE(CLK_USB_PHY0, "usb-phy0", "osc24M", 0xcc, 8)
 198         CCU_GATE(CLK_USB_PHY1, "usb-phy1", "osc24M", 0xcc, 9)
 199         CCU_GATE(CLK_USB_HSIC, "usb-hsic", "pll_hsic", 0xcc, 10)
 200         CCU_GATE(CLK_USB_HSIC_12M, "usb-hsic-12M", "osc12M", 0xcc, 11)
 201         CCU_GATE(CLK_USB_OHCI0, "usb-ohci0", "osc12M", 0xcc, 16)
 202         CCU_GATE(CLK_USB_OHCI1, "usb-ohci1", "usb-ohci0", 0xcc, 17)
 203
 204         CCU_GATE(CLK_DRAM_VE, "dram-ve", "dram", 0x100, 0)
 205         CCU_GATE(CLK_DRAM_CSI, "dram-csi", "dram", 0x100, 1)
 206         CCU_GATE(CLK_DRAM_DEINTERLACE, "dram-deinterlace", "dram", 0x100, 2)
 207         CCU_GATE(CLK_DRAM_TS, "dram-ts", "dram", 0x100, 3)
 208
 209         CCU_GATE(CLK_CSI_MISC, "csi-misc", "osc24M", 0x130, 31)
 210
 211         CCU_GATE(CLK_AC_DIG_4X, "ac-dig-4x", "pll_audio-4x", 0x140, 30)
 212         CCU_GATE(CLK_AC_DIG, "ac-dig", "pll_audio", 0x140, 31)
 213
 214         CCU_GATE(CLK_AVS, "avs", "osc24M", 0x144, 31)
 215
 216         CCU_GATE(CLK_HDMI_DDC, "hdmi-ddc", "osc24M", 0x154, 31)
 217 };
 218
 219 static const char *osc12m_parents[] = {"osc24M"};
 220 FIXED_CLK(osc12m_clk,
 221     CLK_OSC_12M,                        /* id */
 222     "osc12M",                           /* name */
 223     osc12m_parents,                     /* parent */
 224     0,                                  /* freq */
 225     1,                                  /* mult */
 226     2,                                  /* div */
 227     0);                                 /* flags */
 228
 229 static const char *pll_cpux_parents[] = {"osc24M"};
 230 NKMP_CLK(pll_cpux_clk,
 231     CLK_PLL_CPUX,                               /* id */
 232     "pll_cpux", pll_cpux_parents,               /* name, parents */
 233     0x00,                                       /* offset */
 234     8, 5, 0, 0,                                 /* n factor */
 235     4, 2, 0, 0,                                 /* k factor */
 236     0, 2, 0, 0,                                 /* m factor */
 237     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* p factor */
 238     31,                                         /* gate */
 239     28, 1000,                                   /* lock */
 240     AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK | AW_CLK_SCALE_CHANGE);           /* flags */
 241
 242 static const char *pll_audio_parents[] = {"osc24M"};
 243 NKMP_CLK(pll_audio_clk,
 244     CLK_PLL_AUDIO,                              /* id */
 245     "pll_audio", pll_audio_parents,             /* name, parents */
 246     0x08,                                       /* offset */
 247     8, 7, 0, 0,                                 /* n factor */
 248     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* k factor (fake) */
 249     0, 5, 0, 0,                                 /* m factor */
 250     16, 4, 0, 0,                                /* p factor */
 251     31,                                         /* gate */
 252     28, 1000,                                   /* lock */
 253     AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK);         /* flags */
 254
 255 static const char *pll_audio_mult_parents[] = {"pll_audio"};
 256 FIXED_CLK(pll_audio_2x_clk,
 257     CLK_PLL_AUDIO_2X,                   /* id */
 258     "pll_audio-2x",                     /* name */
 259     pll_audio_mult_parents,             /* parent */
 260     0,                                  /* freq */
 261     2,                                  /* mult */
 262     1,                                  /* div */
 263     0);                                 /* flags */
 264 FIXED_CLK(pll_audio_4x_clk,
 265     CLK_PLL_AUDIO_4X,                   /* id */
 266     "pll_audio-4x",                     /* name */
 267     pll_audio_mult_parents,             /* parent */
 268     0,                                  /* freq */
 269     4,                                  /* mult */
 270     1,                                  /* div */
 271     0);                                 /* flags */
 272 FIXED_CLK(pll_audio_8x_clk,
 273     CLK_PLL_AUDIO_8X,                   /* id */
 274     "pll_audio-8x",                     /* name */
 275     pll_audio_mult_parents,             /* parent */
 276     0,                                  /* freq */
 277     8,                                  /* mult */
 278     1,                                  /* div */
 279     0);                                 /* flags */
 280
 281 static const char *pll_video0_parents[] = {"osc24M"};
 282 FRAC_CLK(pll_video0_clk,
 283     CLK_PLL_VIDEO0,                             /* id */
 284     "pll_video0", pll_video0_parents,           /* name, parents */
 285     0x10,                                       /* offset */
 286     8, 7, 0, 0,                                 /* n factor */
 287     0, 4, 0, 0,                                 /* m factor */
 288     31, 28, 1000,                               /* gate, lock, lock retries */
 289     AW_CLK_HAS_LOCK,                            /* flags */
 290     270000000, 297000000,                       /* freq0, freq1 */
 291     24, 25,                                     /* mode sel, freq sel */
 292     192000000, 600000000);                      /* min freq, max freq */
 293 static const char *pll_video0_2x_parents[] = {"pll_video0"};
 294 FIXED_CLK(pll_video0_2x_clk,
 295     CLK_PLL_VIDEO0_2X,                  /* id */
 296     "pll_video0-2x",                    /* name */
 297     pll_video0_2x_parents,              /* parent */
 298     0,                                  /* freq */
 299     2,                                  /* mult */
 300     1,                                  /* div */
 301     0);                                 /* flags */
 302
 303 static const char *pll_ve_parents[] = {"osc24M"};
 304 FRAC_CLK(pll_ve_clk,
 305     CLK_PLL_VE,                                 /* id */
 306     "pll_ve", pll_ve_parents,                   /* name, parents */
 307     0x18,                                       /* offset */
 308     8, 7, 0, 0,                                 /* n factor */
 309     0, 4, 0, 0,                                 /* m factor */
 310     31, 28, 1000,                               /* gate, lock, lock retries */
 311     AW_CLK_HAS_LOCK,                            /* flags */
 312     270000000, 297000000,                       /* freq0, freq1 */
 313     24, 25,                                     /* mode sel, freq sel */
 314     192000000, 600000000);                      /* min freq, max freq */
 315
 316 static const char *pll_ddr0_parents[] = {"osc24M"};
 317 NKMP_CLK_WITH_UPDATE(pll_ddr0_clk,
 318     CLK_PLL_DDR0,                               /* id */
 319     "pll_ddr0", pll_ddr0_parents,               /* name, parents */
 320     0x20,                                       /* offset */
 321     8, 5, 0, 0,                                 /* n factor */
 322     4, 2, 0, 0,                                 /* k factor */
 323     0, 2, 0, 0,                                 /* m factor */
 324     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* p factor (fake) */
 325     31,                                         /* gate */
 326     28, 1000,                                   /* lock */
 327     20,                                         /* update */
 328     AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK);         /* flags */
 329
 330 static const char *pll_periph0_2x_parents[] = {"osc24M"};
 331 static const char *pll_periph0_parents[] = {"pll_periph0_2x"};
 332 NKMP_CLK(pll_periph0_2x_clk,
 333     CLK_PLL_PERIPH0_2X,                         /* id */
 334     "pll_periph0_2x", pll_periph0_2x_parents,   /* name, parents */
 335     0x28,                                       /* offset */
 336     8, 5, 0, 0,                                 /* n factor */
 337     4, 2, 0, 0,                                 /* k factor */
 338     0, 0, 2, AW_CLK_FACTOR_FIXED,               /* m factor (fake) */
 339     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* p factor (fake) */
 340     31,                                         /* gate */
 341     28, 1000,                                   /* lock */
 342     AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK);         /* flags */
 343 FIXED_CLK(pll_periph0_clk,
 344     CLK_PLL_PERIPH0,                    /* id */
 345     "pll_periph0",                      /* name */
 346     pll_periph0_parents,                /* parent */
 347     0,                                  /* freq */
 348     1,                                  /* mult */
 349     2,                                  /* div */
 350     0);                                 /* flags */
 351
 352 static const char *pll_periph1_2x_parents[] = {"osc24M"};
 353 static const char *pll_periph1_parents[] = {"pll_periph1_2x"};
 354 NKMP_CLK(pll_periph1_2x_clk,
 355     CLK_PLL_PERIPH1_2X,                         /* id */
 356     "pll_periph1_2x", pll_periph1_2x_parents,   /* name, parents */
 357     0x2C,                                       /* offset */
 358     8, 5, 0, 0,                                 /* n factor */
 359     4, 2, 0, 0,                                 /* k factor */
 360     0, 0, 2, AW_CLK_FACTOR_FIXED,               /* m factor (fake) */
 361     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* p factor (fake) */
 362     31,                                         /* gate */
 363     28, 1000,                                   /* lock */
 364     AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK);         /* flags */
 365 FIXED_CLK(pll_periph1_clk,
 366     CLK_PLL_PERIPH1,                    /* id */
 367     "pll_periph1",                      /* name */
 368     pll_periph1_parents,                /* parent */
 369     0,                                  /* freq */
 370     1,                                  /* mult */
 371     2,                                  /* div */
 372     0);                                 /* flags */
 373
 374 static const char *pll_video1_parents[] = {"osc24M"};
 375 FRAC_CLK(pll_video1_clk,
 376     CLK_PLL_VIDEO1,                             /* id */
 377     "pll_video1", pll_video1_parents,           /* name, parents */
 378     0x30,                                       /* offset */
 379     8, 7, 0, 0,                                 /* n factor */
 380     0, 4, 0, 0,                                 /* m factor */
 381     31, 28, 1000,                               /* gate, lock, lock retries */
 382     AW_CLK_HAS_LOCK,                            /* flags */
 383     270000000, 297000000,                       /* freq0, freq1 */
 384     24, 25,                                     /* mode sel, freq sel */
 385     192000000, 600000000);                      /* min freq, max freq */
 386
 387 static const char *pll_gpu_parents[] = {"osc24M"};
 388 FRAC_CLK(pll_gpu_clk,
 389     CLK_PLL_GPU,                                /* id */
 390     "pll_gpu", pll_gpu_parents,                 /* name, parents */
 391     0x38,                                       /* offset */
 392     8, 7, 0, 0,                                 /* n factor */
 393     0, 4, 0, 0,                                 /* m factor */
 394     31, 28, 1000,                               /* gate, lock, lock retries */
 395     AW_CLK_HAS_LOCK,                            /* flags */
 396     270000000, 297000000,                       /* freq0, freq1 */
 397     24, 25,                                     /* mode sel, freq sel */
 398     192000000, 600000000);                      /* min freq, max freq */
 399
 400 /* PLL MIPI is missing */
 401
 402 static const char *pll_hsic_parents[] = {"osc24M"};
 403 FRAC_CLK(pll_hsic_clk,
 404     CLK_PLL_HSIC,                               /* id */
 405     "pll_hsic", pll_hsic_parents,               /* name, parents */
 406     0x44,                                       /* offset */
 407     8, 7, 0, 0,                                 /* n factor */
 408     0, 4, 0, 0,                                 /* m factor */
 409     31, 28, 1000,                               /* gate, lock, lock retries */
 410     AW_CLK_HAS_LOCK,                            /* flags */
 411     270000000, 297000000,                       /* freq0, freq1 */
 412     24, 25,                                     /* mode sel, freq sel */
 413     192000000, 600000000);                      /* min freq, max freq */
 414
 415 static const char *pll_de_parents[] = {"osc24M"};
 416 FRAC_CLK(pll_de_clk,
 417     CLK_PLL_DE,                                 /* id */
 418     "pll_de", pll_de_parents,                   /* name, parents */
 419     0x48,                                       /* offset */
 420     8, 7, 0, 0,                                 /* n factor */
 421     0, 4, 0, 0,                                 /* m factor */
 422     31, 28, 1000,                               /* gate, lock, lock retries */
 423     AW_CLK_HAS_LOCK,                            /* flags */
 424     270000000, 297000000,                       /* freq0, freq1 */
 425     24, 25,                                     /* mode sel, freq sel */
 426     192000000, 600000000);                      /* min freq, max freq */
 427
 428 static const char *pll_ddr1_parents[] = {"osc24M"};
 429 NKMP_CLK_WITH_UPDATE(pll_ddr1_clk,
 430     CLK_PLL_DDR1,                               /* id */
 431     "pll_ddr1", pll_ddr1_parents,               /* name, parents */
 432     0x4C,                                       /* offset */
 433     8, 7, 0, 0,                                 /* n factor */
 434     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* k factor (fake) */
 435     0, 2, 0, 0,                                 /* m factor */
 436     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* p factor (fake) */
 437     31,                                         /* gate */
 438     28, 1000,                                   /* lock */
 439     20,                                         /* update */
 440     AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK);         /* flags */
 441
 442 static const char *cpux_parents[] = {"osc32k", "osc24M", "pll_cpux"};
 443 MUX_CLK(cpux_clk,
 444     CLK_CPUX,                   /* id */
 445     "cpux", cpux_parents,       /* name, parents */
 446     0x50, 16, 2);               /* offset, shift, width */
 447
 448 static const char *axi_parents[] = {"cpux"};
 449 DIV_CLK(axi_clk,
 450     CLK_AXI,                    /* id */
 451     "axi", axi_parents,         /* name, parents */
 452     0x50,                       /* offset */
 453     0, 2,                       /* shift, width */
 454     0, NULL);                   /* flags, div table */
 455
 456 static const char *apb_parents[] = {"cpux"};
 457 DIV_CLK(apb_clk,
 458     CLK_APB,                    /* id */
 459     "apb", apb_parents,         /* name, parents */
 460     0x50,                       /* offset */
 461     8, 2,                       /* shift, width */
 462     0, NULL);                   /* flags, div table */
 463
 464 static const char *ahb1_parents[] = {"osc32k", "osc24M", "axi", "pll_periph0"};
 465 PREDIV_CLK(ahb1_clk, CLK_AHB1,                                  /* id */
 466     "ahb1", ahb1_parents,                                       /* name, parents */
 467     0x54,                                                       /* offset */
 468     12, 2,                                                      /* mux */
 469     4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,                        /* div */
 470     6, 2, 0, AW_CLK_FACTOR_HAS_COND,                            /* prediv */
 471     12, 2, 3);                                                  /* prediv condition */
 472
 473 static const char *apb1_parents[] = {"ahb1"};
 474 static struct clk_div_table apb1_div_table[] = {
 475         { .value = 0, .divider = 2, },
 476         { .value = 1, .divider = 2, },
 477         { .value = 2, .divider = 4, },
 478         { .value = 3, .divider = 8, },
 479         { },
 480 };
 481 DIV_CLK(apb1_clk,
 482     CLK_APB1,                   /* id */
 483     "apb1", apb1_parents,       /* name, parents */
 484     0x54,                       /* offset */
 485     8, 2,                       /* shift, width */
 486     CLK_DIV_WITH_TABLE,         /* flags */
 487     apb1_div_table);            /* div table */
 488
 489 static const char *apb2_parents[] = {"osc32k", "osc24M", "pll_periph0_2x", "pll_periph0_2x"};
 490 NM_CLK(apb2_clk,
 491     CLK_APB2,                                   /* id */
 492     "apb2", apb2_parents,                       /* name, parents */
 493     0x58,                                       /* offset */
 494     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 495     0, 5, 0, 0,                                 /* m factor */
 496     24, 2,                                      /* mux */
 497     0,                                          /* gate */
 498     AW_CLK_HAS_MUX);
 499
 500 static const char *ahb2_parents[] = {"ahb1", "pll_periph0"};
 501 PREDIV_CLK(ahb2_clk, CLK_AHB2,                                  /* id */
 502     "ahb2", ahb2_parents,                                       /* name, parents */
 503     0x5c,                                                       /* offset */
 504     0, 2,                                                       /* mux */
 505     0, 0, 1, AW_CLK_FACTOR_FIXED,                               /* div */
 506     0, 0, 2, AW_CLK_FACTOR_HAS_COND | AW_CLK_FACTOR_FIXED,      /* prediv */
 507     0, 2, 1);                                                   /* prediv condition */
 508
 509 static const char *ths_parents[] = {"osc24M"};
 510 static struct clk_div_table ths_div_table[] = {
 511         { .value = 0, .divider = 1, },
 512         { .value = 1, .divider = 2, },
 513         { .value = 2, .divider = 4, },
 514         { .value = 3, .divider = 6, },
 515         { },
 516 };
 517 DIV_CLK(ths_clk,
 518     0,                          /* id */
 519     "thsdiv", ths_parents,      /* name, parents */
 520     0x74,                       /* offset */
 521     0, 2,                       /* div shift, div width */
 522     CLK_DIV_WITH_TABLE,         /* flags */
 523     ths_div_table);             /* div table */
 524
 525 static const char *mod_parents[] = {"osc24M", "pll_periph0_2x", "pll_periph1_2x"};
 526 NM_CLK(nand_clk,
 527     CLK_NAND, "nand", mod_parents,              /* id, name, parents */
 528     0x80,                                       /* offset */
 529     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 530     0, 4, 0, 0,                                 /* m factor */
 531     24, 2,                                      /* mux */
 532     31,                                         /* gate */
 533     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX);          /* flags */
 534
 535 NM_CLK(mmc0_clk,
 536     CLK_MMC0, "mmc0", mod_parents,              /* id, name, parents */
 537     0x88,                                       /* offset */
 538     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 539     0, 4, 0, 0,                                 /* m factor */
 540     24, 2,                                      /* mux */
 541     31,                                         /* gate */
 542     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
 543     AW_CLK_REPARENT);                           /* flags */
 544
 545 NM_CLK(mmc1_clk,
 546     CLK_MMC1, "mmc1", mod_parents,              /* id, name, parents */
 547     0x8c,                                       /* offset */
 548     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 549     0, 4, 0, 0,                                 /* m factor */
 550     24, 2,                                      /* mux */
 551     31,                                         /* gate */
 552     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
 553     AW_CLK_REPARENT);                           /* flags */
 554
 555 NM_CLK(mmc2_clk,
 556     CLK_MMC2, "mmc2", mod_parents,              /* id, name, parents */
 557     0x90,                                       /* offset */
 558     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 559     0, 4, 0, 0,                                 /* m factor */
 560     24, 2,                                      /* mux */
 561     31,                                         /* gate */
 562     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
 563     AW_CLK_REPARENT);                           /* flags */
 564
 565 static const char *ts_parents[] = {"osc24M", "pll_periph0"};
 566 NM_CLK(ts_clk,
 567     CLK_TS, "ts", ts_parents,                   /* id, name, parents */
 568     0x98,                                       /* offset */
 569     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 570     0, 4, 0, 0,                                 /* m factor */
 571     24, 2,                                      /* mux */
 572     31,                                         /* gate */
 573     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX);          /* flags */
 574
 575 NM_CLK(ce_clk,
 576     CLK_CE, "ce", mod_parents,                  /* id, name, parents */
 577     0x9C,                                       /* offset */
 578     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 579     0, 4, 0, 0,                                 /* m factor */
 580     24, 2,                                      /* mux */
 581     31,                                         /* gate */
 582     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX);          /* flags */
 583
 584 NM_CLK(spi0_clk,
 585     CLK_SPI0, "spi0", mod_parents,              /* id, name, parents */
 586     0xA0,                                       /* offset */
 587     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 588     0, 4, 0, 0,                                 /* m factor */
 589     24, 2,                                      /* mux */
 590     31,                                         /* gate */
 591     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
 592     AW_CLK_REPARENT);                           /* flags */
 593
 594 NM_CLK(spi1_clk,
 595     CLK_SPI1, "spi1", mod_parents,              /* id, name, parents */
 596     0xA4,                                       /* offset */
 597     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 598     0, 4, 0, 0,                                 /* m factor */
 599     24, 2,                                      /* mux */
 600     31,                                         /* gate */
 601     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
 602     AW_CLK_REPARENT);                           /* flags */
 603
 604 static const char *i2s_parents[] = {"pll_audio-8x", "pll_audio-4x", "pll_audio-2x", "pll_audio"};
 605 MUX_CLK(i2s0mux_clk,
 606     0, "i2s0mux", i2s_parents,                  /* id, name, parents */
 607     0xb0, 16, 2);                               /* offset, mux shift, mux width */
 608 MUX_CLK(i2s1mux_clk,
 609     0, "i2s1mux", i2s_parents,                  /* id, name, parents */
 610     0xb4, 16, 2);                               /* offset, mux shift, mux width */
 611 MUX_CLK(i2s2mux_clk,
 612     0, "i2s2mux", i2s_parents,                  /* id, name, parents */
 613     0xb8, 16, 2);                               /* offset, mux shift, mux width */
 614
 615 static const char *spdif_parents[] = {"pll_audio"};
 616 M_CLK(spdif_clk,
 617     CLK_SPDIF, "spdif", spdif_parents,          /* id, name, parents */
 618     0xC0,                                       /* offset */
 619     0, 4, 0, 0,                                 /* m factor */
 620     0, 0,                                       /* mux */
 621     31,                                         /* gate */
 622     AW_CLK_HAS_GATE);                           /* flags */
 623
 624 /* USBPHY clk sel */
 625
 626 /* DRAM needs update bit */
 627 static const char *dram_parents[] = {"pll_ddr0", "pll_ddr1"};
 628 M_CLK(dram_clk,
 629     CLK_DRAM, "dram", dram_parents,             /* id, name, parents */
 630     0xF4,                                       /* offset */
 631     0, 2, 0, 0,                                 /* m factor */
 632     20, 2,                                      /* mux */
 633     0,                                          /* gate */
 634     AW_CLK_HAS_MUX);                            /* flags */
 635
 636 static const char *de_parents[] = {"pll_periph0_2x", "pll_de"};
 637 M_CLK(de_clk,
 638     CLK_DE, "de", de_parents,                   /* id, name, parents */
 639     0x104,                                      /* offset */
 640     0, 4, 0, 0,                                 /* m factor */
 641     24, 2,                                      /* mux */
 642     31,                                         /* gate */
 643     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 644
 645 /* TCON0/1 Needs mux table */
 646 static const char *tcon1_parents[] = {"pll_video0", "pll_video0", "pll_video1"};
 647 M_CLK(tcon1_clk,
 648     CLK_TCON1, "tcon1", tcon1_parents,  /* id, name, parents */
 649     0x11C,                              /* offset */
 650     0, 5, 0, 0,                         /* m factor */
 651     24, 2,                              /* mux */
 652     31,                                 /* gate */
 653     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE |
 654     AW_CLK_SET_PARENT);                 /* flags */
 655
 656 static const char *deinterlace_parents[] = {"pll_periph0", "pll_periph1"};
 657 M_CLK(deinterlace_clk,
 658     CLK_DEINTERLACE, "deinterlace", deinterlace_parents,        /* id, name, parents */
 659     0x124,                                      /* offset */
 660     0, 4, 0, 0,                                 /* m factor */
 661     24, 2,                                      /* mux */
 662     31,                                         /* gate */
 663     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 664
 665 static const char *csi_sclk_parents[] = {"pll_periph0", "pll_periph1"};
 666 M_CLK(csi_sclk_clk,
 667     CLK_CSI_SCLK, "csi-sclk", csi_sclk_parents, /* id, name, parents */
 668     0x134,                                      /* offset */
 669     16, 4, 0, 0,                                /* m factor */
 670     24, 2,                                      /* mux */
 671     31,                                         /* gate */
 672     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 673
 674 static const char *csi_mclk_parents[] = {"osc24M", "pll_video0", "pll_periph1"};
 675 M_CLK(csi_mclk_clk,
 676     CLK_CSI_MCLK, "csi-mclk", csi_mclk_parents, /* id, name, parents */
 677     0x134,                                      /* offset */
 678     0, 4, 0, 0,                                 /* m factor */
 679     8, 2,                                       /* mux */
 680     15,                                         /* gate */
 681     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 682
 683 static const char *ve_parents[] = {"pll_ve"};
 684 M_CLK(ve_clk,
 685     CLK_VE, "ve", ve_parents,                   /* id, name, parents */
 686     0x13C,                                      /* offset */
 687     16, 3, 0, 0,                                /* m factor */
 688     0, 0,                                       /* mux */
 689     31,                                         /* gate */
 690     AW_CLK_HAS_GATE);                           /* flags */
 691
 692 static const char *hdmi_parents[] = {"pll_video0"};
 693 M_CLK(hdmi_clk,
 694     CLK_HDMI, "hdmi", hdmi_parents,             /* id, name, parents */
 695     0x150,                                      /* offset */
 696     0, 4, 0, 0,                                 /* m factor */
 697     24, 2,                                      /* mux */
 698     31,                                         /* gate */
 699     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_SET_PARENT);              /* flags */
 700
 701 static const char *mbus_parents[] = {"osc24M", "pll_periph0_2x", "pll_ddr0"};
 702 M_CLK(mbus_clk,
 703     CLK_MBUS, "mbus", mbus_parents,             /* id, name, parents */
 704     0x15C,                                      /* offset */
 705     0, 3, 0, 0,                                 /* m factor */
 706     24, 2,                                      /* mux */
 707     31,                                         /* gate */
 708     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 709
 710 static const char *gpu_parents[] = {"pll_gpu"};
 711 M_CLK(gpu_clk,
 712     CLK_GPU, "gpu", gpu_parents,                /* id, name, parents */
 713     0x1A0,                                      /* offset */
 714     0, 2, 0, 0,                                 /* m factor */
 715     0, 0,                                       /* mux */
 716     31,                                         /* gate */
 717     AW_CLK_HAS_GATE);                           /* flags */
 718
 719 static struct aw_ccung_clk a64_ccu_clks[] = {
 720         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_cpux_clk},
 721         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_audio_clk},
 722         { .type = AW_CLK_FRAC, .clk.frac = &pll_video0_clk},
 723         { .type = AW_CLK_FRAC, .clk.frac = &pll_ve_clk},
 724         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr0_clk},
 725         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph0_2x_clk},
 726         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph1_2x_clk},
 727         { .type = AW_CLK_FRAC, .clk.frac = &pll_video1_clk},
 728         { .type = AW_CLK_FRAC, .clk.frac = &pll_gpu_clk},
 729         /* PLL_MIPI */
 730         { .type = AW_CLK_FRAC, .clk.frac = &pll_hsic_clk},
 731         { .type = AW_CLK_FRAC, .clk.frac = &pll_de_clk},
 732         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr1_clk},
 733
 734         { .type = AW_CLK_NM, .clk.nm = &apb2_clk},
 735         { .type = AW_CLK_NM, .clk.nm = &nand_clk},
 736         { .type = AW_CLK_NM, .clk.nm = &mmc0_clk},
 737         { .type = AW_CLK_NM, .clk.nm = &mmc1_clk},
 738         { .type = AW_CLK_NM, .clk.nm = &mmc2_clk},
 739         { .type = AW_CLK_NM, .clk.nm = &ts_clk},
 740         { .type = AW_CLK_NM, .clk.nm = &ce_clk},
 741         { .type = AW_CLK_NM, .clk.nm = &spi0_clk},
 742         { .type = AW_CLK_NM, .clk.nm = &spi1_clk},
 743         { .type = AW_CLK_M, .clk.m = &spdif_clk},
 744         { .type = AW_CLK_M, .clk.m = &dram_clk},
 745         { .type = AW_CLK_M, .clk.m = &de_clk},
 746         { .type = AW_CLK_M, .clk.m = &tcon1_clk},
 747         { .type = AW_CLK_M, .clk.m = &deinterlace_clk},
 748         { .type = AW_CLK_M, .clk.m = &csi_sclk_clk},
 749         { .type = AW_CLK_M, .clk.m = &csi_mclk_clk},
 750         { .type = AW_CLK_M, .clk.m = &ve_clk},
 751         { .type = AW_CLK_M, .clk.m = &hdmi_clk},
 752         { .type = AW_CLK_M, .clk.m = &mbus_clk},
 753         { .type = AW_CLK_M, .clk.m = &gpu_clk},
 754         { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb1_clk},
 755         { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb2_clk},
 756         { .type = AW_CLK_MUX, .clk.mux = &cpux_clk},
 757         { .type = AW_CLK_MUX, .clk.mux = &i2s0mux_clk},
 758         { .type = AW_CLK_MUX, .clk.mux = &i2s1mux_clk},
 759         { .type = AW_CLK_MUX, .clk.mux = &i2s2mux_clk},
 760         { .type = AW_CLK_DIV, .clk.div = &axi_clk},
 761         { .type = AW_CLK_DIV, .clk.div = &apb1_clk},
 762         { .type = AW_CLK_DIV, .clk.div = &apb_clk},
 763         { .type = AW_CLK_DIV, .clk.div = &ths_clk},
 764         { .type = AW_CLK_FIXED, .clk.fixed = &osc12m_clk},
 765         { .type = AW_CLK_FIXED, .clk.fixed = &pll_periph0_clk},
 766         { .type = AW_CLK_FIXED, .clk.fixed = &pll_periph1_clk},
 767         { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_2x_clk},
 768         { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_4x_clk},
 769         { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_8x_clk},
 770         { .type = AW_CLK_FIXED, .clk.fixed = &pll_video0_2x_clk},
 771 };
 772
 773 static struct aw_clk_init a64_init_clks[] = {
 774         {"ahb1", "pll_periph0", 0, false},
 775         {"ahb2", "pll_periph0", 0, false},
 776         {"dram", "pll_ddr0", 0, false},
 777 };
 778
 779 static int
 780 ccu_a64_probe(device_t dev)
 781 {
 782
 783         if (!ofw_bus_status_okay(dev))
 784                 return (ENXIO);
 785
 786         if (!ofw_bus_is_compatible(dev, "allwinner,sun50i-a64-ccu"))
 787                 return (ENXIO);
 788
 789         device_set_desc(dev, "Allwinner A64 Clock Control Unit NG");
 790         return (BUS_PROBE_DEFAULT);
 791 }
 792
 793 static int
 794 ccu_a64_attach(device_t dev)
 795 {
 796         struct aw_ccung_softc *sc;
 797
 798         sc = device_get_softc(dev);
 799
 800         sc->resets = a64_ccu_resets;
 801         sc->nresets = nitems(a64_ccu_resets);
 802         sc->gates = a64_ccu_gates;
 803         sc->ngates = nitems(a64_ccu_gates);
 804         sc->clks = a64_ccu_clks;
 805         sc->nclks = nitems(a64_ccu_clks);
 806         sc->clk_init = a64_init_clks;
 807         sc->n_clk_init = nitems(a64_init_clks);
 808
 809         return (aw_ccung_attach(dev));
 810 }
 811
 812 static device_method_t ccu_a64ng_methods[] = {
 813         /* Device interface */
 814         DEVMETHOD(device_probe,         ccu_a64_probe),
 815         DEVMETHOD(device_attach,        ccu_a64_attach),
 816
 817         DEVMETHOD_END
 818 };
 819
 820 static devclass_t ccu_a64ng_devclass;
 821
 822 DEFINE_CLASS_1(ccu_a64ng, ccu_a64ng_driver, ccu_a64ng_methods,
 823   sizeof(struct aw_ccung_softc), aw_ccung_driver);
 824
 825 EARLY_DRIVER_MODULE(ccu_a64ng, simplebus, ccu_a64ng_driver,
 826     ccu_a64ng_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);