sys/arm/allwinner/clkng/ccu_a83t.c

   1 /*-
   2  * Copyright (c) 2017 Kyle Evans <kevans@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  15  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  16  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  17  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  18  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  19  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  20  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  21  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  22  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  * $FreeBSD$
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __FBSDID("$FreeBSD$");
  31
  32 #include <sys/param.h>
  33 #include <sys/systm.h>
  34 #include <sys/bus.h>
  35
  36 #include <dev/extres/clk/clk_div.h>
  37 #include <dev/extres/clk/clk_fixed.h>
  38 #include <dev/extres/clk/clk_mux.h>
  39
  40 #include <arm/allwinner/clkng/aw_ccung.h>
  41 #include <arm/allwinner/clkng/aw_clk.h>
  42 #include <arm/allwinner/clkng/aw_clk_nm.h>
  43 #include <arm/allwinner/clkng/aw_clk_nkmp.h>
  44 #include <arm/allwinner/clkng/aw_clk_prediv_mux.h>
  45
  46 #include <gnu/dts/include/dt-bindings/clock/sun8i-a83t-ccu.h>
  47 #include <gnu/dts/include/dt-bindings/reset/sun8i-a83t-ccu.h>
  48
  49 #include "ccu_a83t.h"
  50
  51 /* Non-exported resets */
  52 /*
  53 #define RST_BUS_SCR             53
  54 */
  55
  56 /* Non-exported clocks */
  57
  58 #define CLK_PLL_C0CPUX          0
  59 #define CLK_PLL_C1CPUX          1
  60 #define CLK_PLL_AUDIO           2
  61 #define CLK_PLL_VIDEO0          3
  62 #define CLK_PLL_VE              4
  63 #define CLK_PLL_DDR             5
  64
  65 #define CLK_PLL_GPU             7
  66 #define CLK_PLL_HSIC            8
  67 #define CLK_PLL_VIDEO1          10
  68
  69 #define CLK_AXI0                13
  70 #define CLK_AXI1                14
  71 #define CLK_AHB1                15
  72 #define CLK_APB1                16
  73 #define CLK_APB2                17
  74 #define CLK_AHB2                18
  75
  76 #define CLK_CCI400              58
  77
  78 #define CLK_DRAM                82
  79
  80 #define CLK_MBUS                95
  81
  82 /* Non-exported fixed clocks */
  83 #define CLK_OSC_12M             150
  84
  85
  86 static struct aw_ccung_reset a83t_ccu_resets[] = {
  87         CCU_RESET(RST_USB_PHY0, 0xcc, 0)
  88         CCU_RESET(RST_USB_PHY1, 0xcc, 1)
  89         CCU_RESET(RST_USB_HSIC, 0xcc, 2)
  90
  91         CCU_RESET(RST_DRAM, 0xf4, 31)
  92         CCU_RESET(RST_MBUS, 0xfc, 31)
  93
  94         CCU_RESET(RST_BUS_MIPI_DSI, 0x2c0, 1)
  95         CCU_RESET(RST_BUS_SS, 0x2c0, 5)
  96         CCU_RESET(RST_BUS_DMA, 0x2c0, 6)
  97         CCU_RESET(RST_BUS_MMC0, 0x2c0, 8)
  98         CCU_RESET(RST_BUS_MMC1, 0x2c0, 9)
  99         CCU_RESET(RST_BUS_MMC2, 0x2c0, 10)
 100         CCU_RESET(RST_BUS_NAND, 0x2c0, 13)
 101         CCU_RESET(RST_BUS_DRAM, 0x2c0, 14)
 102         CCU_RESET(RST_BUS_EMAC, 0x2c0, 17)
 103         CCU_RESET(RST_BUS_HSTIMER, 0x2c0, 19)
 104         CCU_RESET(RST_BUS_SPI0, 0x2c0, 20)
 105         CCU_RESET(RST_BUS_SPI1, 0x2c0, 21)
 106         CCU_RESET(RST_BUS_OTG, 0x2c0, 24)
 107         CCU_RESET(RST_BUS_EHCI0, 0x2c0, 26)
 108         CCU_RESET(RST_BUS_EHCI1, 0x2c0, 27)
 109         CCU_RESET(RST_BUS_OHCI0, 0x2c0, 29)
 110
 111         CCU_RESET(RST_BUS_VE, 0x2c4, 0)
 112         CCU_RESET(RST_BUS_TCON0, 0x2c4, 4)
 113         CCU_RESET(RST_BUS_TCON1, 0x2c4, 5)
 114         CCU_RESET(RST_BUS_CSI, 0x2c4, 8)
 115         CCU_RESET(RST_BUS_HDMI0, 0x2c4, 10)
 116         CCU_RESET(RST_BUS_HDMI1, 0x2c4, 11)
 117         CCU_RESET(RST_BUS_DE, 0x2c4, 12)
 118         CCU_RESET(RST_BUS_GPU, 0x2c4, 20)
 119         CCU_RESET(RST_BUS_MSGBOX, 0x2c4, 21)
 120         CCU_RESET(RST_BUS_SPINLOCK, 0x2c4, 22)
 121
 122         CCU_RESET(RST_BUS_LVDS, 0x2c8, 0)
 123
 124         CCU_RESET(RST_BUS_SPDIF, 0x2d0, 1)
 125         CCU_RESET(RST_BUS_I2S0, 0x2d0, 12)
 126         CCU_RESET(RST_BUS_I2S1, 0x2d0, 13)
 127         CCU_RESET(RST_BUS_I2S2, 0x2d0, 14)
 128         CCU_RESET(RST_BUS_TDM, 0x2d0, 15)
 129
 130         CCU_RESET(RST_BUS_I2C0, 0x2d8, 0)
 131         CCU_RESET(RST_BUS_I2C1, 0x2d8, 1)
 132         CCU_RESET(RST_BUS_I2C2, 0x2d8, 2)
 133         CCU_RESET(RST_BUS_UART0, 0x2d8, 16)
 134         CCU_RESET(RST_BUS_UART1, 0x2d8, 17)
 135         CCU_RESET(RST_BUS_UART2, 0x2d8, 18)
 136         CCU_RESET(RST_BUS_UART3, 0x2d8, 19)
 137         CCU_RESET(RST_BUS_UART4, 0x2d8, 20)
 138 };
 139
 140 static struct aw_ccung_gate a83t_ccu_gates[] = {
 141         CCU_GATE(CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 0x60, 1)
 142         CCU_GATE(CLK_BUS_SS, "bus-ss", "ahb1", 0x60, 5)
 143         CCU_GATE(CLK_BUS_DMA, "bus-dma", "ahb1", 0x60, 6)
 144         CCU_GATE(CLK_BUS_MMC0, "bus-mmc0", "ahb1", 0x60, 8)
 145         CCU_GATE(CLK_BUS_MMC1, "bus-mmc1", "ahb1", 0x60, 9)
 146         CCU_GATE(CLK_BUS_MMC2, "bus-mmc2", "ahb1", 0x60, 10)
 147         CCU_GATE(CLK_BUS_NAND, "bus-nand", "ahb1", 0x60, 13)
 148         CCU_GATE(CLK_BUS_DRAM, "bus-dram", "ahb1", 0x60, 14)
 149         CCU_GATE(CLK_BUS_EMAC, "bus-emac", "ahb1", 0x60, 17)
 150         CCU_GATE(CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 0x60, 19)
 151         CCU_GATE(CLK_BUS_SPI0, "bus-spi0", "ahb1", 0x60, 20)
 152         CCU_GATE(CLK_BUS_SPI1, "bus-spi1", "ahb1", 0x60, 21)
 153         CCU_GATE(CLK_BUS_OTG, "bus-otg", "ahb1", 0x60, 24)
 154         CCU_GATE(CLK_BUS_EHCI0, "bus-ehci0", "ahb2", 0x60, 26)
 155         CCU_GATE(CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 0x60, 27)
 156         CCU_GATE(CLK_BUS_OHCI0, "bus-ohci0", "ahb2", 0x60, 29)
 157
 158         CCU_GATE(CLK_BUS_VE, "bus-ve", "ahb1", 0x64, 0)
 159         CCU_GATE(CLK_BUS_TCON0, "bus-tcon0", "ahb1", 0x64, 4)
 160         CCU_GATE(CLK_BUS_TCON1, "bus-tcon1", "ahb1", 0x64, 5)
 161         CCU_GATE(CLK_BUS_CSI, "bus-csi", "ahb1", 0x64, 8)
 162         CCU_GATE(CLK_BUS_HDMI, "bus-hdmi", "ahb1", 0x64, 11)
 163         CCU_GATE(CLK_BUS_DE, "bus-de", "ahb1", 0x64, 12)
 164         CCU_GATE(CLK_BUS_GPU, "bus-gpu", "ahb1", 0x64, 20)
 165         CCU_GATE(CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 0x64, 21)
 166         CCU_GATE(CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 0x64, 22)
 167
 168         CCU_GATE(CLK_BUS_SPDIF, "bus-spdif", "apb1", 0x68, 1)
 169         CCU_GATE(CLK_BUS_PIO, "bus-pio", "apb1", 0x68, 5)
 170         CCU_GATE(CLK_BUS_I2S0, "bus-i2s0", "apb1", 0x68, 12)
 171         CCU_GATE(CLK_BUS_I2S1, "bus-i2s1", "apb1", 0x68, 13)
 172         CCU_GATE(CLK_BUS_I2S2, "bus-i2s2", "apb1", 0x68, 14)
 173         CCU_GATE(CLK_BUS_TDM, "bus-tdm", "apb1", 0x68, 15)
 174
 175         CCU_GATE(CLK_BUS_I2C0, "bus-i2c0", "apb2", 0x6c, 0)
 176         CCU_GATE(CLK_BUS_I2C1, "bus-i2c1", "apb2", 0x6c, 1)
 177         CCU_GATE(CLK_BUS_I2C2, "bus-i2c2", "apb2", 0x6c, 2)
 178         CCU_GATE(CLK_BUS_UART0, "bus-uart0", "apb2", 0x6c, 16)
 179         CCU_GATE(CLK_BUS_UART1, "bus-uart1", "apb2", 0x6c, 17)
 180         CCU_GATE(CLK_BUS_UART2, "bus-uart2", "apb2", 0x6c, 18)
 181         CCU_GATE(CLK_BUS_UART3, "bus-uart3", "apb2", 0x6c, 19)
 182         CCU_GATE(CLK_BUS_UART4, "bus-uart4", "apb2", 0x6c, 20)
 183
 184         CCU_GATE(CLK_USB_PHY0, "usb-phy0", "osc24M", 0xcc, 8)
 185         CCU_GATE(CLK_USB_PHY1, "usb-phy1", "osc24M", 0xcc, 9)
 186         CCU_GATE(CLK_USB_HSIC, "usb-hsic", "pll_hsic", 0xcc, 10)
 187         CCU_GATE(CLK_USB_HSIC_12M, "usb-hsic-12M", "osc12M", 0xcc, 11)
 188         CCU_GATE(CLK_USB_OHCI0, "usb-ohci0", "osc12M", 0xcc, 16)
 189
 190         CCU_GATE(CLK_DRAM_VE, "dram-ve", "dram", 0x100, 0)
 191         CCU_GATE(CLK_DRAM_CSI, "dram-csi", "dram", 0x100, 1)
 192
 193         CCU_GATE(CLK_CSI_MISC, "csi-misc", "osc24M", 0x130, 16)
 194         CCU_GATE(CLK_MIPI_CSI, "mipi-csi", "osc24M", 0x130, 31)
 195
 196         CCU_GATE(CLK_AVS, "avs", "osc24M", 0x144, 31)
 197
 198         CCU_GATE(CLK_HDMI_SLOW, "hdmi-ddc", "osc24M", 0x154, 31)
 199 };
 200
 201 static const char *osc12m_parents[] = {"osc24M"};
 202 FIXED_CLK(osc12m_clk,
 203     CLK_OSC_12M,                                /* id */
 204     "osc12M", osc12m_parents,                   /* name, parents */
 205     0,                                          /* freq */
 206     1,                                          /* mult */
 207     2,                                          /* div */
 208     0);                                         /* flags */
 209
 210 static const char *pll_c0cpux_parents[] = {"osc24M"};
 211 static const char *pll_c1cpux_parents[] = {"osc24M"};
 212 NM_CLK(pll_c0cpux_clk,
 213     CLK_PLL_C0CPUX,                             /* id */
 214     "pll_c0cpux", pll_c0cpux_parents,           /* name, parents */
 215     0x00,                                       /* offset */
 216     8, 8, 0, AW_CLK_FACTOR_ZERO_BASED,          /* n factor */
 217     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* m factor (fake) */
 218     0, 0,                                       /* mux */
 219     31,                                         /* gate */
 220     AW_CLK_HAS_GATE | AW_CLK_SCALE_CHANGE);     /* flags */
 221 NM_CLK(pll_c1cpux_clk,
 222     CLK_PLL_C1CPUX,                             /* id */
 223     "pll_c1cpux", pll_c1cpux_parents,           /* name, parents */
 224     0x04,                                       /* offset */
 225     8, 8, 0, AW_CLK_FACTOR_ZERO_BASED,          /* n factor */
 226     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* m factor (fake) */
 227     0, 0,                                       /* mux */
 228     31,                                         /* gate */
 229     AW_CLK_HAS_GATE | AW_CLK_SCALE_CHANGE);     /* flags */
 230
 231 static const char *pll_audio_parents[] = {"osc24M"};
 232 NKMP_CLK(pll_audio_clk,
 233     CLK_PLL_AUDIO,                              /* id */
 234     "pll_audio", pll_audio_parents,             /* name, parents */
 235     0x08,                                       /* offset */
 236     8, 8, 0, AW_CLK_FACTOR_ZERO_BASED,          /* n factor */
 237     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* k factor (fake) */
 238     16, 1, 0, 0,                                /* m factor */
 239     18, 1, 0, 0,                                /* p factor */
 240     31,                                         /* gate */
 241     0, 0,                                       /* lock */
 242     AW_CLK_HAS_GATE);                           /* flags */
 243
 244 static const char *pll_video0_parents[] = {"osc24M"};
 245 NKMP_CLK(pll_video0_clk,
 246     CLK_PLL_VIDEO0,                             /* id */
 247     "pll_video0", pll_video0_parents,           /* name, parents */
 248     0x10,                                       /* offset */
 249     8, 8, 0, AW_CLK_FACTOR_ZERO_BASED,          /* n factor */
 250     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* k factor (fake) */
 251     16, 1, 0, 0,                                /* m factor */
 252     0, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,        /* p factor */
 253     31,                                         /* gate */
 254     0, 0,                                       /* lock */
 255     AW_CLK_HAS_GATE);                           /* flags */
 256
 257 static const char *pll_ve_parents[] = {"osc24M"};
 258 NKMP_CLK(pll_ve_clk,
 259     CLK_PLL_VE,                                 /* id */
 260     "pll_ve", pll_ve_parents,                   /* name, parents */
 261     0x18,                                       /* offset */
 262     8, 8, 0, AW_CLK_FACTOR_ZERO_BASED,          /* n factor */
 263     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* k factor (fake) */
 264     16, 1, 0, 0,                                /* m factor */
 265     18, 1, 0, 0,                                /* p factor */
 266     31,                                         /* gate */
 267     0, 0,                                       /* lock */
 268     AW_CLK_HAS_GATE);                           /* flags */
 269
 270 static const char *pll_ddr_parents[] = {"osc24M"};
 271 NKMP_CLK(pll_ddr_clk,
 272     CLK_PLL_DDR,                                /* id */
 273     "pll_ddr", pll_ddr_parents,                 /* name, parents */
 274     0x20,                                       /* offset */
 275     8, 5, 0, 0,                                 /* n factor */
 276     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* k factor (fake) */
 277     16, 1, 0, 0,                                /* m factor */
 278     18, 1, 0, 0,                                /* p factor */
 279     31,                                         /* gate */
 280     0, 0,                                       /* lock */
 281     AW_CLK_HAS_GATE);                           /* flags */
 282
 283 static const char *pll_periph_parents[] = {"osc24M"};
 284 NKMP_CLK(pll_periph_clk,
 285     CLK_PLL_PERIPH,                             /* id */
 286     "pll_periph", pll_periph_parents,           /* name, parents */
 287     0x28,                                       /* offset */
 288     8, 8, 0, AW_CLK_FACTOR_ZERO_BASED,          /* n factor */
 289     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* k factor (fake) */
 290     16, 1, 1, 0,                                /* m factor */
 291     18, 1, 1, 0,                                /* p factor */
 292     31,                                         /* gate */
 293     0, 0,                                       /* lock */
 294     AW_CLK_HAS_GATE);                           /* flags */
 295
 296 static const char *pll_gpu_parents[] = {"osc24M"};
 297 NKMP_CLK(pll_gpu_clk,
 298     CLK_PLL_GPU,                                /* id */
 299     "pll_gpu", pll_gpu_parents,                 /* name, parents */
 300     0x38,                                       /* offset */
 301     8, 8, 0, AW_CLK_FACTOR_ZERO_BASED,          /* n factor */
 302     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* k factor (fake) */
 303     16, 1, 1, 0,                                /* m factor */
 304     18, 1, 1, 0,                                /* p factor */
 305     31,                                         /* gate */
 306     0, 0,                                       /* lock */
 307     AW_CLK_HAS_GATE);                           /* flags */
 308
 309 static const char *pll_hsic_parents[] = {"osc24M"};
 310 NKMP_CLK(pll_hsic_clk,
 311     CLK_PLL_HSIC,                               /* id */
 312     "pll_hsic", pll_hsic_parents,               /* name, parents */
 313     0x44,                                       /* offset */
 314     8, 8, 0, AW_CLK_FACTOR_ZERO_BASED,          /* n factor */
 315     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* k factor (fake) */
 316     16, 1, 1, 0,                                /* m factor */
 317     18, 1, 1, 0,                                /* p factor */
 318     31,                                         /* gate */
 319     0, 0,                                       /* lock */
 320     AW_CLK_HAS_GATE);                           /* flags */
 321
 322 static const char *pll_de_parents[] = {"osc24M"};
 323 NKMP_CLK(pll_de_clk,
 324     CLK_PLL_DE,                                 /* id */
 325     "pll_de", pll_de_parents,                   /* name, parents */
 326     0x48,                                       /* offset */
 327     8, 8, 0, AW_CLK_FACTOR_ZERO_BASED,          /* n factor */
 328     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* k factor (fake) */
 329     16, 1, 1, 0,                                /* m factor */
 330     18, 1, 1, 0,                                /* p factor */
 331     31,                                         /* gate */
 332     0, 0,                                       /* lock */
 333     AW_CLK_HAS_GATE);                           /* flags */
 334
 335 static const char *pll_video1_parents[] = {"osc24M"};
 336 NKMP_CLK(pll_video1_clk,
 337     CLK_PLL_VIDEO1,                             /* id */
 338     "pll_video1", pll_video1_parents,           /* name, parents */
 339     0x4c,                                       /* offset */
 340     8, 8, 0, AW_CLK_FACTOR_ZERO_BASED,          /* n factor */
 341     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* k factor (fake) */
 342     16, 1, 1, 0,                                /* m factor */
 343     0, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,        /* p factor */
 344     31,                                         /* gate */
 345     0, 0,                                       /* lock */
 346     AW_CLK_HAS_GATE);                           /* flags */
 347
 348 static const char *c0cpux_parents[] = {"osc24M", "pll_c0cpux"};
 349 MUX_CLK(c0cpux_clk,
 350     CLK_C0CPUX,                                 /* id */
 351     "c0cpux", c0cpux_parents,                   /* name, parents */
 352     0x50, 12, 1);                               /* offset, shift, width */
 353
 354 static const char *c1cpux_parents[] = {"osc24M", "pll_c1cpux"};
 355 MUX_CLK(c1cpux_clk,
 356     CLK_C1CPUX,                                 /* id */
 357     "c1cpux", c1cpux_parents,                   /* name, parents */
 358     0x50, 28, 1);                               /* offset, shift, width */
 359
 360 static const char *axi0_parents[] = {"c0cpux"};
 361 DIV_CLK(axi0_clk,
 362     CLK_AXI0,                                   /* id */
 363     "axi0", axi0_parents,                       /* name, parents */
 364     0x50,                                       /* offset */
 365     0, 2,                                       /* shift, width */
 366     0, NULL);                                   /* flags, div table */
 367
 368 static const char *axi1_parents[] = {"c1cpux"};
 369 DIV_CLK(axi1_clk,
 370     CLK_AXI1,                                   /* id */
 371     "axi1", axi1_parents,                       /* name, parents */
 372     0x50,                                       /* offset */
 373     16, 2,                                      /* shift, width */
 374     0, NULL);                                   /* flags, div table */
 375
 376 static const char *ahb1_parents[] = {"osc16M-d512", "osc24M", "pll_periph", "pll_periph"};
 377 PREDIV_CLK_WITH_MASK(ahb1_clk,
 378     CLK_AHB1,                                   /* id */
 379     "ahb1", ahb1_parents,                       /* name, parents */
 380     0x54,                                       /* offset */
 381     12, 2,                                      /* mux */
 382     4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,        /* div */
 383     6, 2, 0, AW_CLK_FACTOR_HAS_COND,            /* prediv */
 384     (2 << 12), (2 << 12));                      /* prediv condition */
 385
 386 static const char *apb1_parents[] = {"ahb1"};
 387 DIV_CLK(apb1_clk,
 388     CLK_APB1,                                   /* id */
 389     "apb1", apb1_parents,                       /* name, parents */
 390     0x54,                                       /* offset */
 391     8, 2,                                       /* shift, width */
 392     0, NULL);                                   /* flags, div table */
 393
 394 static const char *apb2_parents[] = {"osc16M-d512", "osc24M", "pll_periph", "pll_periph"};
 395 NM_CLK(apb2_clk,
 396     CLK_APB2,                                   /* id */
 397     "apb2", apb2_parents,                       /* name, parents */
 398     0x58,                                       /* offset */
 399     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 400     0, 5, 0, 0,                                 /* m factor */
 401     24, 2,                                      /* mux */
 402     0,                                          /* gate */
 403     AW_CLK_HAS_MUX);
 404
 405 static const char *ahb2_parents[] = {"ahb1", "pll_periph"};
 406 PREDIV_CLK(ahb2_clk,
 407     CLK_AHB2,                                                   /* id */
 408     "ahb2", ahb2_parents,                                       /* name, parents */
 409     0x5c,
 410     0, 2,                                                       /* mux */
 411     0, 0, 1, AW_CLK_FACTOR_FIXED,                               /* div (fake) */
 412     0, 0, 2, AW_CLK_FACTOR_HAS_COND | AW_CLK_FACTOR_FIXED,      /* prediv */
 413     0, 2, 1);                                                   /* prediv cond */
 414
 415 /* Actually has a divider, but we don't use it */
 416 static const char *cci400_parents[] = {"osc24M", "pll_periph", "pll_hsic"};
 417 MUX_CLK(cci400_clk,
 418     CLK_CCI400,                                 /* id */
 419     "cci400", cci400_parents,                   /* name, parents */
 420     0x78, 24, 2);                               /* offset, shift, width */
 421
 422 static const char *mod_parents[] = {"osc24M", "pll_periph"};
 423
 424 NM_CLK(nand_clk,
 425     CLK_NAND,                                   /* id */
 426     "nand", mod_parents,                        /* name, parents */
 427     0x80,                                       /* offset */
 428     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 429     0, 4, 0, 0,                                 /* m factor */
 430     24, 2,                                      /* mux */
 431     31,                                         /* gate */
 432     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX);
 433
 434 NM_CLK(mmc0_clk,
 435     CLK_MMC0,                                   /* id */
 436     "mmc0", mod_parents,                        /* name, parents */
 437     0x88,                                       /* offset */
 438     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 439     0, 4, 0, 0,                                 /* m factor */
 440     24, 2,                                      /* mux */
 441     31,                                         /* gate */
 442     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
 443     AW_CLK_REPARENT);
 444 NM_CLK(mmc1_clk,
 445     CLK_MMC1,                                   /* id */
 446     "mmc1", mod_parents,                        /* name, parents */
 447     0x8c,                                       /* offset */
 448     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 449     0, 4, 0, 0,                                 /* m factor */
 450     24, 2,                                      /* mux */
 451     31,                                         /* gate */
 452     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
 453     AW_CLK_REPARENT);
 454 NM_CLK(mmc2_clk,
 455     CLK_MMC2,                                   /* id */
 456     "mmc2", mod_parents,                        /* name, parents */
 457     0x90,                                       /* offset */
 458     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 459     0, 4, 0, 0,                                 /* m factor */
 460     24, 2,                                      /* mux */
 461     31,                                         /* gate */
 462     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
 463     AW_CLK_REPARENT);
 464
 465 NM_CLK(ss_clk,
 466     CLK_SS,                                     /* id */
 467     "ss", mod_parents,                          /* name, parents */
 468     0x9c,                                       /* offset */
 469     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 470     0, 4, 0, 0,                                 /* m factor */
 471     24, 2,                                      /* mux */
 472     31,                                         /* gate */
 473     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX);
 474
 475 NM_CLK(spi0_clk,
 476     CLK_SPI0,                                   /* id */
 477     "spi0", mod_parents,                        /* name, parents */
 478     0xa0,                                       /* offset */
 479     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 480     0, 4, 0, 0,                                 /* m factor */
 481     24, 2,                                      /* mux */
 482     31,                                         /* gate */
 483     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX);
 484 NM_CLK(spi1_clk,
 485     CLK_SPI1,                                   /* id */
 486     "spi1", mod_parents,                        /* name, parents */
 487     0xa4,                                       /* offset */
 488     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 489     0, 4, 0, 0,                                 /* m factor */
 490     24, 2,                                      /* mux */
 491     31,                                         /* gate */
 492     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX);
 493
 494 static const char *daudio_parents[] = {"pll_audio"};
 495 NM_CLK(i2s0_clk,
 496     CLK_I2S0,                                   /* id */
 497     "i2s0", daudio_parents,                     /* name, parents */
 498     0xb0,                                       /* offset */
 499     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 500     0, 4, 0, 0,                                 /* m factor */
 501     0, 0,                                       /* mux */
 502     31,                                         /* gate */
 503     AW_CLK_HAS_GATE);
 504 NM_CLK(i2s1_clk,
 505     CLK_I2S1,                                   /* id */
 506     "i2s1", daudio_parents,                     /* name, parents */
 507     0xb4,                                       /* offset */
 508     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 509     0, 4, 0, 0,                                 /* m factor */
 510     0, 0,                                       /* mux */
 511     31,                                         /* gate */
 512     AW_CLK_HAS_GATE);
 513 NM_CLK(i2s2_clk,
 514     CLK_I2S2,                                   /* id */
 515     "i2s2", daudio_parents,                     /* name, parents */
 516     0xb8,                                       /* offset */
 517     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 518     0, 4, 0, 0,                                 /* m factor */
 519     0, 0,                                       /* mux */
 520     31,                                         /* gate */
 521     AW_CLK_HAS_GATE);
 522
 523 static const char *tdm_parents[] = {"pll_audio"};
 524 NM_CLK(tdm_clk,
 525     CLK_TDM,                                    /* id */
 526     "tdm", tdm_parents,                         /* name, parents */
 527     0xbc,                                       /* offset */
 528     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 529     0, 4, 0, 0,                                 /* m factor */
 530     0, 0,                                       /* mux */
 531     31,                                         /* gate */
 532     AW_CLK_HAS_GATE);
 533
 534 static const char *spdif_parents[] = {"pll_audio"};
 535 NM_CLK(spdif_clk,
 536     CLK_SPDIF,                                  /* id */
 537     "spdif", spdif_parents,                     /* name, parents */
 538     0xc0,                                       /* offset */
 539     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 540     0, 4, 0, 0,                                 /* m factor */
 541     0, 0,                                       /* mux */
 542     31,                                         /* gate */
 543     AW_CLK_HAS_GATE);
 544
 545 static const char *dram_parents[] = {"pll_ddr"};
 546 NM_CLK(dram_clk,
 547     CLK_DRAM,                                   /* id */
 548     "dram", dram_parents,                       /* name, parents */
 549     0xf4,                                       /* offset */
 550     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 551     0, 4, 0, 0,                                 /* m factor */
 552     0, 0,                                       /* mux */
 553     0,                                          /* gate */
 554     0);
 555
 556 static const char *tcon0_parents[] = {"pll_video0"};
 557 MUX_CLK(tcon0_clk,
 558     CLK_TCON0,                                  /* id */
 559     "tcon0", tcon0_parents,                     /* name, parents */
 560     0x118, 24, 2);                              /* offset, shift, width */
 561
 562 static const char *tcon1_parents[] = {"pll_video1"};
 563 NM_CLK(tcon1_clk,
 564     CLK_TCON1,                                  /* id */
 565     "tcon1", tcon1_parents,                     /* name, parents */
 566     0x11c,                                      /* offset */
 567     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 568     0, 4, 0, 0,                                 /* m factor */
 569     0, 0,                                       /* mux */
 570     31,                                         /* gate */
 571     AW_CLK_HAS_GATE);
 572
 573 static const char *csi_mclk_parents[] = {"pll_de", "osc24M"};
 574 NM_CLK(csi_mclk_clk,
 575     CLK_CSI_MCLK,                               /* id */
 576     "csi-mclk", csi_mclk_parents,               /* name, parents */
 577     0x134,                                      /* offset */
 578     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 579     0, 4, 0, 0,                                 /* m factor */
 580     8, 3,                                       /* mux */
 581     15,                                         /* gate */
 582     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);
 583
 584 static const char *csi_sclk_parents[] = {"pll_periph", "pll_ve"};
 585 NM_CLK(csi_sclk_clk,
 586     CLK_CSI_SCLK,                               /* id */
 587     "csi-sclk", csi_sclk_parents,               /* name, parents */
 588     0x134,                                      /* offset */
 589     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 590     16, 4, 0, 0,                                /* m factor */
 591     24, 3,                                      /* mux */
 592     31,                                         /* gate */
 593     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);
 594
 595 static const char *ve_parents[] = {"pll_ve"};
 596 NM_CLK(ve_clk,
 597     CLK_VE,                                     /* id */
 598     "ve", ve_parents,                           /* name, parents */
 599     0x13c,                                      /* offset */
 600     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 601     16, 3, 0, 0,                                /* m factor */
 602     0, 0,                                       /* mux */
 603     31,                                         /* gate */
 604     AW_CLK_HAS_GATE);
 605
 606 static const char *hdmi_parents[] = {"pll_video1"};
 607 NM_CLK(hdmi_clk,
 608     CLK_HDMI,                                   /* id */
 609     "hdmi", hdmi_parents,                       /* name, parents */
 610     0x150,                                      /* offset */
 611     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 612     0, 4, 0, 0,                                 /* m factor */
 613     24, 2,                                      /* mux */
 614     31,                                         /* gate */
 615     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);
 616
 617 static const char *mbus_parents[] = {"osc24M", "pll_periph", "pll_ddr"};
 618 NM_CLK(mbus_clk,
 619     CLK_MBUS,                                   /* id */
 620     "mbus", mbus_parents,                       /* name, parents */
 621     0x15c,                                      /* offset */
 622     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 623     0, 3, 0, 0,                                 /* m factor */
 624     24, 2,                                      /* mux */
 625     31,                                         /* gate */
 626     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);
 627
 628 static const char *mipi_dsi0_parents[] = {"pll_video0"};
 629 NM_CLK(mipi_dsi0_clk,
 630     CLK_MIPI_DSI0,                              /* id */
 631     "mipi-dsi0", mipi_dsi0_parents,             /* name, parents */
 632     0x168,                                      /* offset */
 633     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 634     0, 4, 0, 0,                                 /* m factor */
 635     24, 4,                                      /* mux */
 636     31,                                         /* gate */
 637     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);
 638
 639 static const char *mipi_dsi1_parents[] = {"osc24M", "pll_video0"};
 640 NM_CLK(mipi_dsi1_clk,
 641     CLK_MIPI_DSI1,                              /* id */
 642     "mipi-dsi1", mipi_dsi1_parents,             /* name, parents */
 643     0x16c,                                      /* offset */
 644     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 645     0, 4, 0, 0,                                 /* m factor */
 646     24, 4,                                      /* mux */
 647     31,                                         /* gate */
 648     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);
 649
 650 static const char *gpu_core_parents[] = {"pll_gpu"};
 651 NM_CLK(gpu_core_clk,
 652     CLK_GPU_CORE,                               /* id */
 653     "gpu-core", gpu_core_parents,               /* name, parents */
 654     0x1a0,                                      /* offset */
 655     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 656     0, 3, 0, 0,                                 /* m factor */
 657     0, 0,                                       /* mux */
 658     31,                                         /* gate */
 659     AW_CLK_HAS_GATE);
 660
 661 static const char *gpu_memory_parents[] = {"pll_gpu", "pll_periph"};
 662 NM_CLK(gpu_memory_clk,
 663     CLK_GPU_MEMORY,                             /* id */
 664     "gpu-memory", gpu_memory_parents,           /* name, parents */
 665     0x1a4,                                      /* offset */
 666     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 667     0, 3, 0, 0,                                 /* m factor */
 668     24, 1,                                      /* mux */
 669     31,                                         /* gate */
 670     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);
 671
 672 static const char *gpu_hyd_parents[] = {"pll_gpu"};
 673 NM_CLK(gpu_hyd_clk,
 674     CLK_GPU_HYD,                                /* id */
 675     "gpu-hyd", gpu_hyd_parents,                 /* name, parents */
 676     0x1a0,                                      /* offset */
 677     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 678     0, 3, 0, 0,                                 /* m factor */
 679     0, 0,                                       /* mux */
 680     31,                                         /* gate */
 681     AW_CLK_HAS_GATE);
 682
 683
 684 static struct aw_clk_nkmp_def *nkmp_clks[] = {
 685         &pll_audio_clk,
 686         &pll_video0_clk,
 687         &pll_ve_clk,
 688         &pll_ddr_clk,
 689         &pll_periph_clk,
 690         &pll_gpu_clk,
 691         &pll_hsic_clk,
 692         &pll_de_clk,
 693         &pll_video1_clk,
 694 };
 695
 696 static struct aw_clk_nm_def *nm_clks[] = {
 697         &pll_c0cpux_clk,
 698         &pll_c1cpux_clk,
 699         &apb2_clk,
 700         &nand_clk,
 701         &mmc0_clk,
 702         &mmc1_clk,
 703         &mmc2_clk,
 704         &ss_clk,
 705         &spi0_clk,
 706         &spi1_clk,
 707         &i2s0_clk,
 708         &i2s1_clk,
 709         &i2s2_clk,
 710         &tdm_clk,
 711         &spdif_clk,
 712         &dram_clk,
 713         &tcon1_clk,
 714         &csi_mclk_clk,
 715         &csi_sclk_clk,
 716         &ve_clk,
 717         &hdmi_clk,
 718         &mbus_clk,
 719         &mipi_dsi0_clk,
 720         &mipi_dsi1_clk,
 721         &gpu_core_clk,
 722         &gpu_memory_clk,
 723         &gpu_hyd_clk,
 724 };
 725
 726 static struct aw_clk_prediv_mux_def *prediv_mux_clks[] = {
 727         &ahb1_clk,
 728         &ahb2_clk,
 729 };
 730
 731 static struct clk_mux_def *mux_clks[] = {
 732         &c0cpux_clk,
 733         &c1cpux_clk,
 734         &cci400_clk,
 735         &tcon0_clk,
 736 };
 737
 738 static struct clk_div_def *div_clks[] = {
 739         &axi0_clk,
 740         &axi1_clk,
 741         &apb1_clk,
 742 };
 743
 744 static struct clk_fixed_def *fixed_factor_clks[] = {
 745         &osc12m_clk,
 746 };
 747
 748 static struct aw_clk_init init_clks[] = {
 749         {"ahb1", "pll_periph", 0, false},
 750         {"ahb2", "ahb1", 0, false},
 751         {"dram", "pll_ddr", 0, false},
 752 };
 753
 754 void
 755 ccu_a83t_register_clocks(struct aw_ccung_softc *sc)
 756 {
 757         int i;
 758
 759         sc->resets = a83t_ccu_resets;
 760         sc->nresets = nitems(a83t_ccu_resets);
 761         sc->gates = a83t_ccu_gates;
 762         sc->ngates = nitems(a83t_ccu_gates);
 763         sc->clk_init = init_clks;
 764         sc->n_clk_init = nitems(init_clks);
 765
 766         for (i = 0; i < nitems(nkmp_clks); i++)
 767                 aw_clk_nkmp_register(sc->clkdom, nkmp_clks[i]);
 768         for (i = 0; i < nitems(nm_clks); i++)
 769                 aw_clk_nm_register(sc->clkdom, nm_clks[i]);
 770         for (i = 0; i < nitems(prediv_mux_clks); i++)
 771                 aw_clk_prediv_mux_register(sc->clkdom, prediv_mux_clks[i]);
 772
 773         for (i = 0; i < nitems(mux_clks); i++)
 774                 clknode_mux_register(sc->clkdom, mux_clks[i]);
 775         for (i = 0; i < nitems(div_clks); i++)
 776                 clknode_div_register(sc->clkdom, div_clks[i]);
 777         for (i = 0; i < nitems(fixed_factor_clks); i++)
 778                 clknode_fixed_register(sc->clkdom, fixed_factor_clks[i]);
 779 }