sys/arm/allwinner/clkng/ccu_a83t.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2017 Kyle Evans <kevans@FreeBSD.org>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  20  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  21  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  22  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  23  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD$
  28  */
  29
  30 #include <sys/cdefs.h>
  31 __FBSDID("$FreeBSD$");
  32
  33 #include <sys/param.h>
  34 #include <sys/systm.h>
  35 #include <sys/bus.h>
  36 #include <sys/rman.h>
  37 #include <sys/kernel.h>
  38 #include <sys/module.h>
  39 #include <machine/bus.h>
  40
  41 #include <dev/fdt/simplebus.h>
  42
  43 #include <dev/ofw/ofw_bus.h>
  44 #include <dev/ofw/ofw_bus_subr.h>
  45
  46 #include <dev/extres/clk/clk_div.h>
  47 #include <dev/extres/clk/clk_fixed.h>
  48 #include <dev/extres/clk/clk_mux.h>
  49
  50 #include <arm/allwinner/clkng/aw_ccung.h>
  51
  52 #include <gnu/dts/include/dt-bindings/clock/sun8i-a83t-ccu.h>
  53 #include <gnu/dts/include/dt-bindings/reset/sun8i-a83t-ccu.h>
  54
  55 /* Non-exported clocks */
  56
  57 #define CLK_PLL_C0CPUX          0
  58 #define CLK_PLL_C1CPUX          1
  59 #define CLK_PLL_AUDIO           2
  60 #define CLK_PLL_VIDEO0          3
  61 #define CLK_PLL_VE              4
  62 #define CLK_PLL_DDR             5
  63
  64 #define CLK_PLL_GPU             7
  65 #define CLK_PLL_HSIC            8
  66 #define CLK_PLL_VIDEO1          10
  67
  68 #define CLK_AXI0                13
  69 #define CLK_AXI1                14
  70 #define CLK_AHB1                15
  71 #define CLK_APB1                16
  72 #define CLK_APB2                17
  73 #define CLK_AHB2                18
  74
  75 #define CLK_CCI400              58
  76
  77 #define CLK_DRAM                82
  78
  79 #define CLK_MBUS                95
  80
  81 /* Non-exported fixed clocks */
  82 #define CLK_OSC_12M             150
  83
  84
  85 static struct aw_ccung_reset a83t_ccu_resets[] = {
  86         CCU_RESET(RST_USB_PHY0, 0xcc, 0)
  87         CCU_RESET(RST_USB_PHY1, 0xcc, 1)
  88         CCU_RESET(RST_USB_HSIC, 0xcc, 2)
  89
  90         CCU_RESET(RST_DRAM, 0xf4, 31)
  91         CCU_RESET(RST_MBUS, 0xfc, 31)
  92
  93         CCU_RESET(RST_BUS_MIPI_DSI, 0x2c0, 1)
  94         CCU_RESET(RST_BUS_SS, 0x2c0, 5)
  95         CCU_RESET(RST_BUS_DMA, 0x2c0, 6)
  96         CCU_RESET(RST_BUS_MMC0, 0x2c0, 8)
  97         CCU_RESET(RST_BUS_MMC1, 0x2c0, 9)
  98         CCU_RESET(RST_BUS_MMC2, 0x2c0, 10)
  99         CCU_RESET(RST_BUS_NAND, 0x2c0, 13)
 100         CCU_RESET(RST_BUS_DRAM, 0x2c0, 14)
 101         CCU_RESET(RST_BUS_EMAC, 0x2c0, 17)
 102         CCU_RESET(RST_BUS_HSTIMER, 0x2c0, 19)
 103         CCU_RESET(RST_BUS_SPI0, 0x2c0, 20)
 104         CCU_RESET(RST_BUS_SPI1, 0x2c0, 21)
 105         CCU_RESET(RST_BUS_OTG, 0x2c0, 24)
 106         CCU_RESET(RST_BUS_EHCI0, 0x2c0, 26)
 107         CCU_RESET(RST_BUS_EHCI1, 0x2c0, 27)
 108         CCU_RESET(RST_BUS_OHCI0, 0x2c0, 29)
 109
 110         CCU_RESET(RST_BUS_VE, 0x2c4, 0)
 111         CCU_RESET(RST_BUS_TCON0, 0x2c4, 4)
 112         CCU_RESET(RST_BUS_TCON1, 0x2c4, 5)
 113         CCU_RESET(RST_BUS_CSI, 0x2c4, 8)
 114         CCU_RESET(RST_BUS_HDMI0, 0x2c4, 10)
 115         CCU_RESET(RST_BUS_HDMI1, 0x2c4, 11)
 116         CCU_RESET(RST_BUS_DE, 0x2c4, 12)
 117         CCU_RESET(RST_BUS_GPU, 0x2c4, 20)
 118         CCU_RESET(RST_BUS_MSGBOX, 0x2c4, 21)
 119         CCU_RESET(RST_BUS_SPINLOCK, 0x2c4, 22)
 120
 121         CCU_RESET(RST_BUS_LVDS, 0x2c8, 0)
 122
 123         CCU_RESET(RST_BUS_SPDIF, 0x2d0, 1)
 124         CCU_RESET(RST_BUS_I2S0, 0x2d0, 12)
 125         CCU_RESET(RST_BUS_I2S1, 0x2d0, 13)
 126         CCU_RESET(RST_BUS_I2S2, 0x2d0, 14)
 127         CCU_RESET(RST_BUS_TDM, 0x2d0, 15)
 128
 129         CCU_RESET(RST_BUS_I2C0, 0x2d8, 0)
 130         CCU_RESET(RST_BUS_I2C1, 0x2d8, 1)
 131         CCU_RESET(RST_BUS_I2C2, 0x2d8, 2)
 132         CCU_RESET(RST_BUS_UART0, 0x2d8, 16)
 133         CCU_RESET(RST_BUS_UART1, 0x2d8, 17)
 134         CCU_RESET(RST_BUS_UART2, 0x2d8, 18)
 135         CCU_RESET(RST_BUS_UART3, 0x2d8, 19)
 136         CCU_RESET(RST_BUS_UART4, 0x2d8, 20)
 137 };
 138
 139 static struct aw_ccung_gate a83t_ccu_gates[] = {
 140         CCU_GATE(CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 0x60, 1)
 141         CCU_GATE(CLK_BUS_SS, "bus-ss", "ahb1", 0x60, 5)
 142         CCU_GATE(CLK_BUS_DMA, "bus-dma", "ahb1", 0x60, 6)
 143         CCU_GATE(CLK_BUS_MMC0, "bus-mmc0", "ahb1", 0x60, 8)
 144         CCU_GATE(CLK_BUS_MMC1, "bus-mmc1", "ahb1", 0x60, 9)
 145         CCU_GATE(CLK_BUS_MMC2, "bus-mmc2", "ahb1", 0x60, 10)
 146         CCU_GATE(CLK_BUS_NAND, "bus-nand", "ahb1", 0x60, 13)
 147         CCU_GATE(CLK_BUS_DRAM, "bus-dram", "ahb1", 0x60, 14)
 148         CCU_GATE(CLK_BUS_EMAC, "bus-emac", "ahb1", 0x60, 17)
 149         CCU_GATE(CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 0x60, 19)
 150         CCU_GATE(CLK_BUS_SPI0, "bus-spi0", "ahb1", 0x60, 20)
 151         CCU_GATE(CLK_BUS_SPI1, "bus-spi1", "ahb1", 0x60, 21)
 152         CCU_GATE(CLK_BUS_OTG, "bus-otg", "ahb1", 0x60, 24)
 153         CCU_GATE(CLK_BUS_EHCI0, "bus-ehci0", "ahb2", 0x60, 26)
 154         CCU_GATE(CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 0x60, 27)
 155         CCU_GATE(CLK_BUS_OHCI0, "bus-ohci0", "ahb2", 0x60, 29)
 156
 157         CCU_GATE(CLK_BUS_VE, "bus-ve", "ahb1", 0x64, 0)
 158         CCU_GATE(CLK_BUS_TCON0, "bus-tcon0", "ahb1", 0x64, 4)
 159         CCU_GATE(CLK_BUS_TCON1, "bus-tcon1", "ahb1", 0x64, 5)
 160         CCU_GATE(CLK_BUS_CSI, "bus-csi", "ahb1", 0x64, 8)
 161         CCU_GATE(CLK_BUS_HDMI, "bus-hdmi", "ahb1", 0x64, 11)
 162         CCU_GATE(CLK_BUS_DE, "bus-de", "ahb1", 0x64, 12)
 163         CCU_GATE(CLK_BUS_GPU, "bus-gpu", "ahb1", 0x64, 20)
 164         CCU_GATE(CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 0x64, 21)
 165         CCU_GATE(CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 0x64, 22)
 166
 167         CCU_GATE(CLK_BUS_SPDIF, "bus-spdif", "apb1", 0x68, 1)
 168         CCU_GATE(CLK_BUS_PIO, "bus-pio", "apb1", 0x68, 5)
 169         CCU_GATE(CLK_BUS_I2S0, "bus-i2s0", "apb1", 0x68, 12)
 170         CCU_GATE(CLK_BUS_I2S1, "bus-i2s1", "apb1", 0x68, 13)
 171         CCU_GATE(CLK_BUS_I2S2, "bus-i2s2", "apb1", 0x68, 14)
 172         CCU_GATE(CLK_BUS_TDM, "bus-tdm", "apb1", 0x68, 15)
 173
 174         CCU_GATE(CLK_BUS_I2C0, "bus-i2c0", "apb2", 0x6c, 0)
 175         CCU_GATE(CLK_BUS_I2C1, "bus-i2c1", "apb2", 0x6c, 1)
 176         CCU_GATE(CLK_BUS_I2C2, "bus-i2c2", "apb2", 0x6c, 2)
 177         CCU_GATE(CLK_BUS_UART0, "bus-uart0", "apb2", 0x6c, 16)
 178         CCU_GATE(CLK_BUS_UART1, "bus-uart1", "apb2", 0x6c, 17)
 179         CCU_GATE(CLK_BUS_UART2, "bus-uart2", "apb2", 0x6c, 18)
 180         CCU_GATE(CLK_BUS_UART3, "bus-uart3", "apb2", 0x6c, 19)
 181         CCU_GATE(CLK_BUS_UART4, "bus-uart4", "apb2", 0x6c, 20)
 182
 183         CCU_GATE(CLK_USB_PHY0, "usb-phy0", "osc24M", 0xcc, 8)
 184         CCU_GATE(CLK_USB_PHY1, "usb-phy1", "osc24M", 0xcc, 9)
 185         CCU_GATE(CLK_USB_HSIC, "usb-hsic", "pll_hsic", 0xcc, 10)
 186         CCU_GATE(CLK_USB_HSIC_12M, "usb-hsic-12M", "osc12M", 0xcc, 11)
 187         CCU_GATE(CLK_USB_OHCI0, "usb-ohci0", "osc12M", 0xcc, 16)
 188
 189         CCU_GATE(CLK_DRAM_VE, "dram-ve", "dram", 0x100, 0)
 190         CCU_GATE(CLK_DRAM_CSI, "dram-csi", "dram", 0x100, 1)
 191
 192         CCU_GATE(CLK_CSI_MISC, "csi-misc", "osc24M", 0x130, 16)
 193         CCU_GATE(CLK_MIPI_CSI, "mipi-csi", "osc24M", 0x130, 31)
 194
 195         CCU_GATE(CLK_AVS, "avs", "osc24M", 0x144, 31)
 196
 197         CCU_GATE(CLK_HDMI_SLOW, "hdmi-ddc", "osc24M", 0x154, 31)
 198 };
 199
 200 static const char *osc12m_parents[] = {"osc24M"};
 201 FIXED_CLK(osc12m_clk,
 202     CLK_OSC_12M,                                /* id */
 203     "osc12M", osc12m_parents,                   /* name, parents */
 204     0,                                          /* freq */
 205     1,                                          /* mult */
 206     2,                                          /* div */
 207     0);                                         /* flags */
 208
 209 /* CPU PLL are 24Mhz * N / P */
 210 static const char *pll_c0cpux_parents[] = {"osc24M"};
 211 static const char *pll_c1cpux_parents[] = {"osc24M"};
 212 NKMP_CLK(pll_c0cpux_clk,
 213     CLK_PLL_C0CPUX,                             /* id */
 214     "pll_c0cpux", pll_c0cpux_parents,           /* name, parents */
 215     0x00,                                       /* offset */
 216     8, 8, 0, AW_CLK_FACTOR_ZERO_BASED,          /* n factor */
 217     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* k factor (fake) */
 218     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* m factor */
 219     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* p factor (fake) */
 220     0, 0,                                       /* lock */
 221     31,                                         /* gate */
 222     AW_CLK_HAS_GATE | AW_CLK_SCALE_CHANGE);     /* flags */
 223 NKMP_CLK(pll_c1cpux_clk,
 224     CLK_PLL_C1CPUX,                             /* id */
 225     "pll_c1cpux", pll_c1cpux_parents,           /* name, parents */
 226     0x04,                                       /* offset */
 227     8, 8, 0, AW_CLK_FACTOR_ZERO_BASED,          /* n factor */
 228     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* k factor (fake) */
 229     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* m factor */
 230     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* p factor (fake) */
 231     0, 0,                                       /* lock */
 232     31,                                         /* gate */
 233     AW_CLK_HAS_GATE | AW_CLK_SCALE_CHANGE);     /* flags */
 234
 235 static const char *pll_audio_parents[] = {"osc24M"};
 236 NKMP_CLK(pll_audio_clk,
 237     CLK_PLL_AUDIO,                              /* id */
 238     "pll_audio", pll_audio_parents,             /* name, parents */
 239     0x08,                                       /* offset */
 240     8, 8, 0, AW_CLK_FACTOR_ZERO_BASED,          /* n factor */
 241     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* k factor (fake) */
 242     16, 1, 0, 0,                                /* m factor */
 243     18, 1, 0, 0,                                /* p factor */
 244     31,                                         /* gate */
 245     0, 0,                                       /* lock */
 246     AW_CLK_HAS_GATE);                           /* flags */
 247
 248 static const char *pll_video0_parents[] = {"osc24M"};
 249 NKMP_CLK(pll_video0_clk,
 250     CLK_PLL_VIDEO0,                             /* id */
 251     "pll_video0", pll_video0_parents,           /* name, parents */
 252     0x10,                                       /* offset */
 253     8, 8, 0, AW_CLK_FACTOR_ZERO_BASED,          /* n factor */
 254     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* k factor (fake) */
 255     16, 1, 0, 0,                                /* m factor */
 256     0, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,        /* p factor */
 257     31,                                         /* gate */
 258     0, 0,                                       /* lock */
 259     AW_CLK_HAS_GATE);                           /* flags */
 260
 261 static const char *pll_ve_parents[] = {"osc24M"};
 262 NKMP_CLK(pll_ve_clk,
 263     CLK_PLL_VE,                                 /* id */
 264     "pll_ve", pll_ve_parents,                   /* name, parents */
 265     0x18,                                       /* offset */
 266     8, 8, 0, AW_CLK_FACTOR_ZERO_BASED,          /* n factor */
 267     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* k factor (fake) */
 268     16, 1, 0, 0,                                /* m factor */
 269     18, 1, 0, 0,                                /* p factor */
 270     31,                                         /* gate */
 271     0, 0,                                       /* lock */
 272     AW_CLK_HAS_GATE);                           /* flags */
 273
 274 static const char *pll_ddr_parents[] = {"osc24M"};
 275 NKMP_CLK(pll_ddr_clk,
 276     CLK_PLL_DDR,                                /* id */
 277     "pll_ddr", pll_ddr_parents,                 /* name, parents */
 278     0x20,                                       /* offset */
 279     8, 5, 0, 0,                                 /* n factor */
 280     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* k factor (fake) */
 281     16, 1, 0, 0,                                /* m factor */
 282     18, 1, 0, 0,                                /* p factor */
 283     31,                                         /* gate */
 284     0, 0,                                       /* lock */
 285     AW_CLK_HAS_GATE);                           /* flags */
 286
 287 static const char *pll_periph_parents[] = {"osc24M"};
 288 NKMP_CLK(pll_periph_clk,
 289     CLK_PLL_PERIPH,                             /* id */
 290     "pll_periph", pll_periph_parents,           /* name, parents */
 291     0x28,                                       /* offset */
 292     8, 8, 0, AW_CLK_FACTOR_ZERO_BASED,          /* n factor */
 293     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* k factor (fake) */
 294     16, 1, 1, 0,                                /* m factor */
 295     18, 1, 1, 0,                                /* p factor */
 296     31,                                         /* gate */
 297     0, 0,                                       /* lock */
 298     AW_CLK_HAS_GATE);                           /* flags */
 299
 300 static const char *pll_gpu_parents[] = {"osc24M"};
 301 NKMP_CLK(pll_gpu_clk,
 302     CLK_PLL_GPU,                                /* id */
 303     "pll_gpu", pll_gpu_parents,                 /* name, parents */
 304     0x38,                                       /* offset */
 305     8, 8, 0, AW_CLK_FACTOR_ZERO_BASED,          /* n factor */
 306     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* k factor (fake) */
 307     16, 1, 1, 0,                                /* m factor */
 308     18, 1, 1, 0,                                /* p factor */
 309     31,                                         /* gate */
 310     0, 0,                                       /* lock */
 311     AW_CLK_HAS_GATE);                           /* flags */
 312
 313 static const char *pll_hsic_parents[] = {"osc24M"};
 314 NKMP_CLK(pll_hsic_clk,
 315     CLK_PLL_HSIC,                               /* id */
 316     "pll_hsic", pll_hsic_parents,               /* name, parents */
 317     0x44,                                       /* offset */
 318     8, 8, 0, AW_CLK_FACTOR_ZERO_BASED,          /* n factor */
 319     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* k factor (fake) */
 320     16, 1, 1, 0,                                /* m factor */
 321     18, 1, 1, 0,                                /* p factor */
 322     31,                                         /* gate */
 323     0, 0,                                       /* lock */
 324     AW_CLK_HAS_GATE);                           /* flags */
 325
 326 static const char *pll_de_parents[] = {"osc24M"};
 327 NKMP_CLK(pll_de_clk,
 328     CLK_PLL_DE,                                 /* id */
 329     "pll_de", pll_de_parents,                   /* name, parents */
 330     0x48,                                       /* offset */
 331     8, 8, 0, AW_CLK_FACTOR_ZERO_BASED,          /* n factor */
 332     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* k factor (fake) */
 333     16, 1, 1, 0,                                /* m factor */
 334     18, 1, 1, 0,                                /* p factor */
 335     31,                                         /* gate */
 336     0, 0,                                       /* lock */
 337     AW_CLK_HAS_GATE);                           /* flags */
 338
 339 static const char *pll_video1_parents[] = {"osc24M"};
 340 NKMP_CLK(pll_video1_clk,
 341     CLK_PLL_VIDEO1,                             /* id */
 342     "pll_video1", pll_video1_parents,           /* name, parents */
 343     0x4c,                                       /* offset */
 344     8, 8, 0, AW_CLK_FACTOR_ZERO_BASED,          /* n factor */
 345     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* k factor (fake) */
 346     16, 1, 1, 0,                                /* m factor */
 347     0, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,        /* p factor */
 348     31,                                         /* gate */
 349     0, 0,                                       /* lock */
 350     AW_CLK_HAS_GATE);                           /* flags */
 351
 352 static const char *c0cpux_parents[] = {"osc24M", "pll_c0cpux"};
 353 MUX_CLK(c0cpux_clk,
 354     CLK_C0CPUX,                                 /* id */
 355     "c0cpux", c0cpux_parents,                   /* name, parents */
 356     0x50, 12, 1);                               /* offset, shift, width */
 357
 358 static const char *c1cpux_parents[] = {"osc24M", "pll_c1cpux"};
 359 MUX_CLK(c1cpux_clk,
 360     CLK_C1CPUX,                                 /* id */
 361     "c1cpux", c1cpux_parents,                   /* name, parents */
 362     0x50, 28, 1);                               /* offset, shift, width */
 363
 364 static const char *axi0_parents[] = {"c0cpux"};
 365 DIV_CLK(axi0_clk,
 366     CLK_AXI0,                                   /* id */
 367     "axi0", axi0_parents,                       /* name, parents */
 368     0x50,                                       /* offset */
 369     0, 2,                                       /* shift, width */
 370     0, NULL);                                   /* flags, div table */
 371
 372 static const char *axi1_parents[] = {"c1cpux"};
 373 DIV_CLK(axi1_clk,
 374     CLK_AXI1,                                   /* id */
 375     "axi1", axi1_parents,                       /* name, parents */
 376     0x50,                                       /* offset */
 377     16, 2,                                      /* shift, width */
 378     0, NULL);                                   /* flags, div table */
 379
 380 static const char *ahb1_parents[] = {"osc16M-d512", "osc24M", "pll_periph", "pll_periph"};
 381 PREDIV_CLK_WITH_MASK(ahb1_clk,
 382     CLK_AHB1,                                   /* id */
 383     "ahb1", ahb1_parents,                       /* name, parents */
 384     0x54,                                       /* offset */
 385     12, 2,                                      /* mux */
 386     4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,        /* div */
 387     6, 2, 0, AW_CLK_FACTOR_HAS_COND,            /* prediv */
 388     (2 << 12), (2 << 12));                      /* prediv condition */
 389
 390 static const char *apb1_parents[] = {"ahb1"};
 391 DIV_CLK(apb1_clk,
 392     CLK_APB1,                                   /* id */
 393     "apb1", apb1_parents,                       /* name, parents */
 394     0x54,                                       /* offset */
 395     8, 2,                                       /* shift, width */
 396     0, NULL);                                   /* flags, div table */
 397
 398 static const char *apb2_parents[] = {"osc16M-d512", "osc24M", "pll_periph", "pll_periph"};
 399 NM_CLK(apb2_clk,
 400     CLK_APB2,                                   /* id */
 401     "apb2", apb2_parents,                       /* name, parents */
 402     0x58,                                       /* offset */
 403     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 404     0, 5, 0, 0,                                 /* m factor */
 405     24, 2,                                      /* mux */
 406     0,                                          /* gate */
 407     AW_CLK_HAS_MUX);
 408
 409 static const char *ahb2_parents[] = {"ahb1", "pll_periph"};
 410 PREDIV_CLK(ahb2_clk,
 411     CLK_AHB2,                                                   /* id */
 412     "ahb2", ahb2_parents,                                       /* name, parents */
 413     0x5c,
 414     0, 2,                                                       /* mux */
 415     0, 0, 1, AW_CLK_FACTOR_FIXED,                               /* div (fake) */
 416     0, 0, 2, AW_CLK_FACTOR_HAS_COND | AW_CLK_FACTOR_FIXED,      /* prediv */
 417     0, 2, 1);                                                   /* prediv cond */
 418
 419 /* Actually has a divider, but we don't use it */
 420 static const char *cci400_parents[] = {"osc24M", "pll_periph", "pll_hsic"};
 421 MUX_CLK(cci400_clk,
 422     CLK_CCI400,                                 /* id */
 423     "cci400", cci400_parents,                   /* name, parents */
 424     0x78, 24, 2);                               /* offset, shift, width */
 425
 426 static const char *mod_parents[] = {"osc24M", "pll_periph"};
 427
 428 NM_CLK(nand_clk,
 429     CLK_NAND,                                   /* id */
 430     "nand", mod_parents,                        /* name, parents */
 431     0x80,                                       /* offset */
 432     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 433     0, 4, 0, 0,                                 /* m factor */
 434     24, 2,                                      /* mux */
 435     31,                                         /* gate */
 436     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX);
 437
 438 NM_CLK(mmc0_clk,
 439     CLK_MMC0,                                   /* id */
 440     "mmc0", mod_parents,                        /* name, parents */
 441     0x88,                                       /* offset */
 442     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 443     0, 4, 0, 0,                                 /* m factor */
 444     24, 2,                                      /* mux */
 445     31,                                         /* gate */
 446     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
 447     AW_CLK_REPARENT);
 448 NM_CLK(mmc1_clk,
 449     CLK_MMC1,                                   /* id */
 450     "mmc1", mod_parents,                        /* name, parents */
 451     0x8c,                                       /* offset */
 452     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 453     0, 4, 0, 0,                                 /* m factor */
 454     24, 2,                                      /* mux */
 455     31,                                         /* gate */
 456     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
 457     AW_CLK_REPARENT);
 458 NM_CLK(mmc2_clk,
 459     CLK_MMC2,                                   /* id */
 460     "mmc2", mod_parents,                        /* name, parents */
 461     0x90,                                       /* offset */
 462     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 463     0, 4, 0, 0,                                 /* m factor */
 464     24, 2,                                      /* mux */
 465     31,                                         /* gate */
 466     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
 467     AW_CLK_REPARENT);
 468
 469 NM_CLK(ss_clk,
 470     CLK_SS,                                     /* id */
 471     "ss", mod_parents,                          /* name, parents */
 472     0x9c,                                       /* offset */
 473     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 474     0, 4, 0, 0,                                 /* m factor */
 475     24, 2,                                      /* mux */
 476     31,                                         /* gate */
 477     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX);
 478
 479 NM_CLK(spi0_clk,
 480     CLK_SPI0,                                   /* id */
 481     "spi0", mod_parents,                        /* name, parents */
 482     0xa0,                                       /* offset */
 483     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 484     0, 4, 0, 0,                                 /* m factor */
 485     24, 2,                                      /* mux */
 486     31,                                         /* gate */
 487     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX);
 488 NM_CLK(spi1_clk,
 489     CLK_SPI1,                                   /* id */
 490     "spi1", mod_parents,                        /* name, parents */
 491     0xa4,                                       /* offset */
 492     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 493     0, 4, 0, 0,                                 /* m factor */
 494     24, 2,                                      /* mux */
 495     31,                                         /* gate */
 496     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX);
 497
 498 static const char *daudio_parents[] = {"pll_audio"};
 499 NM_CLK(i2s0_clk,
 500     CLK_I2S0,                                   /* id */
 501     "i2s0", daudio_parents,                     /* name, parents */
 502     0xb0,                                       /* offset */
 503     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 504     0, 4, 0, 0,                                 /* m factor */
 505     0, 0,                                       /* mux */
 506     31,                                         /* gate */
 507     AW_CLK_HAS_GATE);
 508 NM_CLK(i2s1_clk,
 509     CLK_I2S1,                                   /* id */
 510     "i2s1", daudio_parents,                     /* name, parents */
 511     0xb4,                                       /* offset */
 512     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 513     0, 4, 0, 0,                                 /* m factor */
 514     0, 0,                                       /* mux */
 515     31,                                         /* gate */
 516     AW_CLK_HAS_GATE);
 517 NM_CLK(i2s2_clk,
 518     CLK_I2S2,                                   /* id */
 519     "i2s2", daudio_parents,                     /* name, parents */
 520     0xb8,                                       /* offset */
 521     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 522     0, 4, 0, 0,                                 /* m factor */
 523     0, 0,                                       /* mux */
 524     31,                                         /* gate */
 525     AW_CLK_HAS_GATE);
 526
 527 static const char *tdm_parents[] = {"pll_audio"};
 528 NM_CLK(tdm_clk,
 529     CLK_TDM,                                    /* id */
 530     "tdm", tdm_parents,                         /* name, parents */
 531     0xbc,                                       /* offset */
 532     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 533     0, 4, 0, 0,                                 /* m factor */
 534     0, 0,                                       /* mux */
 535     31,                                         /* gate */
 536     AW_CLK_HAS_GATE);
 537
 538 static const char *spdif_parents[] = {"pll_audio"};
 539 NM_CLK(spdif_clk,
 540     CLK_SPDIF,                                  /* id */
 541     "spdif", spdif_parents,                     /* name, parents */
 542     0xc0,                                       /* offset */
 543     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 544     0, 4, 0, 0,                                 /* m factor */
 545     0, 0,                                       /* mux */
 546     31,                                         /* gate */
 547     AW_CLK_HAS_GATE);
 548
 549 static const char *dram_parents[] = {"pll_ddr"};
 550 NM_CLK(dram_clk,
 551     CLK_DRAM,                                   /* id */
 552     "dram", dram_parents,                       /* name, parents */
 553     0xf4,                                       /* offset */
 554     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 555     0, 4, 0, 0,                                 /* m factor */
 556     0, 0,                                       /* mux */
 557     0,                                          /* gate */
 558     0);
 559
 560 static const char *tcon0_parents[] = {"pll_video0"};
 561 MUX_CLK(tcon0_clk,
 562     CLK_TCON0,                                  /* id */
 563     "tcon0", tcon0_parents,                     /* name, parents */
 564     0x118, 24, 2);                              /* offset, shift, width */
 565
 566 static const char *tcon1_parents[] = {"pll_video1"};
 567 NM_CLK(tcon1_clk,
 568     CLK_TCON1,                                  /* id */
 569     "tcon1", tcon1_parents,                     /* name, parents */
 570     0x11c,                                      /* offset */
 571     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 572     0, 4, 0, 0,                                 /* m factor */
 573     0, 0,                                       /* mux */
 574     31,                                         /* gate */
 575     AW_CLK_HAS_GATE);
 576
 577 static const char *csi_mclk_parents[] = {"pll_de", "osc24M"};
 578 NM_CLK(csi_mclk_clk,
 579     CLK_CSI_MCLK,                               /* id */
 580     "csi-mclk", csi_mclk_parents,               /* name, parents */
 581     0x134,                                      /* offset */
 582     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 583     0, 4, 0, 0,                                 /* m factor */
 584     8, 3,                                       /* mux */
 585     15,                                         /* gate */
 586     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);
 587
 588 static const char *csi_sclk_parents[] = {"pll_periph", "pll_ve"};
 589 NM_CLK(csi_sclk_clk,
 590     CLK_CSI_SCLK,                               /* id */
 591     "csi-sclk", csi_sclk_parents,               /* name, parents */
 592     0x134,                                      /* offset */
 593     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 594     16, 4, 0, 0,                                /* m factor */
 595     24, 3,                                      /* mux */
 596     31,                                         /* gate */
 597     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);
 598
 599 static const char *ve_parents[] = {"pll_ve"};
 600 NM_CLK(ve_clk,
 601     CLK_VE,                                     /* id */
 602     "ve", ve_parents,                           /* name, parents */
 603     0x13c,                                      /* offset */
 604     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 605     16, 3, 0, 0,                                /* m factor */
 606     0, 0,                                       /* mux */
 607     31,                                         /* gate */
 608     AW_CLK_HAS_GATE);
 609
 610 static const char *hdmi_parents[] = {"pll_video1"};
 611 NM_CLK(hdmi_clk,
 612     CLK_HDMI,                                   /* id */
 613     "hdmi", hdmi_parents,                       /* name, parents */
 614     0x150,                                      /* offset */
 615     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 616     0, 4, 0, 0,                                 /* m factor */
 617     24, 2,                                      /* mux */
 618     31,                                         /* gate */
 619     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);
 620
 621 static const char *mbus_parents[] = {"osc24M", "pll_periph", "pll_ddr"};
 622 NM_CLK(mbus_clk,
 623     CLK_MBUS,                                   /* id */
 624     "mbus", mbus_parents,                       /* name, parents */
 625     0x15c,                                      /* offset */
 626     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 627     0, 3, 0, 0,                                 /* m factor */
 628     24, 2,                                      /* mux */
 629     31,                                         /* gate */
 630     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);
 631
 632 static const char *mipi_dsi0_parents[] = {"pll_video0"};
 633 NM_CLK(mipi_dsi0_clk,
 634     CLK_MIPI_DSI0,                              /* id */
 635     "mipi-dsi0", mipi_dsi0_parents,             /* name, parents */
 636     0x168,                                      /* offset */
 637     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 638     0, 4, 0, 0,                                 /* m factor */
 639     24, 4,                                      /* mux */
 640     31,                                         /* gate */
 641     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);
 642
 643 static const char *mipi_dsi1_parents[] = {"osc24M", "pll_video0"};
 644 NM_CLK(mipi_dsi1_clk,
 645     CLK_MIPI_DSI1,                              /* id */
 646     "mipi-dsi1", mipi_dsi1_parents,             /* name, parents */
 647     0x16c,                                      /* offset */
 648     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 649     0, 4, 0, 0,                                 /* m factor */
 650     24, 4,                                      /* mux */
 651     31,                                         /* gate */
 652     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);
 653
 654 static const char *gpu_core_parents[] = {"pll_gpu"};
 655 NM_CLK(gpu_core_clk,
 656     CLK_GPU_CORE,                               /* id */
 657     "gpu-core", gpu_core_parents,               /* name, parents */
 658     0x1a0,                                      /* offset */
 659     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 660     0, 3, 0, 0,                                 /* m factor */
 661     0, 0,                                       /* mux */
 662     31,                                         /* gate */
 663     AW_CLK_HAS_GATE);
 664
 665 static const char *gpu_memory_parents[] = {"pll_gpu", "pll_periph"};
 666 NM_CLK(gpu_memory_clk,
 667     CLK_GPU_MEMORY,                             /* id */
 668     "gpu-memory", gpu_memory_parents,           /* name, parents */
 669     0x1a4,                                      /* offset */
 670     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 671     0, 3, 0, 0,                                 /* m factor */
 672     24, 1,                                      /* mux */
 673     31,                                         /* gate */
 674     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);
 675
 676 static const char *gpu_hyd_parents[] = {"pll_gpu"};
 677 NM_CLK(gpu_hyd_clk,
 678     CLK_GPU_HYD,                                /* id */
 679     "gpu-hyd", gpu_hyd_parents,                 /* name, parents */
 680     0x1a0,                                      /* offset */
 681     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 682     0, 3, 0, 0,                                 /* m factor */
 683     0, 0,                                       /* mux */
 684     31,                                         /* gate */
 685     AW_CLK_HAS_GATE);
 686
 687 static struct aw_ccung_clk a83t_clks[] = {
 688         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_audio_clk},
 689         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_video0_clk},
 690         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ve_clk},
 691         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_clk},
 692         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph_clk},
 693         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_gpu_clk},
 694         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_hsic_clk},
 695         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_de_clk},
 696         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_video1_clk},
 697         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_c0cpux_clk},
 698         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_c1cpux_clk},
 699         { .type = AW_CLK_NM, .clk.nm = &apb2_clk},
 700         { .type = AW_CLK_NM, .clk.nm = &nand_clk},
 701         { .type = AW_CLK_NM, .clk.nm = &mmc0_clk},
 702         { .type = AW_CLK_NM, .clk.nm = &mmc1_clk},
 703         { .type = AW_CLK_NM, .clk.nm = &mmc2_clk},
 704         { .type = AW_CLK_NM, .clk.nm = &ss_clk},
 705         { .type = AW_CLK_NM, .clk.nm = &spi0_clk},
 706         { .type = AW_CLK_NM, .clk.nm = &spi1_clk},
 707         { .type = AW_CLK_NM, .clk.nm = &i2s0_clk},
 708         { .type = AW_CLK_NM, .clk.nm = &i2s1_clk},
 709         { .type = AW_CLK_NM, .clk.nm = &i2s2_clk},
 710         { .type = AW_CLK_NM, .clk.nm = &tdm_clk},
 711         { .type = AW_CLK_NM, .clk.nm = &spdif_clk},
 712         { .type = AW_CLK_NM, .clk.nm = &dram_clk},
 713         { .type = AW_CLK_NM, .clk.nm = &tcon1_clk},
 714         { .type = AW_CLK_NM, .clk.nm = &csi_mclk_clk},
 715         { .type = AW_CLK_NM, .clk.nm = &csi_sclk_clk},
 716         { .type = AW_CLK_NM, .clk.nm = &ve_clk},
 717         { .type = AW_CLK_NM, .clk.nm = &hdmi_clk},
 718         { .type = AW_CLK_NM, .clk.nm = &mbus_clk},
 719         { .type = AW_CLK_NM, .clk.nm = &mipi_dsi0_clk},
 720         { .type = AW_CLK_NM, .clk.nm = &mipi_dsi1_clk},
 721         { .type = AW_CLK_NM, .clk.nm = &gpu_core_clk},
 722         { .type = AW_CLK_NM, .clk.nm = &gpu_memory_clk},
 723         { .type = AW_CLK_NM, .clk.nm = &gpu_hyd_clk},
 724         { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb1_clk},
 725         { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb2_clk},
 726         { .type = AW_CLK_MUX, .clk.mux = &c0cpux_clk},
 727         { .type = AW_CLK_MUX, .clk.mux = &c1cpux_clk},
 728         { .type = AW_CLK_MUX, .clk.mux = &cci400_clk},
 729         { .type = AW_CLK_MUX, .clk.mux = &tcon0_clk},
 730         { .type = AW_CLK_DIV, .clk.div = &axi0_clk},
 731         { .type = AW_CLK_DIV, .clk.div = &axi1_clk},
 732         { .type = AW_CLK_DIV, .clk.div = &apb1_clk},
 733         { .type = AW_CLK_FIXED, .clk.fixed = &osc12m_clk},
 734 };
 735
 736 static struct aw_clk_init a83t_init_clks[] = {
 737         {"ahb1", "pll_periph", 0, false},
 738         {"ahb2", "ahb1", 0, false},
 739         {"dram", "pll_ddr", 0, false},
 740 };
 741
 742 static int
 743 ccu_a83t_probe(device_t dev)
 744 {
 745
 746         if (!ofw_bus_status_okay(dev))
 747                 return (ENXIO);
 748
 749         if (!ofw_bus_is_compatible(dev, "allwinner,sun8i-a83t-ccu"))
 750                 return (ENXIO);
 751
 752         device_set_desc(dev, "Allwinner A83T Clock Control Unit NG");
 753         return (BUS_PROBE_DEFAULT);
 754 }
 755
 756 static int
 757 ccu_a83t_attach(device_t dev)
 758 {
 759         struct aw_ccung_softc *sc;
 760
 761         sc = device_get_softc(dev);
 762
 763         sc->resets = a83t_ccu_resets;
 764         sc->nresets = nitems(a83t_ccu_resets);
 765         sc->gates = a83t_ccu_gates;
 766         sc->ngates = nitems(a83t_ccu_gates);
 767         sc->clks = a83t_clks;
 768         sc->nclks = nitems(a83t_clks);
 769         sc->clk_init = a83t_init_clks;
 770         sc->n_clk_init = nitems(a83t_init_clks);
 771
 772         return (aw_ccung_attach(dev));
 773 }
 774
 775 static device_method_t ccu_a83tng_methods[] = {
 776         /* Device interface */
 777         DEVMETHOD(device_probe,         ccu_a83t_probe),
 778         DEVMETHOD(device_attach,        ccu_a83t_attach),
 779
 780         DEVMETHOD_END
 781 };
 782
 783 static devclass_t ccu_a83tng_devclass;
 784
 785 DEFINE_CLASS_1(ccu_a83tng, ccu_a83tng_driver, ccu_a83tng_methods,
 786   sizeof(struct aw_ccung_softc), aw_ccung_driver);
 787
 788 EARLY_DRIVER_MODULE(ccu_a83tng, simplebus, ccu_a83tng_driver,
 789     ccu_a83tng_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);