sys/arm/allwinner/clkng/ccu_h3.c

   1 /*-
   2  * Copyright (c) 2017 Emmanuel Vadot <manu@freebsd.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  15  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  16  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  17  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  18  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  19  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  20  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  21  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  22  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  * $FreeBSD$
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __FBSDID("$FreeBSD$");
  31
  32 #include <sys/param.h>
  33 #include <sys/systm.h>
  34 #include <sys/bus.h>
  35
  36 #include <dev/extres/clk/clk_div.h>
  37 #include <dev/extres/clk/clk_fixed.h>
  38 #include <dev/extres/clk/clk_mux.h>
  39
  40 #include <arm/allwinner/clkng/aw_ccung.h>
  41 #include <arm/allwinner/clkng/aw_clk.h>
  42 #include <arm/allwinner/clkng/aw_clk_nm.h>
  43 #include <arm/allwinner/clkng/aw_clk_nkmp.h>
  44 #include <arm/allwinner/clkng/aw_clk_prediv_mux.h>
  45
  46 #include "ccu_h3.h"
  47
  48 static struct aw_ccung_reset h3_ccu_resets[] = {
  49         CCU_RESET(H3_RST_USB_PHY0, 0xcc, 0)
  50         CCU_RESET(H3_RST_USB_PHY1, 0xcc, 1)
  51         CCU_RESET(H3_RST_USB_PHY2, 0xcc, 2)
  52         CCU_RESET(H3_RST_USB_PHY3, 0xcc, 3)
  53
  54         CCU_RESET(H3_RST_MBUS, 0xfc, 31)
  55
  56         CCU_RESET(H3_RST_BUS_CE, 0x2c0, 5)
  57         CCU_RESET(H3_RST_BUS_DMA, 0x2c0, 6)
  58         CCU_RESET(H3_RST_BUS_MMC0, 0x2c0, 8)
  59         CCU_RESET(H3_RST_BUS_MMC1, 0x2c0, 9)
  60         CCU_RESET(H3_RST_BUS_MMC2, 0x2c0, 10)
  61         CCU_RESET(H3_RST_BUS_NAND, 0x2c0, 13)
  62         CCU_RESET(H3_RST_BUS_DRAM, 0x2c0, 14)
  63         CCU_RESET(H3_RST_BUS_EMAC, 0x2c0, 17)
  64         CCU_RESET(H3_RST_BUS_TS, 0x2c0, 18)
  65         CCU_RESET(H3_RST_BUS_HSTIMER, 0x2c0, 19)
  66         CCU_RESET(H3_RST_BUS_SPI0, 0x2c0, 20)
  67         CCU_RESET(H3_RST_BUS_SPI1, 0x2c0, 21)
  68         CCU_RESET(H3_RST_BUS_OTG, 0x2c0, 23)
  69         CCU_RESET(H3_RST_BUS_EHCI0, 0x2c0, 24)
  70         CCU_RESET(H3_RST_BUS_EHCI1, 0x2c0, 25)
  71         CCU_RESET(H3_RST_BUS_EHCI2, 0x2c0, 26)
  72         CCU_RESET(H3_RST_BUS_EHCI3, 0x2c0, 27)
  73         CCU_RESET(H3_RST_BUS_OHCI0, 0x2c0, 28)
  74         CCU_RESET(H3_RST_BUS_OHCI1, 0x2c0, 29)
  75         CCU_RESET(H3_RST_BUS_OHCI2, 0x2c0, 30)
  76         CCU_RESET(H3_RST_BUS_OHCI3, 0x2c0, 31)
  77
  78         CCU_RESET(H3_RST_BUS_VE, 0x2c4, 0)
  79         CCU_RESET(H3_RST_BUS_TCON0, 0x2c4, 3)
  80         CCU_RESET(H3_RST_BUS_TCON1, 0x2c4, 4)
  81         CCU_RESET(H3_RST_BUS_DEINTERLACE, 0x2c4, 5)
  82         CCU_RESET(H3_RST_BUS_CSI, 0x2c4, 8)
  83         CCU_RESET(H3_RST_BUS_TVE, 0x2c4, 9)
  84         CCU_RESET(H3_RST_BUS_HDMI0, 0x2c4, 10)
  85         CCU_RESET(H3_RST_BUS_HDMI1, 0x2c4, 11)
  86         CCU_RESET(H3_RST_BUS_DE, 0x2c4, 12)
  87         CCU_RESET(H3_RST_BUS_GPU, 0x2c4, 20)
  88         CCU_RESET(H3_RST_BUS_MSGBOX, 0x2c4, 21)
  89         CCU_RESET(H3_RST_BUS_SPINLOCK, 0x2c4, 22)
  90         CCU_RESET(H3_RST_BUS_DBG, 0x2c4, 31)
  91
  92         CCU_RESET(H3_RST_BUS_EPHY, 0x2c8, 2)
  93
  94         CCU_RESET(H3_RST_BUS_CODEC, 0x2d0, 0)
  95         CCU_RESET(H3_RST_BUS_SPDIF, 0x2d0, 1)
  96         CCU_RESET(H3_RST_BUS_THS, 0x2d0, 8)
  97         CCU_RESET(H3_RST_BUS_I2S0, 0x2d0, 12)
  98         CCU_RESET(H3_RST_BUS_I2S1, 0x2d0, 13)
  99         CCU_RESET(H3_RST_BUS_I2S2, 0x2d0, 14)
 100
 101         CCU_RESET(H3_RST_BUS_I2C0, 0x2d8, 0)
 102         CCU_RESET(H3_RST_BUS_I2C1, 0x2d8, 1)
 103         CCU_RESET(H3_RST_BUS_I2C2, 0x2d8, 2)
 104         CCU_RESET(H3_RST_BUS_UART0, 0x2d8, 16)
 105         CCU_RESET(H3_RST_BUS_UART1, 0x2d8, 17)
 106         CCU_RESET(H3_RST_BUS_UART2, 0x2d8, 18)
 107         CCU_RESET(H3_RST_BUS_UART3, 0x2d8, 19)
 108         CCU_RESET(H3_RST_BUS_SCR, 0x2d8, 20)
 109 };
 110
 111 static struct aw_ccung_gate h3_ccu_gates[] = {
 112         CCU_GATE(H3_CLK_BUS_CE, "bus-ce", "ahb1", 0x60, 5)
 113         CCU_GATE(H3_CLK_BUS_DMA, "bus-dma", "ahb1", 0x60, 6)
 114         CCU_GATE(H3_CLK_BUS_MMC0, "bus-mmc0", "ahb1", 0x60, 8)
 115         CCU_GATE(H3_CLK_BUS_MMC1, "bus-mmc1", "ahb1", 0x60, 9)
 116         CCU_GATE(H3_CLK_BUS_MMC2, "bus-mmc2", "ahb1", 0x60, 10)
 117         CCU_GATE(H3_CLK_BUS_NAND, "bus-nand", "ahb1", 0x60, 13)
 118         CCU_GATE(H3_CLK_BUS_DRAM, "bus-dram", "ahb1", 0x60, 14)
 119         CCU_GATE(H3_CLK_BUS_EMAC, "bus-emac", "ahb2", 0x60, 17)
 120         CCU_GATE(H3_CLK_BUS_TS, "bus-ts", "ahb1", 0x60, 18)
 121         CCU_GATE(H3_CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 0x60, 19)
 122         CCU_GATE(H3_CLK_BUS_SPI0, "bus-spi0", "ahb1", 0x60, 20)
 123         CCU_GATE(H3_CLK_BUS_SPI1, "bus-spi1", "ahb1", 0x60, 21)
 124         CCU_GATE(H3_CLK_BUS_OTG, "bus-otg", "ahb1", 0x60, 23)
 125         CCU_GATE(H3_CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 0x60, 24)
 126         CCU_GATE(H3_CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 0x60, 25)
 127         CCU_GATE(H3_CLK_BUS_EHCI2, "bus-ehci2", "ahb2", 0x60, 26)
 128         CCU_GATE(H3_CLK_BUS_EHCI3, "bus-ehci3", "ahb2", 0x60, 27)
 129         CCU_GATE(H3_CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 0x60, 28)
 130         CCU_GATE(H3_CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 0x60, 29)
 131         CCU_GATE(H3_CLK_BUS_OHCI2, "bus-ohci2", "ahb2", 0x60, 30)
 132         CCU_GATE(H3_CLK_BUS_OHCI3, "bus-ohci3", "ahb2", 0x60, 31)
 133
 134         CCU_GATE(H3_CLK_BUS_VE, "bus-ve", "ahb1", 0x64, 0)
 135         CCU_GATE(H3_CLK_BUS_TCON0, "bus-tcon0", "ahb1", 0x64, 3)
 136         CCU_GATE(H3_CLK_BUS_TCON1, "bus-tcon1", "ahb1", 0x64, 4)
 137         CCU_GATE(H3_CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 0x64, 5)
 138         CCU_GATE(H3_CLK_BUS_CSI, "bus-csi", "ahb1", 0x64, 8)
 139         CCU_GATE(H3_CLK_BUS_TVE, "bus-tve", "ahb1", 0x64, 9)
 140         CCU_GATE(H3_CLK_BUS_HDMI, "bus-hdmi", "ahb1", 0x64, 11)
 141         CCU_GATE(H3_CLK_BUS_DE, "bus-de", "ahb1", 0x64, 12)
 142         CCU_GATE(H3_CLK_BUS_GPU, "bus-gpu", "ahb1", 0x64, 20)
 143         CCU_GATE(H3_CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 0x64, 21)
 144         CCU_GATE(H3_CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 0x64, 22)
 145
 146         CCU_GATE(H3_CLK_BUS_CODEC, "bus-codec", "apb1", 0x68, 0)
 147         CCU_GATE(H3_CLK_BUS_SPDIF, "bus-spdif", "apb1", 0x68, 1)
 148         CCU_GATE(H3_CLK_BUS_PIO, "bus-pio", "apb1", 0x68, 5)
 149         CCU_GATE(H3_CLK_BUS_THS, "bus-ths", "apb1", 0x68, 8)
 150         CCU_GATE(H3_CLK_BUS_I2S0, "bus-i2s0", "apb1", 0x68, 12)
 151         CCU_GATE(H3_CLK_BUS_I2S1, "bus-i2s1", "apb1", 0x68, 13)
 152         CCU_GATE(H3_CLK_BUS_I2S2, "bus-i2s2", "apb1", 0x68, 14)
 153
 154         CCU_GATE(H3_CLK_BUS_I2C0, "bus-i2c0", "apb2", 0x6c, 0)
 155         CCU_GATE(H3_CLK_BUS_I2C1, "bus-i2c1", "apb2", 0x6c, 1)
 156         CCU_GATE(H3_CLK_BUS_I2C2, "bus-i2c2", "apb2", 0x6c, 2)
 157         CCU_GATE(H3_CLK_BUS_UART0, "bus-uart0", "apb2", 0x6c, 16)
 158         CCU_GATE(H3_CLK_BUS_UART1, "bus-uart1", "apb2", 0x6c, 17)
 159         CCU_GATE(H3_CLK_BUS_UART2, "bus-uart2", "apb2", 0x6c, 18)
 160         CCU_GATE(H3_CLK_BUS_UART3, "bus-uart3", "apb2", 0x6c, 19)
 161         CCU_GATE(H3_CLK_BUS_SCR, "bus-scr", "apb2", 0x6c, 20)
 162
 163         CCU_GATE(H3_CLK_BUS_EPHY, "bus-ephy", "ahb1", 0x70, 0)
 164         CCU_GATE(H3_CLK_BUS_DBG, "bus-dbg", "ahb1", 0x70, 7)
 165
 166         CCU_GATE(H3_CLK_USBPHY0, "usb-phy0", "osc24M", 0xcc, 8)
 167         CCU_GATE(H3_CLK_USBPHY1, "usb-phy1", "osc24M", 0xcc, 9)
 168         CCU_GATE(H3_CLK_USBPHY2, "usb-phy2", "osc24M", 0xcc, 10)
 169         CCU_GATE(H3_CLK_USBPHY3, "usb-phy3", "osc24M", 0xcc, 11)
 170         CCU_GATE(H3_CLK_USBOHCI0, "usb-ohci0", "osc24M", 0xcc, 16)
 171         CCU_GATE(H3_CLK_USBOHCI1, "usb-ohci1", "osc24M", 0xcc, 17)
 172         CCU_GATE(H3_CLK_USBOHCI2, "usb-ohci2", "osc24M", 0xcc, 18)
 173         CCU_GATE(H3_CLK_USBOHCI3, "usb-ohci3", "osc24M", 0xcc, 19)
 174
 175         CCU_GATE(H3_CLK_THS, "ths", "thsdiv", 0x74, 31)
 176         CCU_GATE(H3_CLK_I2S0, "i2s0", "i2s0mux", 0xB0, 31)
 177         CCU_GATE(H3_CLK_I2S1, "i2s1", "i2s1mux", 0xB4, 31)
 178         CCU_GATE(H3_CLK_I2S2, "i2s2", "i2s2mux", 0xB8, 31)
 179
 180         CCU_GATE(H3_CLK_DRAM_VE, "dram-ve", "dram", 0x100, 0)
 181         CCU_GATE(H3_CLK_DRAM_CSI, "dram-csi", "dram", 0x100, 1)
 182         CCU_GATE(H3_CLK_DRAM_DEINTERLACE, "dram-deinterlace", "dram", 0x100, 2)
 183         CCU_GATE(H3_CLK_DRAM_TS, "dram-ts", "dram", 0x100, 3)
 184
 185         CCU_GATE(H3_CLK_AC_DIG, "ac-dig", "pll_audio", 0x140, 31)
 186
 187         CCU_GATE(H3_CLK_AVS, "avs", "osc24M", 0x144, 31)
 188
 189         CCU_GATE(H3_CLK_CSI_MISC, "csi-misc", "osc24M", 0x130, 31)
 190
 191         CCU_GATE(H3_CLK_HDMI_DDC, "hdmi-ddc", "osc24M", 0x154, 31)
 192 };
 193
 194 static const char *pll_cpux_parents[] = {"osc24M"};
 195 NKMP_CLK(pll_cpux_clk,
 196     H3_CLK_PLL_CPUX,                    /* id */
 197     "pll_cpux", pll_cpux_parents,               /* name, parents */
 198     0x00,                                       /* offset */
 199     8, 5, 0, 0,                                 /* n factor */
 200     4, 2, 0, 0,                                 /* k factor */
 201     0, 2, 0, 0,                                 /* m factor */
 202     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* p factor */
 203     31,                                         /* gate */
 204     28, 1000,                                   /* lock */
 205     AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK | AW_CLK_SCALE_CHANGE);           /* flags */
 206
 207 static const char *pll_audio_parents[] = {"osc24M"};
 208 NKMP_CLK(pll_audio_clk,
 209     H3_CLK_PLL_AUDIO,                   /* id */
 210     "pll_audio", pll_audio_parents,             /* name, parents */
 211     0x08,                                       /* offset */
 212     8, 7, 0, 0,                                 /* n factor */
 213     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* k factor (fake) */
 214     0, 5, 0, 0,                                 /* m factor */
 215     16, 4, 0, 0,                                /* p factor */
 216     31,                                         /* gate */
 217     28, 1000,                                   /* lock */
 218     AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK);         /* flags */
 219
 220 static const char *pll_audio_mult_parents[] = {"pll_audio"};
 221 FIXED_CLK(pll_audio_2x_clk,
 222     H3_CLK_PLL_AUDIO_2X,                /* id */
 223     "pll_audio-2x",                     /* name */
 224     pll_audio_mult_parents,             /* parent */
 225     0,                                  /* freq */
 226     2,                                  /* mult */
 227     1,                                  /* div */
 228     0);                                 /* flags */
 229 FIXED_CLK(pll_audio_4x_clk,
 230     H3_CLK_PLL_AUDIO_4X,                /* id */
 231     "pll_audio-4x",                     /* name */
 232     pll_audio_mult_parents,             /* parent */
 233     0,                                  /* freq */
 234     4,                                  /* mult */
 235     1,                                  /* div */
 236     0);                                 /* flags */
 237 FIXED_CLK(pll_audio_8x_clk,
 238     H3_CLK_PLL_AUDIO_8X,                /* id */
 239     "pll_audio-8x",                     /* name */
 240     pll_audio_mult_parents,             /* parent */
 241     0,                                  /* freq */
 242     8,                                  /* mult */
 243     1,                                  /* div */
 244     0);                                 /* flags */
 245
 246 static const char *pll_video_parents[] = {"osc24M"};
 247 NM_CLK_WITH_FRAC(pll_video_clk,
 248     H3_CLK_PLL_VIDEO,                           /* id */
 249     "pll_video", pll_video_parents,             /* name, parents */
 250     0x10,                                       /* offset */
 251     8, 7, 0, 0,                                 /* n factor */
 252     0, 4, 0, 0,                                 /* m factor */
 253     31, 28, 1000,                               /* gate, lock, lock retries */
 254     AW_CLK_HAS_LOCK,                            /* flags */
 255     270000000, 297000000,                       /* freq0, freq1 */
 256     24, 25);                                    /* mode sel, freq sel */
 257
 258 static const char *pll_ve_parents[] = {"osc24M"};
 259 NM_CLK_WITH_FRAC(pll_ve_clk,
 260     H3_CLK_PLL_VE,                              /* id */
 261     "pll_ve", pll_ve_parents,                   /* name, parents */
 262     0x18,                                       /* offset */
 263     8, 7, 0, 0,                                 /* n factor */
 264     0, 4, 0, 0,                                 /* m factor */
 265     31, 28, 1000,                               /* gate, lock, lock retries */
 266     AW_CLK_HAS_LOCK,                            /* flags */
 267     270000000, 297000000,                       /* freq0, freq1 */
 268     24, 25);                                    /* mode sel, freq sel */
 269
 270 static const char *pll_ddr_parents[] = {"osc24M"};
 271 NKMP_CLK_WITH_UPDATE(pll_ddr_clk,
 272     H3_CLK_PLL_DDR,                             /* id */
 273     "pll_ddr", pll_ddr_parents,                 /* name, parents */
 274     0x20,                                       /* offset */
 275     8, 5, 0, 0,                                 /* n factor */
 276     4, 2, 0, 0,                                 /* k factor */
 277     0, 2, 0, 0,                                 /* m factor */
 278     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* p factor (fake) */
 279     31,                                         /* gate */
 280     28, 1000,                                   /* lock */
 281     20,                                         /* update */
 282     AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK);         /* flags */
 283
 284 static const char *pll_periph0_parents[] = {"osc24M"};
 285 static const char *pll_periph0_2x_parents[] = {"pll_periph0"};
 286 NKMP_CLK(pll_periph0_clk,
 287     H3_CLK_PLL_PERIPH0,         /* id */
 288     "pll_periph0", pll_periph0_parents,         /* name, parents */
 289     0x28,                                       /* offset */
 290     8, 5, 0, 0,                                 /* n factor */
 291     4, 2, 0, 0,                                 /* k factor */
 292     0, 0, 2, AW_CLK_FACTOR_FIXED,               /* m factor (fake) */
 293     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* p factor (fake) */
 294     31,                                         /* gate */
 295     28, 1000,                                   /* lock */
 296     AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK);         /* flags */
 297 FIXED_CLK(pll_periph0_2x_clk,
 298     H3_CLK_PLL_PERIPH0_2X,      /* id */
 299     "pll_periph0-2x",                   /* name */
 300     pll_periph0_2x_parents,             /* parent */
 301     0,                                  /* freq */
 302     2,                                  /* mult */
 303     1,                                  /* div */
 304     0);                                 /* flags */
 305
 306 static const char *pll_gpu_parents[] = {"osc24M"};
 307 NM_CLK_WITH_FRAC(pll_gpu_clk,
 308     H3_CLK_PLL_GPU,                             /* id */
 309     "pll_gpu", pll_gpu_parents,                 /* name, parents */
 310     0x38,                                       /* offset */
 311     8, 7, 0, 0,                                 /* n factor */
 312     0, 4, 0, 0,                                 /* m factor */
 313     31, 28, 1000,                               /* gate, lock, lock retries */
 314     AW_CLK_HAS_LOCK,                            /* flags */
 315     270000000, 297000000,                       /* freq0, freq1 */
 316     24, 25);                                    /* mode sel, freq sel */
 317
 318 static const char *pll_periph1_parents[] = {"osc24M"};
 319 NKMP_CLK(pll_periph1_clk,
 320     H3_CLK_PLL_PERIPH1,                         /* id */
 321     "pll_periph1", pll_periph1_parents,         /* name, parents */
 322     0x44,                                       /* offset */
 323     8, 5, 0, 0,                                 /* n factor */
 324     4, 2, 0, 0,                                 /* k factor */
 325     0, 0, 2, AW_CLK_FACTOR_FIXED,               /* m factor (fake) */
 326     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* p factor (fake) */
 327     31,                                         /* gate */
 328     28, 1000,                                   /* lock */
 329     AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK);         /* flags */
 330
 331 static const char *pll_de_parents[] = {"osc24M"};
 332 NM_CLK_WITH_FRAC(pll_de_clk,
 333     H3_CLK_PLL_DE,                              /* id */
 334     "pll_de", pll_de_parents,                   /* name, parents */
 335     0x48,                                       /* offset */
 336     8, 7, 0, 0,                                 /* n factor */
 337     0, 4, 0, 0,                                 /* m factor */
 338     31, 28, 1000,                               /* gate, lock, lock retries */
 339     AW_CLK_HAS_LOCK,                            /* flags */
 340     270000000, 297000000,                       /* freq0, freq1 */
 341     24, 25);                                    /* mode sel, freq sel */
 342
 343 static const char *cpux_parents[] = {"osc32k", "osc24M", "pll_cpux", "pll_cpux"};
 344 MUX_CLK(cpux_clk,
 345     H3_CLK_CPUX,                /* id */
 346     "cpux", cpux_parents,       /* name, parents */
 347     0x50, 16, 2);               /* offset, shift, width */
 348
 349 static const char *axi_parents[] = {"cpux"};
 350 DIV_CLK(axi_clk,
 351     H3_CLK_AXI,         /* id */
 352     "axi", axi_parents,         /* name, parents */
 353     0x50,                       /* offset */
 354     0, 2,                       /* shift, width */
 355     0, NULL);                   /* flags, div table */
 356
 357 static const char *ahb1_parents[] = {"osc32k", "osc24M", "axi", "pll_periph0"};
 358 PREDIV_CLK(ahb1_clk, H3_CLK_AHB1,                               /* id */
 359     "ahb1", ahb1_parents,                                       /* name, parents */
 360     0x54,                                                       /* offset */
 361     12, 2,                                                      /* mux */
 362     4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,                        /* div */
 363     6, 2, 0, AW_CLK_FACTOR_HAS_COND,                            /* prediv */
 364     12, 2, 3);                                                  /* prediv condition */
 365
 366 static const char *apb1_parents[] = {"ahb1"};
 367 static struct clk_div_table apb1_div_table[] = {
 368         { .value = 0, .divider = 2, },
 369         { .value = 1, .divider = 2, },
 370         { .value = 2, .divider = 4, },
 371         { .value = 3, .divider = 8, },
 372         { },
 373 };
 374 DIV_CLK(apb1_clk,
 375     H3_CLK_APB1,                /* id */
 376     "apb1", apb1_parents,       /* name, parents */
 377     0x54,                       /* offset */
 378     8, 2,                       /* shift, width */
 379     CLK_DIV_WITH_TABLE,         /* flags */
 380     apb1_div_table);            /* div table */
 381
 382 static const char *apb2_parents[] = {"osc32k", "osc24M", "pll_periph0", "pll_periph0"};
 383 NM_CLK(apb2_clk,
 384     H3_CLK_APB2,                                /* id */
 385     "apb2", apb2_parents,                       /* name, parents */
 386     0x58,                                       /* offset */
 387     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 388     0, 5, 0, 0,                                 /* m factor */
 389     24, 2,                                      /* mux */
 390     0,                                          /* gate */
 391     AW_CLK_HAS_MUX);
 392
 393 static const char *ahb2_parents[] = {"ahb1", "pll_periph0"};
 394 PREDIV_CLK(ahb2_clk, H3_CLK_AHB2,                               /* id */
 395     "ahb2", ahb2_parents,                                       /* name, parents */
 396     0x5c,                                                       /* offset */
 397     0, 2,                                                       /* mux */
 398     0, 0, 1, AW_CLK_FACTOR_FIXED,                               /* div */
 399     0, 0, 2, AW_CLK_FACTOR_HAS_COND | AW_CLK_FACTOR_FIXED,      /* prediv */
 400     0, 2, 1);                                                   /* prediv condition */
 401
 402 static const char *ths_parents[] = {"osc24M"};
 403 static struct clk_div_table ths_div_table[] = {
 404         { .value = 0, .divider = 1, },
 405         { .value = 1, .divider = 2, },
 406         { .value = 2, .divider = 4, },
 407         { .value = 3, .divider = 6, },
 408         { },
 409 };
 410 DIV_CLK(thsdiv_clk,
 411     0,                  /* id */
 412     "thsdiv", ths_parents,      /* name, parents */
 413     0x74,                       /* offset */
 414     0, 2,                       /* shift, width */
 415     CLK_DIV_WITH_TABLE,         /* flags */
 416     ths_div_table);             /* div table */
 417
 418 static const char *mod_parents[] = {"osc24M", "pll_periph0", "pll_periph1"};
 419 NM_CLK(nand_clk,
 420     H3_CLK_NAND, "nand", mod_parents,           /* id, name, parents */
 421     0x80,                                       /* offset */
 422     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 423     0, 4, 0, 0,                                 /* m factor */
 424     24, 2,                                      /* mux */
 425     31,                                         /* gate */
 426     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX);          /* flags */
 427
 428 NM_CLK(mmc0_clk,
 429     H3_CLK_MMC0, "mmc0", mod_parents,           /* id, name, parents */
 430     0x88,                                       /* offset */
 431     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 432     0, 4, 0, 0,                                 /* m factor */
 433     24, 2,                                      /* mux */
 434     31,                                         /* gate */
 435     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
 436     AW_CLK_REPARENT);                           /* flags */
 437
 438 NM_CLK(mmc1_clk,
 439     H3_CLK_MMC1, "mmc1", mod_parents,           /* id, name, parents */
 440     0x8c,                                       /* offset */
 441     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 442     0, 4, 0, 0,                                 /* m factor */
 443     24, 2,                                      /* mux */
 444     31,                                         /* gate */
 445     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
 446     AW_CLK_REPARENT);                           /* flags */
 447
 448 NM_CLK(mmc2_clk,
 449     H3_CLK_MMC2, "mmc2", mod_parents,           /* id, name, parents */
 450     0x90,                                       /* offset */
 451     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 452     0, 4, 0, 0,                                 /* m factor */
 453     24, 2,                                      /* mux */
 454     31,                                         /* gate */
 455     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
 456     AW_CLK_REPARENT);                           /* flags */
 457
 458 static const char *ts_parents[] = {"osc24M", "pll_periph0"};
 459 NM_CLK(ts_clk,
 460     H3_CLK_TS, "ts", ts_parents,                /* id, name, parents */
 461     0x98,                                       /* offset */
 462     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 463     0, 4, 0, 0,                                 /* m factor */
 464     24, 2,                                      /* mux */
 465     31,                                         /* gate */
 466     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX);          /* flags */
 467
 468 NM_CLK(ce_clk,
 469     H3_CLK_CE, "ce", mod_parents,               /* id, name, parents */
 470     0x9C,                                       /* offset */
 471     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 472     0, 4, 0, 0,                                 /* m factor */
 473     24, 2,                                      /* mux */
 474     31,                                         /* gate */
 475     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX);          /* flags */
 476
 477 NM_CLK(spi0_clk,
 478     H3_CLK_SPI0, "spi0", mod_parents,   /* id, name, parents */
 479     0xA0,                                       /* offset */
 480     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 481     0, 4, 0, 0,                                 /* m factor */
 482     24, 2,                                      /* mux */
 483     31,                                         /* gate */
 484     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
 485     AW_CLK_REPARENT);                           /* flags */
 486
 487 NM_CLK(spi1_clk,
 488     H3_CLK_SPI1, "spi1", mod_parents,   /* id, name, parents */
 489     0xA4,                                       /* offset */
 490     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 491     0, 4, 0, 0,                                 /* m factor */
 492     24, 2,                                      /* mux */
 493     31,                                         /* gate */
 494     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
 495     AW_CLK_REPARENT);                           /* flags */
 496
 497 static const char *i2s_parents[] = {"pll_audio-8x", "pll_audio-4x", "pll_audio-2x", "pll_audio"};
 498 MUX_CLK(i2s0mux_clk,
 499     0, "i2s0mux", i2s_parents,                  /* id, name, parents */
 500     0xb0, 16, 2);                               /* offset, mux shift, mux width */
 501 MUX_CLK(i2s1mux_clk,
 502     0, "i2s1mux", i2s_parents,                  /* id, name, parents */
 503     0xb4, 16, 2);                               /* offset, mux shift, mux width */
 504 MUX_CLK(i2s2mux_clk,
 505     0, "i2s2mux", i2s_parents,                  /* id, name, parents */
 506     0xb8, 16, 2);                               /* offset, mux shift, mux width */
 507
 508 static const char *spdif_parents[] = {"pll_audio"};
 509 NM_CLK(spdif_clk,
 510     H3_CLK_SPDIF, "spdif", spdif_parents,       /* id, name, parents */
 511     0xC0,                                       /* offset */
 512     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake); */
 513     0, 4, 0, 0,                                 /* m factor */
 514     0, 0,                                       /* mux */
 515     31,                                         /* gate */
 516     AW_CLK_HAS_GATE);                           /* flags */
 517
 518 static const char *dram_parents[] = {"pll_ddr", "pll_periph0-2x"};
 519 NM_CLK(dram_clk,
 520     H3_CLK_DRAM, "dram", dram_parents,          /* id, name, parents */
 521     0xF4,                                       /* offset */
 522     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 523     0, 4, 0, 0,                                 /* m factor */
 524     20, 2,                                      /* mux */
 525     0,                                          /* gate */
 526     AW_CLK_HAS_MUX);                            /* flags */
 527
 528 static const char *de_parents[] = {"pll_periph0-2x", "pll_de"};
 529 NM_CLK(de_clk,
 530     H3_CLK_DE, "de", de_parents,                /* id, name, parents */
 531     0x104,                                      /* offset */
 532     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 533     0, 4, 0, 0,                                 /* m factor */
 534     24, 2,                                      /* mux */
 535     31,                                         /* gate */
 536     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 537
 538 static const char *tcon0_parents[] = {"pll_video"};
 539 NM_CLK(tcon0_clk,
 540     H3_CLK_TCON0, "tcon0", tcon0_parents,       /* id, name, parents */
 541     0x118,                                      /* offset */
 542     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 543     0, 4, 0, 0,                                 /* m factor */
 544     24, 2,                                      /* mux */
 545     31,                                         /* gate */
 546     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 547
 548 static const char *tve_parents[] = {"pll_de", "pll_periph1"};
 549 NM_CLK(tve_clk,
 550     H3_CLK_TVE, "tve", tve_parents,     /* id, name, parents */
 551     0x120,                                      /* offset */
 552     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 553     0, 4, 0, 0,                                 /* m factor */
 554     24, 2,                                      /* mux */
 555     31,                                         /* gate */
 556     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 557
 558 static const char *deinterlace_parents[] = {"pll_periph0", "pll_periph1"};
 559 NM_CLK(deinterlace_clk,
 560     H3_CLK_DEINTERLACE, "deinterlace", deinterlace_parents,     /* id, name, parents */
 561     0x124,                                      /* offset */
 562     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 563     0, 4, 0, 0,                                 /* m factor */
 564     24, 2,                                      /* mux */
 565     31,                                         /* gate */
 566     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 567
 568 static const char *csi_sclk_parents[] = {"pll_periph0", "pll_periph1"};
 569 NM_CLK(csi_sclk_clk,
 570     H3_CLK_CSI_SCLK, "csi-sclk", csi_sclk_parents,      /* id, name, parents */
 571     0x134,                                      /* offset */
 572     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 573     16, 4, 0, 0,                                /* m factor */
 574     24, 2,                                      /* mux */
 575     31,                                         /* gate */
 576     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 577
 578 static const char *csi_mclk_parents[] = {"osc24M", "pll_video", "pll_periph1"};
 579 NM_CLK(csi_mclk_clk,
 580     H3_CLK_CSI_MCLK, "csi-mclk", csi_mclk_parents,      /* id, name, parents */
 581     0x134,                                      /* offset */
 582     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 583     0, 4, 0, 0,                                 /* m factor */
 584     8, 2,                                       /* mux */
 585     15,                                         /* gate */
 586     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 587
 588 static const char *ve_parents[] = {"pll_ve"};
 589 NM_CLK(ve_clk,
 590     H3_CLK_VE, "ve", ve_parents,        /* id, name, parents */
 591     0x13C,                                      /* offset */
 592     16, 3, 0, 0,                                /* n factor */
 593     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* m factor (fake) */
 594     0, 0,                                       /* mux */
 595     31,                                         /* gate */
 596     AW_CLK_HAS_GATE);                           /* flags */
 597
 598 static const char *hdmi_parents[] = {"pll_video"};
 599 NM_CLK(hdmi_clk,
 600     H3_CLK_HDMI, "hdmi", hdmi_parents,          /* id, name, parents */
 601     0x150,                                      /* offset */
 602     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 603     0, 4, 0, 0,                                 /* m factor */
 604     24, 2,                                      /* mux */
 605     31,                                         /* gate */
 606     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 607
 608 static const char *mbus_parents[] = {"osc24M", "pll_periph0-2x", "pll_ddr"};
 609 NM_CLK(mbus_clk,
 610     H3_CLK_MBUS, "mbus", mbus_parents,          /* id, name, parents */
 611     0x15C,                                      /* offset */
 612     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 613     0, 3, 0, 0,                                 /* m factor */
 614     24, 2,                                      /* mux */
 615     31,                                         /* gate */
 616     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 617
 618 static const char *gpu_parents[] = {"pll_gpu"};
 619 NM_CLK(gpu_clk,
 620     H3_CLK_GPU, "gpu", gpu_parents,             /* id, name, parents */
 621     0x1A0,                                      /* offset */
 622     0, 2, 0, 0,                                 /* n factor */
 623     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* m factor (fake) */
 624     0, 0,                                       /* mux */
 625     31,                                         /* gate */
 626     AW_CLK_HAS_GATE);                           /* flags */
 627
 628 static struct aw_clk_nkmp_def *nkmp_clks[] = {
 629         &pll_cpux_clk,
 630         &pll_audio_clk,
 631         &pll_periph0_clk,
 632         &pll_periph1_clk,
 633         &pll_ddr_clk,
 634 };
 635
 636 static struct aw_clk_nm_def *nm_clks[] = {
 637         &pll_video_clk,
 638         &pll_ve_clk,
 639         &pll_gpu_clk,
 640         &pll_de_clk,
 641         &apb2_clk,
 642         &nand_clk,
 643         &mmc0_clk,
 644         &mmc1_clk,
 645         &mmc2_clk,
 646         &ts_clk,
 647         &ce_clk,
 648         &spi0_clk,
 649         &spi1_clk,
 650         &spdif_clk,
 651         &dram_clk,
 652         &de_clk,
 653         &tcon0_clk,
 654         &tve_clk,
 655         &deinterlace_clk,
 656         &csi_sclk_clk,
 657         &csi_mclk_clk,
 658         &ve_clk,
 659         &hdmi_clk,
 660         &mbus_clk,
 661         &gpu_clk,
 662 };
 663
 664 static struct aw_clk_prediv_mux_def *prediv_mux_clks[] = {
 665         &ahb1_clk,
 666         &ahb2_clk,
 667 };
 668
 669 static struct clk_mux_def *mux_clks[] = {
 670         &cpux_clk,
 671         &i2s0mux_clk,
 672         &i2s1mux_clk,
 673         &i2s2mux_clk,
 674 };
 675
 676 static struct clk_div_def *div_clks[] = {
 677         &axi_clk,
 678         &apb1_clk,
 679         &thsdiv_clk,
 680 };
 681
 682 static struct clk_fixed_def *fixed_factor_clks[] = {
 683         &pll_periph0_2x_clk,
 684         &pll_audio_2x_clk,
 685         &pll_audio_4x_clk,
 686         &pll_audio_8x_clk,
 687 };
 688
 689 static struct aw_clk_init init_clks[] = {
 690         {"ahb1", "pll_periph0", 0, false},
 691         {"ahb2", "pll_periph0", 0, false},
 692         {"dram", "pll_ddr", 0, false},
 693 };
 694
 695 void
 696 ccu_h3_register_clocks(struct aw_ccung_softc *sc)
 697 {
 698         int i;
 699
 700         sc->resets = h3_ccu_resets;
 701         sc->nresets = nitems(h3_ccu_resets);
 702         sc->gates = h3_ccu_gates;
 703         sc->ngates = nitems(h3_ccu_gates);
 704         sc->clk_init = init_clks;
 705         sc->n_clk_init = nitems(init_clks);
 706
 707         for (i = 0; i < nitems(nkmp_clks); i++)
 708                 aw_clk_nkmp_register(sc->clkdom, nkmp_clks[i]);
 709         for (i = 0; i < nitems(nm_clks); i++)
 710                 aw_clk_nm_register(sc->clkdom, nm_clks[i]);
 711         for (i = 0; i < nitems(prediv_mux_clks); i++)
 712                 aw_clk_prediv_mux_register(sc->clkdom, prediv_mux_clks[i]);
 713
 714         for (i = 0; i < nitems(mux_clks); i++)
 715                 clknode_mux_register(sc->clkdom, mux_clks[i]);
 716         for (i = 0; i < nitems(div_clks); i++)
 717                 clknode_div_register(sc->clkdom, div_clks[i]);
 718         for (i = 0; i < nitems(fixed_factor_clks); i++)
 719                 clknode_fixed_register(sc->clkdom, fixed_factor_clks[i]);
 720 }