sys/arm/allwinner/clkng/ccu_h3.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2017,2018 Emmanuel Vadot <manu@freebsd.org>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  20  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  21  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  22  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  23  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD$
  28  */
  29
  30 #include <sys/cdefs.h>
  31 __FBSDID("$FreeBSD$");
  32
  33 #include <sys/param.h>
  34 #include <sys/systm.h>
  35 #include <sys/bus.h>
  36 #include <sys/rman.h>
  37 #include <sys/kernel.h>
  38 #include <sys/module.h>
  39 #include <machine/bus.h>
  40
  41 #include <dev/fdt/simplebus.h>
  42
  43 #include <dev/ofw/ofw_bus.h>
  44 #include <dev/ofw/ofw_bus_subr.h>
  45
  46 #include <sys/param.h>
  47 #include <sys/systm.h>
  48 #include <sys/bus.h>
  49
  50 #include <dev/extres/clk/clk_div.h>
  51 #include <dev/extres/clk/clk_fixed.h>
  52 #include <dev/extres/clk/clk_mux.h>
  53
  54 #if defined(__aarch64__)
  55 #include "opt_soc.h"
  56 #endif
  57
  58 #include <arm/allwinner/clkng/aw_ccung.h>
  59
  60 #include <gnu/dts/include/dt-bindings/clock/sun8i-h3-ccu.h>
  61 #include <gnu/dts/include/dt-bindings/reset/sun8i-h3-ccu.h>
  62
  63 /* Non-exported resets */
  64 #define RST_BUS_SCR             53
  65
  66 /* Non-exported clocks */
  67 #define CLK_PLL_CPUX            0
  68 #define CLK_PLL_AUDIO_BASE      1
  69 #define CLK_PLL_AUDIO           2
  70 #define CLK_PLL_AUDIO_2X        3
  71 #define CLK_PLL_AUDIO_4X        4
  72 #define CLK_PLL_AUDIO_8X        5
  73 #define CLK_PLL_VIDEO           6
  74 #define CLK_PLL_VE              7
  75 #define CLK_PLL_DDR             8
  76 #define CLK_PLL_PERIPH0_2X      10
  77 #define CLK_PLL_GPU             11
  78 #define CLK_PLL_PERIPH1         12
  79 #define CLK_PLL_DE              13
  80
  81 #define CLK_AXI                 15
  82 #define CLK_AHB1                16
  83 #define CLK_APB1                17
  84 #define CLK_APB2                18
  85 #define CLK_AHB2                19
  86
  87 #define CLK_BUS_SCR             66
  88
  89 #define CLK_USBPHY0             88
  90 #define CLK_USBPHY1             89
  91 #define CLK_USBPHY2             90
  92 #define CLK_USBPHY3             91
  93 #define CLK_USBOHCI0            92
  94 #define CLK_USBOHCI1            93
  95 #define CLK_USBOHCI2            94
  96 #define CLK_USBOHCI3            95
  97 #define CLK_DRAM                96
  98
  99 #define CLK_MBUS                113
 100
 101 static struct aw_ccung_reset h3_ccu_resets[] = {
 102         CCU_RESET(RST_USB_PHY0, 0xcc, 0)
 103         CCU_RESET(RST_USB_PHY1, 0xcc, 1)
 104         CCU_RESET(RST_USB_PHY2, 0xcc, 2)
 105         CCU_RESET(RST_USB_PHY3, 0xcc, 3)
 106
 107         CCU_RESET(RST_MBUS, 0xfc, 31)
 108
 109         CCU_RESET(RST_BUS_CE, 0x2c0, 5)
 110         CCU_RESET(RST_BUS_DMA, 0x2c0, 6)
 111         CCU_RESET(RST_BUS_MMC0, 0x2c0, 8)
 112         CCU_RESET(RST_BUS_MMC1, 0x2c0, 9)
 113         CCU_RESET(RST_BUS_MMC2, 0x2c0, 10)
 114         CCU_RESET(RST_BUS_NAND, 0x2c0, 13)
 115         CCU_RESET(RST_BUS_DRAM, 0x2c0, 14)
 116         CCU_RESET(RST_BUS_EMAC, 0x2c0, 17)
 117         CCU_RESET(RST_BUS_TS, 0x2c0, 18)
 118         CCU_RESET(RST_BUS_HSTIMER, 0x2c0, 19)
 119         CCU_RESET(RST_BUS_SPI0, 0x2c0, 20)
 120         CCU_RESET(RST_BUS_SPI1, 0x2c0, 21)
 121         CCU_RESET(RST_BUS_OTG, 0x2c0, 23)
 122         CCU_RESET(RST_BUS_EHCI0, 0x2c0, 24)
 123         CCU_RESET(RST_BUS_EHCI1, 0x2c0, 25)
 124         CCU_RESET(RST_BUS_EHCI2, 0x2c0, 26)
 125         CCU_RESET(RST_BUS_EHCI3, 0x2c0, 27)
 126         CCU_RESET(RST_BUS_OHCI0, 0x2c0, 28)
 127         CCU_RESET(RST_BUS_OHCI1, 0x2c0, 29)
 128         CCU_RESET(RST_BUS_OHCI2, 0x2c0, 30)
 129         CCU_RESET(RST_BUS_OHCI3, 0x2c0, 31)
 130
 131         CCU_RESET(RST_BUS_VE, 0x2c4, 0)
 132         CCU_RESET(RST_BUS_TCON0, 0x2c4, 3)
 133         CCU_RESET(RST_BUS_TCON1, 0x2c4, 4)
 134         CCU_RESET(RST_BUS_DEINTERLACE, 0x2c4, 5)
 135         CCU_RESET(RST_BUS_CSI, 0x2c4, 8)
 136         CCU_RESET(RST_BUS_TVE, 0x2c4, 9)
 137         CCU_RESET(RST_BUS_HDMI0, 0x2c4, 10)
 138         CCU_RESET(RST_BUS_HDMI1, 0x2c4, 11)
 139         CCU_RESET(RST_BUS_DE, 0x2c4, 12)
 140         CCU_RESET(RST_BUS_GPU, 0x2c4, 20)
 141         CCU_RESET(RST_BUS_MSGBOX, 0x2c4, 21)
 142         CCU_RESET(RST_BUS_SPINLOCK, 0x2c4, 22)
 143         CCU_RESET(RST_BUS_DBG, 0x2c4, 31)
 144
 145         CCU_RESET(RST_BUS_EPHY, 0x2c8, 2)
 146
 147         CCU_RESET(RST_BUS_CODEC, 0x2d0, 0)
 148         CCU_RESET(RST_BUS_SPDIF, 0x2d0, 1)
 149         CCU_RESET(RST_BUS_THS, 0x2d0, 8)
 150         CCU_RESET(RST_BUS_I2S0, 0x2d0, 12)
 151         CCU_RESET(RST_BUS_I2S1, 0x2d0, 13)
 152         CCU_RESET(RST_BUS_I2S2, 0x2d0, 14)
 153
 154         CCU_RESET(RST_BUS_I2C0, 0x2d8, 0)
 155         CCU_RESET(RST_BUS_I2C1, 0x2d8, 1)
 156         CCU_RESET(RST_BUS_I2C2, 0x2d8, 2)
 157         CCU_RESET(RST_BUS_UART0, 0x2d8, 16)
 158         CCU_RESET(RST_BUS_UART1, 0x2d8, 17)
 159         CCU_RESET(RST_BUS_UART2, 0x2d8, 18)
 160         CCU_RESET(RST_BUS_UART3, 0x2d8, 19)
 161         CCU_RESET(RST_BUS_SCR, 0x2d8, 20)
 162 };
 163
 164 static struct aw_ccung_gate h3_ccu_gates[] = {
 165         CCU_GATE(CLK_BUS_CE, "bus-ce", "ahb1", 0x60, 5)
 166         CCU_GATE(CLK_BUS_DMA, "bus-dma", "ahb1", 0x60, 6)
 167         CCU_GATE(CLK_BUS_MMC0, "bus-mmc0", "ahb1", 0x60, 8)
 168         CCU_GATE(CLK_BUS_MMC1, "bus-mmc1", "ahb1", 0x60, 9)
 169         CCU_GATE(CLK_BUS_MMC2, "bus-mmc2", "ahb1", 0x60, 10)
 170         CCU_GATE(CLK_BUS_NAND, "bus-nand", "ahb1", 0x60, 13)
 171         CCU_GATE(CLK_BUS_DRAM, "bus-dram", "ahb1", 0x60, 14)
 172         CCU_GATE(CLK_BUS_EMAC, "bus-emac", "ahb2", 0x60, 17)
 173         CCU_GATE(CLK_BUS_TS, "bus-ts", "ahb1", 0x60, 18)
 174         CCU_GATE(CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 0x60, 19)
 175         CCU_GATE(CLK_BUS_SPI0, "bus-spi0", "ahb1", 0x60, 20)
 176         CCU_GATE(CLK_BUS_SPI1, "bus-spi1", "ahb1", 0x60, 21)
 177         CCU_GATE(CLK_BUS_OTG, "bus-otg", "ahb1", 0x60, 23)
 178         CCU_GATE(CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 0x60, 24)
 179         CCU_GATE(CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 0x60, 25)
 180         CCU_GATE(CLK_BUS_EHCI2, "bus-ehci2", "ahb2", 0x60, 26)
 181         CCU_GATE(CLK_BUS_EHCI3, "bus-ehci3", "ahb2", 0x60, 27)
 182         CCU_GATE(CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 0x60, 28)
 183         CCU_GATE(CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 0x60, 29)
 184         CCU_GATE(CLK_BUS_OHCI2, "bus-ohci2", "ahb2", 0x60, 30)
 185         CCU_GATE(CLK_BUS_OHCI3, "bus-ohci3", "ahb2", 0x60, 31)
 186
 187         CCU_GATE(CLK_BUS_VE, "bus-ve", "ahb1", 0x64, 0)
 188         CCU_GATE(CLK_BUS_TCON0, "bus-tcon0", "ahb1", 0x64, 3)
 189         CCU_GATE(CLK_BUS_TCON1, "bus-tcon1", "ahb1", 0x64, 4)
 190         CCU_GATE(CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 0x64, 5)
 191         CCU_GATE(CLK_BUS_CSI, "bus-csi", "ahb1", 0x64, 8)
 192         CCU_GATE(CLK_BUS_TVE, "bus-tve", "ahb1", 0x64, 9)
 193         CCU_GATE(CLK_BUS_HDMI, "bus-hdmi", "ahb1", 0x64, 11)
 194         CCU_GATE(CLK_BUS_DE, "bus-de", "ahb1", 0x64, 12)
 195         CCU_GATE(CLK_BUS_GPU, "bus-gpu", "ahb1", 0x64, 20)
 196         CCU_GATE(CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 0x64, 21)
 197         CCU_GATE(CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 0x64, 22)
 198
 199         CCU_GATE(CLK_BUS_CODEC, "bus-codec", "apb1", 0x68, 0)
 200         CCU_GATE(CLK_BUS_SPDIF, "bus-spdif", "apb1", 0x68, 1)
 201         CCU_GATE(CLK_BUS_PIO, "bus-pio", "apb1", 0x68, 5)
 202         CCU_GATE(CLK_BUS_THS, "bus-ths", "apb1", 0x68, 8)
 203         CCU_GATE(CLK_BUS_I2S0, "bus-i2s0", "apb1", 0x68, 12)
 204         CCU_GATE(CLK_BUS_I2S1, "bus-i2s1", "apb1", 0x68, 13)
 205         CCU_GATE(CLK_BUS_I2S2, "bus-i2s2", "apb1", 0x68, 14)
 206
 207         CCU_GATE(CLK_BUS_I2C0, "bus-i2c0", "apb2", 0x6c, 0)
 208         CCU_GATE(CLK_BUS_I2C1, "bus-i2c1", "apb2", 0x6c, 1)
 209         CCU_GATE(CLK_BUS_I2C2, "bus-i2c2", "apb2", 0x6c, 2)
 210         CCU_GATE(CLK_BUS_UART0, "bus-uart0", "apb2", 0x6c, 16)
 211         CCU_GATE(CLK_BUS_UART1, "bus-uart1", "apb2", 0x6c, 17)
 212         CCU_GATE(CLK_BUS_UART2, "bus-uart2", "apb2", 0x6c, 18)
 213         CCU_GATE(CLK_BUS_UART3, "bus-uart3", "apb2", 0x6c, 19)
 214         CCU_GATE(CLK_BUS_SCR, "bus-scr", "apb2", 0x6c, 20)
 215
 216         CCU_GATE(CLK_BUS_EPHY, "bus-ephy", "ahb1", 0x70, 0)
 217         CCU_GATE(CLK_BUS_DBG, "bus-dbg", "ahb1", 0x70, 7)
 218
 219         CCU_GATE(CLK_USBPHY0, "usb-phy0", "osc24M", 0xcc, 8)
 220         CCU_GATE(CLK_USBPHY1, "usb-phy1", "osc24M", 0xcc, 9)
 221         CCU_GATE(CLK_USBPHY2, "usb-phy2", "osc24M", 0xcc, 10)
 222         CCU_GATE(CLK_USBPHY3, "usb-phy3", "osc24M", 0xcc, 11)
 223         CCU_GATE(CLK_USBOHCI0, "usb-ohci0", "osc24M", 0xcc, 16)
 224         CCU_GATE(CLK_USBOHCI1, "usb-ohci1", "osc24M", 0xcc, 17)
 225         CCU_GATE(CLK_USBOHCI2, "usb-ohci2", "osc24M", 0xcc, 18)
 226         CCU_GATE(CLK_USBOHCI3, "usb-ohci3", "osc24M", 0xcc, 19)
 227
 228         CCU_GATE(CLK_THS, "ths", "thsdiv", 0x74, 31)
 229         CCU_GATE(CLK_I2S0, "i2s0", "i2s0mux", 0xB0, 31)
 230         CCU_GATE(CLK_I2S1, "i2s1", "i2s1mux", 0xB4, 31)
 231         CCU_GATE(CLK_I2S2, "i2s2", "i2s2mux", 0xB8, 31)
 232
 233         CCU_GATE(CLK_DRAM_VE, "dram-ve", "dram", 0x100, 0)
 234         CCU_GATE(CLK_DRAM_CSI, "dram-csi", "dram", 0x100, 1)
 235         CCU_GATE(CLK_DRAM_DEINTERLACE, "dram-deinterlace", "dram", 0x100, 2)
 236         CCU_GATE(CLK_DRAM_TS, "dram-ts", "dram", 0x100, 3)
 237
 238         CCU_GATE(CLK_AC_DIG, "ac-dig", "pll_audio", 0x140, 31)
 239
 240         CCU_GATE(CLK_AVS, "avs", "osc24M", 0x144, 31)
 241
 242         CCU_GATE(CLK_CSI_MISC, "csi-misc", "osc24M", 0x130, 31)
 243
 244         CCU_GATE(CLK_HDMI_DDC, "hdmi-ddc", "osc24M", 0x154, 31)
 245 };
 246
 247 static const char *pll_cpux_parents[] = {"osc24M"};
 248 NKMP_CLK(pll_cpux_clk,
 249     CLK_PLL_CPUX,                               /* id */
 250     "pll_cpux", pll_cpux_parents,               /* name, parents */
 251     0x00,                                       /* offset */
 252     8, 5, 0, 0,                                 /* n factor */
 253     4, 2, 0, 0,                                 /* k factor */
 254     0, 2, 0, 0,                                 /* m factor */
 255     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* p factor */
 256     31,                                         /* gate */
 257     28, 1000,                                   /* lock */
 258     AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK | AW_CLK_SCALE_CHANGE);           /* flags */
 259
 260 static const char *pll_audio_parents[] = {"osc24M"};
 261 NKMP_CLK(pll_audio_clk,
 262     CLK_PLL_AUDIO,                              /* id */
 263     "pll_audio", pll_audio_parents,             /* name, parents */
 264     0x08,                                       /* offset */
 265     8, 7, 0, 0,                                 /* n factor */
 266     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* k factor (fake) */
 267     0, 5, 0, 0,                                 /* m factor */
 268     16, 4, 0, 0,                                /* p factor */
 269     31,                                         /* gate */
 270     28, 1000,                                   /* lock */
 271     AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK);         /* flags */
 272
 273 static const char *pll_audio_mult_parents[] = {"pll_audio"};
 274 FIXED_CLK(pll_audio_2x_clk,
 275     CLK_PLL_AUDIO_2X,                   /* id */
 276     "pll_audio-2x",                     /* name */
 277     pll_audio_mult_parents,             /* parent */
 278     0,                                  /* freq */
 279     2,                                  /* mult */
 280     1,                                  /* div */
 281     0);                                 /* flags */
 282 FIXED_CLK(pll_audio_4x_clk,
 283     CLK_PLL_AUDIO_4X,                   /* id */
 284     "pll_audio-4x",                     /* name */
 285     pll_audio_mult_parents,             /* parent */
 286     0,                                  /* freq */
 287     4,                                  /* mult */
 288     1,                                  /* div */
 289     0);                                 /* flags */
 290 FIXED_CLK(pll_audio_8x_clk,
 291     CLK_PLL_AUDIO_8X,                   /* id */
 292     "pll_audio-8x",                     /* name */
 293     pll_audio_mult_parents,             /* parent */
 294     0,                                  /* freq */
 295     8,                                  /* mult */
 296     1,                                  /* div */
 297     0);                                 /* flags */
 298
 299 static const char *pll_video_parents[] = {"osc24M"};
 300 FRAC_CLK(pll_video_clk,
 301     CLK_PLL_VIDEO,                              /* id */
 302     "pll_video", pll_video_parents,             /* name, parents */
 303     0x10,                                       /* offset */
 304     8, 7, 0, 0,                                 /* n factor */
 305     0, 4, 0, 0,                                 /* m factor */
 306     31, 28, 1000,                               /* gate, lock, lock retries */
 307     AW_CLK_HAS_LOCK,                            /* flags */
 308     270000000, 297000000,                       /* freq0, freq1 */
 309     24, 25);                                    /* mode sel, freq sel */
 310
 311 static const char *pll_ve_parents[] = {"osc24M"};
 312 FRAC_CLK(pll_ve_clk,
 313     CLK_PLL_VE,                         /* id */
 314     "pll_ve", pll_ve_parents,                   /* name, parents */
 315     0x18,                                       /* offset */
 316     8, 7, 0, 0,                                 /* n factor */
 317     0, 4, 0, 0,                                 /* m factor */
 318     31, 28, 1000,                               /* gate, lock, lock retries */
 319     AW_CLK_HAS_LOCK,                            /* flags */
 320     270000000, 297000000,                       /* freq0, freq1 */
 321     24, 25);                                    /* mode sel, freq sel */
 322
 323 static const char *pll_ddr_parents[] = {"osc24M"};
 324 NKMP_CLK_WITH_UPDATE(pll_ddr_clk,
 325     CLK_PLL_DDR,                                /* id */
 326     "pll_ddr", pll_ddr_parents,                 /* name, parents */
 327     0x20,                                       /* offset */
 328     8, 5, 0, 0,                                 /* n factor */
 329     4, 2, 0, 0,                                 /* k factor */
 330     0, 2, 0, 0,                                 /* m factor */
 331     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* p factor (fake) */
 332     31,                                         /* gate */
 333     28, 1000,                                   /* lock */
 334     20,                                         /* update */
 335     AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK);         /* flags */
 336
 337 static const char *pll_periph0_parents[] = {"osc24M"};
 338 static const char *pll_periph0_2x_parents[] = {"pll_periph0"};
 339 NKMP_CLK(pll_periph0_clk,
 340     CLK_PLL_PERIPH0,                            /* id */
 341     "pll_periph0", pll_periph0_parents,         /* name, parents */
 342     0x28,                                       /* offset */
 343     8, 5, 0, 0,                                 /* n factor */
 344     4, 2, 0, 0,                                 /* k factor */
 345     0, 0, 2, AW_CLK_FACTOR_FIXED,               /* m factor (fake) */
 346     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* p factor (fake) */
 347     31,                                         /* gate */
 348     28, 1000,                                   /* lock */
 349     AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK);         /* flags */
 350 FIXED_CLK(pll_periph0_2x_clk,
 351     CLK_PLL_PERIPH0_2X,                 /* id */
 352     "pll_periph0-2x",                   /* name */
 353     pll_periph0_2x_parents,             /* parent */
 354     0,                                  /* freq */
 355     2,                                  /* mult */
 356     1,                                  /* div */
 357     0);                                 /* flags */
 358
 359 static const char *pll_gpu_parents[] = {"osc24M"};
 360 FRAC_CLK(pll_gpu_clk,
 361     CLK_PLL_GPU,                                /* id */
 362     "pll_gpu", pll_gpu_parents,                 /* name, parents */
 363     0x38,                                       /* offset */
 364     8, 7, 0, 0,                                 /* n factor */
 365     0, 4, 0, 0,                                 /* m factor */
 366     31, 28, 1000,                               /* gate, lock, lock retries */
 367     AW_CLK_HAS_LOCK,                            /* flags */
 368     270000000, 297000000,                       /* freq0, freq1 */
 369     24, 25);                                    /* mode sel, freq sel */
 370
 371 static const char *pll_periph1_parents[] = {"osc24M"};
 372 NKMP_CLK(pll_periph1_clk,
 373     CLK_PLL_PERIPH1,                            /* id */
 374     "pll_periph1", pll_periph1_parents,         /* name, parents */
 375     0x44,                                       /* offset */
 376     8, 5, 0, 0,                                 /* n factor */
 377     4, 2, 0, 0,                                 /* k factor */
 378     0, 0, 2, AW_CLK_FACTOR_FIXED,               /* m factor (fake) */
 379     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* p factor (fake) */
 380     31,                                         /* gate */
 381     28, 1000,                                   /* lock */
 382     AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK);         /* flags */
 383
 384 static const char *pll_de_parents[] = {"osc24M"};
 385 FRAC_CLK(pll_de_clk,
 386     CLK_PLL_DE,                                 /* id */
 387     "pll_de", pll_de_parents,                   /* name, parents */
 388     0x48,                                       /* offset */
 389     8, 7, 0, 0,                                 /* n factor */
 390     0, 4, 0, 0,                                 /* m factor */
 391     31, 28, 1000,                               /* gate, lock, lock retries */
 392     AW_CLK_HAS_LOCK,                            /* flags */
 393     270000000, 297000000,                       /* freq0, freq1 */
 394     24, 25);                                    /* mode sel, freq sel */
 395
 396 static const char *cpux_parents[] = {"osc32k", "osc24M", "pll_cpux", "pll_cpux"};
 397 MUX_CLK(cpux_clk,
 398     CLK_CPUX,                   /* id */
 399     "cpux", cpux_parents,       /* name, parents */
 400     0x50, 16, 2);               /* offset, shift, width */
 401
 402 static const char *axi_parents[] = {"cpux"};
 403 DIV_CLK(axi_clk,
 404     CLK_AXI,                    /* id */
 405     "axi", axi_parents,         /* name, parents */
 406     0x50,                       /* offset */
 407     0, 2,                       /* shift, width */
 408     0, NULL);                   /* flags, div table */
 409
 410 static const char *ahb1_parents[] = {"osc32k", "osc24M", "axi", "pll_periph0"};
 411 PREDIV_CLK(ahb1_clk, CLK_AHB1,                                  /* id */
 412     "ahb1", ahb1_parents,                                       /* name, parents */
 413     0x54,                                                       /* offset */
 414     12, 2,                                                      /* mux */
 415     4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,                        /* div */
 416     6, 2, 0, AW_CLK_FACTOR_HAS_COND,                            /* prediv */
 417     12, 2, 3);                                                  /* prediv condition */
 418
 419 static const char *apb1_parents[] = {"ahb1"};
 420 static struct clk_div_table apb1_div_table[] = {
 421         { .value = 0, .divider = 2, },
 422         { .value = 1, .divider = 2, },
 423         { .value = 2, .divider = 4, },
 424         { .value = 3, .divider = 8, },
 425         { },
 426 };
 427 DIV_CLK(apb1_clk,
 428     CLK_APB1,                   /* id */
 429     "apb1", apb1_parents,       /* name, parents */
 430     0x54,                       /* offset */
 431     8, 2,                       /* shift, width */
 432     CLK_DIV_WITH_TABLE,         /* flags */
 433     apb1_div_table);            /* div table */
 434
 435 static const char *apb2_parents[] = {"osc32k", "osc24M", "pll_periph0", "pll_periph0"};
 436 NM_CLK(apb2_clk,
 437     CLK_APB2,                                   /* id */
 438     "apb2", apb2_parents,                       /* name, parents */
 439     0x58,                                       /* offset */
 440     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 441     0, 5, 0, 0,                                 /* m factor */
 442     24, 2,                                      /* mux */
 443     0,                                          /* gate */
 444     AW_CLK_HAS_MUX);
 445
 446 static const char *ahb2_parents[] = {"ahb1", "pll_periph0"};
 447 PREDIV_CLK(ahb2_clk, CLK_AHB2,                                  /* id */
 448     "ahb2", ahb2_parents,                                       /* name, parents */
 449     0x5c,                                                       /* offset */
 450     0, 2,                                                       /* mux */
 451     0, 0, 1, AW_CLK_FACTOR_FIXED,                               /* div */
 452     0, 0, 2, AW_CLK_FACTOR_HAS_COND | AW_CLK_FACTOR_FIXED,      /* prediv */
 453     0, 2, 1);                                                   /* prediv condition */
 454
 455 static const char *ths_parents[] = {"osc24M"};
 456 static struct clk_div_table ths_div_table[] = {
 457         { .value = 0, .divider = 1, },
 458         { .value = 1, .divider = 2, },
 459         { .value = 2, .divider = 4, },
 460         { .value = 3, .divider = 6, },
 461         { },
 462 };
 463 DIV_CLK(thsdiv_clk,
 464     0,                          /* id */
 465     "thsdiv", ths_parents,      /* name, parents */
 466     0x74,                       /* offset */
 467     0, 2,                       /* shift, width */
 468     CLK_DIV_WITH_TABLE,         /* flags */
 469     ths_div_table);             /* div table */
 470
 471 static const char *mod_parents[] = {"osc24M", "pll_periph0", "pll_periph1"};
 472 NM_CLK(nand_clk,
 473     CLK_NAND, "nand", mod_parents,              /* id, name, parents */
 474     0x80,                                       /* offset */
 475     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 476     0, 4, 0, 0,                                 /* m factor */
 477     24, 2,                                      /* mux */
 478     31,                                         /* gate */
 479     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX);          /* flags */
 480
 481 NM_CLK(mmc0_clk,
 482     CLK_MMC0, "mmc0", mod_parents,              /* id, name, parents */
 483     0x88,                                       /* offset */
 484     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 485     0, 4, 0, 0,                                 /* m factor */
 486     24, 2,                                      /* mux */
 487     31,                                         /* gate */
 488     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
 489     AW_CLK_REPARENT);                           /* flags */
 490
 491 NM_CLK(mmc1_clk,
 492     CLK_MMC1, "mmc1", mod_parents,              /* id, name, parents */
 493     0x8c,                                       /* offset */
 494     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 495     0, 4, 0, 0,                                 /* m factor */
 496     24, 2,                                      /* mux */
 497     31,                                         /* gate */
 498     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
 499     AW_CLK_REPARENT);                           /* flags */
 500
 501 NM_CLK(mmc2_clk,
 502     CLK_MMC2, "mmc2", mod_parents,              /* id, name, parents */
 503     0x90,                                       /* offset */
 504     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 505     0, 4, 0, 0,                                 /* m factor */
 506     24, 2,                                      /* mux */
 507     31,                                         /* gate */
 508     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
 509     AW_CLK_REPARENT);                           /* flags */
 510
 511 static const char *ts_parents[] = {"osc24M", "pll_periph0"};
 512 NM_CLK(ts_clk,
 513     CLK_TS, "ts", ts_parents,                   /* id, name, parents */
 514     0x98,                                       /* offset */
 515     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 516     0, 4, 0, 0,                                 /* m factor */
 517     24, 2,                                      /* mux */
 518     31,                                         /* gate */
 519     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX);          /* flags */
 520
 521 NM_CLK(ce_clk,
 522     CLK_CE, "ce", mod_parents,                  /* id, name, parents */
 523     0x9C,                                       /* offset */
 524     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 525     0, 4, 0, 0,                                 /* m factor */
 526     24, 2,                                      /* mux */
 527     31,                                         /* gate */
 528     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX);          /* flags */
 529
 530 NM_CLK(spi0_clk,
 531     CLK_SPI0, "spi0", mod_parents,              /* id, name, parents */
 532     0xA0,                                       /* offset */
 533     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 534     0, 4, 0, 0,                                 /* m factor */
 535     24, 2,                                      /* mux */
 536     31,                                         /* gate */
 537     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
 538     AW_CLK_REPARENT);                           /* flags */
 539
 540 NM_CLK(spi1_clk,
 541     CLK_SPI1, "spi1", mod_parents,              /* id, name, parents */
 542     0xA4,                                       /* offset */
 543     16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO,       /* n factor */
 544     0, 4, 0, 0,                                 /* m factor */
 545     24, 2,                                      /* mux */
 546     31,                                         /* gate */
 547     AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
 548     AW_CLK_REPARENT);                           /* flags */
 549
 550 static const char *i2s_parents[] = {"pll_audio-8x", "pll_audio-4x", "pll_audio-2x", "pll_audio"};
 551 MUX_CLK(i2s0mux_clk,
 552     0, "i2s0mux", i2s_parents,                  /* id, name, parents */
 553     0xb0, 16, 2);                               /* offset, mux shift, mux width */
 554 MUX_CLK(i2s1mux_clk,
 555     0, "i2s1mux", i2s_parents,                  /* id, name, parents */
 556     0xb4, 16, 2);                               /* offset, mux shift, mux width */
 557 MUX_CLK(i2s2mux_clk,
 558     0, "i2s2mux", i2s_parents,                  /* id, name, parents */
 559     0xb8, 16, 2);                               /* offset, mux shift, mux width */
 560
 561 static const char *spdif_parents[] = {"pll_audio"};
 562 NM_CLK(spdif_clk,
 563     CLK_SPDIF, "spdif", spdif_parents,          /* id, name, parents */
 564     0xC0,                                       /* offset */
 565     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake); */
 566     0, 4, 0, 0,                                 /* m factor */
 567     0, 0,                                       /* mux */
 568     31,                                         /* gate */
 569     AW_CLK_HAS_GATE);                           /* flags */
 570
 571 static const char *dram_parents[] = {"pll_ddr", "pll_periph0-2x"};
 572 NM_CLK(dram_clk,
 573     CLK_DRAM, "dram", dram_parents,             /* id, name, parents */
 574     0xF4,                                       /* offset */
 575     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 576     0, 4, 0, 0,                                 /* m factor */
 577     20, 2,                                      /* mux */
 578     0,                                          /* gate */
 579     AW_CLK_HAS_MUX);                            /* flags */
 580
 581 static const char *de_parents[] = {"pll_periph0-2x", "pll_de"};
 582 NM_CLK(de_clk,
 583     CLK_DE, "de", de_parents,                   /* id, name, parents */
 584     0x104,                                      /* offset */
 585     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 586     0, 4, 0, 0,                                 /* m factor */
 587     24, 2,                                      /* mux */
 588     31,                                         /* gate */
 589     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 590
 591 static const char *tcon0_parents[] = {"pll_video"};
 592 NM_CLK(tcon0_clk,
 593     CLK_TCON0, "tcon0", tcon0_parents,          /* id, name, parents */
 594     0x118,                                      /* offset */
 595     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 596     0, 4, 0, 0,                                 /* m factor */
 597     24, 2,                                      /* mux */
 598     31,                                         /* gate */
 599     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 600
 601 static const char *tve_parents[] = {"pll_de", "pll_periph1"};
 602 NM_CLK(tve_clk,
 603     CLK_TVE, "tve", tve_parents,                /* id, name, parents */
 604     0x120,                                      /* offset */
 605     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 606     0, 4, 0, 0,                                 /* m factor */
 607     24, 2,                                      /* mux */
 608     31,                                         /* gate */
 609     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 610
 611 static const char *deinterlace_parents[] = {"pll_periph0", "pll_periph1"};
 612 NM_CLK(deinterlace_clk,
 613     CLK_DEINTERLACE, "deinterlace", deinterlace_parents,        /* id, name, parents */
 614     0x124,                                      /* offset */
 615     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 616     0, 4, 0, 0,                                 /* m factor */
 617     24, 2,                                      /* mux */
 618     31,                                         /* gate */
 619     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 620
 621 static const char *csi_sclk_parents[] = {"pll_periph0", "pll_periph1"};
 622 NM_CLK(csi_sclk_clk,
 623     CLK_CSI_SCLK, "csi-sclk", csi_sclk_parents, /* id, name, parents */
 624     0x134,                                      /* offset */
 625     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 626     16, 4, 0, 0,                                /* m factor */
 627     24, 2,                                      /* mux */
 628     31,                                         /* gate */
 629     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 630
 631 static const char *csi_mclk_parents[] = {"osc24M", "pll_video", "pll_periph1"};
 632 NM_CLK(csi_mclk_clk,
 633     CLK_CSI_MCLK, "csi-mclk", csi_mclk_parents, /* id, name, parents */
 634     0x134,                                      /* offset */
 635     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 636     0, 4, 0, 0,                                 /* m factor */
 637     8, 2,                                       /* mux */
 638     15,                                         /* gate */
 639     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 640
 641 static const char *ve_parents[] = {"pll_ve"};
 642 NM_CLK(ve_clk,
 643     CLK_VE, "ve", ve_parents,                   /* id, name, parents */
 644     0x13C,                                      /* offset */
 645     16, 3, 0, 0,                                /* n factor */
 646     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* m factor (fake) */
 647     0, 0,                                       /* mux */
 648     31,                                         /* gate */
 649     AW_CLK_HAS_GATE);                           /* flags */
 650
 651 static const char *hdmi_parents[] = {"pll_video"};
 652 NM_CLK(hdmi_clk,
 653     CLK_HDMI, "hdmi", hdmi_parents,             /* id, name, parents */
 654     0x150,                                      /* offset */
 655     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 656     0, 4, 0, 0,                                 /* m factor */
 657     24, 2,                                      /* mux */
 658     31,                                         /* gate */
 659     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 660
 661 static const char *mbus_parents[] = {"osc24M", "pll_periph0-2x", "pll_ddr"};
 662 NM_CLK(mbus_clk,
 663     CLK_MBUS, "mbus", mbus_parents,             /* id, name, parents */
 664     0x15C,                                      /* offset */
 665     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* n factor (fake) */
 666     0, 3, 0, 0,                                 /* m factor */
 667     24, 2,                                      /* mux */
 668     31,                                         /* gate */
 669     AW_CLK_HAS_MUX | AW_CLK_HAS_GATE);          /* flags */
 670
 671 static const char *gpu_parents[] = {"pll_gpu"};
 672 NM_CLK(gpu_clk,
 673     CLK_GPU, "gpu", gpu_parents,                /* id, name, parents */
 674     0x1A0,                                      /* offset */
 675     0, 2, 0, 0,                                 /* n factor */
 676     0, 0, 1, AW_CLK_FACTOR_FIXED,               /* m factor (fake) */
 677     0, 0,                                       /* mux */
 678     31,                                         /* gate */
 679     AW_CLK_HAS_GATE);                           /* flags */
 680
 681 static struct aw_ccung_clk h3_ccu_clks[] = {
 682         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_cpux_clk},
 683         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_audio_clk},
 684         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph0_clk},
 685         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph1_clk},
 686         { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_clk},
 687         { .type = AW_CLK_FRAC, .clk.frac = &pll_video_clk},
 688         { .type = AW_CLK_FRAC, .clk.frac = &pll_ve_clk},
 689         { .type = AW_CLK_FRAC, .clk.frac = &pll_gpu_clk},
 690         { .type = AW_CLK_FRAC, .clk.frac = &pll_de_clk},
 691         { .type = AW_CLK_NM, .clk.nm = &apb2_clk},
 692         { .type = AW_CLK_NM, .clk.nm = &nand_clk},
 693         { .type = AW_CLK_NM, .clk.nm = &mmc0_clk},
 694         { .type = AW_CLK_NM, .clk.nm = &mmc1_clk},
 695         { .type = AW_CLK_NM, .clk.nm = &mmc2_clk},
 696         { .type = AW_CLK_NM, .clk.nm = &ts_clk},
 697         { .type = AW_CLK_NM, .clk.nm = &ce_clk},
 698         { .type = AW_CLK_NM, .clk.nm = &spi0_clk},
 699         { .type = AW_CLK_NM, .clk.nm = &spi1_clk},
 700         { .type = AW_CLK_NM, .clk.nm = &spdif_clk},
 701         { .type = AW_CLK_NM, .clk.nm = &dram_clk},
 702         { .type = AW_CLK_NM, .clk.nm = &de_clk},
 703         { .type = AW_CLK_NM, .clk.nm = &tcon0_clk},
 704         { .type = AW_CLK_NM, .clk.nm = &tve_clk},
 705         { .type = AW_CLK_NM, .clk.nm = &deinterlace_clk},
 706         { .type = AW_CLK_NM, .clk.nm = &csi_sclk_clk},
 707         { .type = AW_CLK_NM, .clk.nm = &csi_mclk_clk},
 708         { .type = AW_CLK_NM, .clk.nm = &ve_clk},
 709         { .type = AW_CLK_NM, .clk.nm = &hdmi_clk},
 710         { .type = AW_CLK_NM, .clk.nm = &mbus_clk},
 711         { .type = AW_CLK_NM, .clk.nm = &gpu_clk},
 712         { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb1_clk},
 713         { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb2_clk},
 714         { .type = AW_CLK_MUX, .clk.mux = &cpux_clk},
 715         { .type = AW_CLK_MUX, .clk.mux = &i2s0mux_clk},
 716         { .type = AW_CLK_MUX, .clk.mux = &i2s1mux_clk},
 717         { .type = AW_CLK_MUX, .clk.mux = &i2s2mux_clk},
 718         { .type = AW_CLK_DIV, .clk.div = &axi_clk},
 719         { .type = AW_CLK_DIV, .clk.div = &apb1_clk},
 720         { .type = AW_CLK_DIV, .clk.div = &thsdiv_clk},
 721         { .type = AW_CLK_FIXED, .clk.fixed = &pll_periph0_2x_clk},
 722         { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_2x_clk},
 723         { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_4x_clk},
 724         { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_8x_clk},
 725 };
 726
 727 static struct aw_clk_init h3_init_clks[] = {
 728         {"ahb1", "pll_periph0", 0, false},
 729         {"ahb2", "pll_periph0", 0, false},
 730         {"dram", "pll_ddr", 0, false},
 731 };
 732
 733 static struct ofw_compat_data compat_data[] = {
 734 #if defined(SOC_ALLWINNER_H3)
 735         { "allwinner,sun8i-h3-ccu", 1 },
 736 #endif
 737 #if defined(SOC_ALLWINNER_H5)
 738         { "allwinner,sun50i-h5-ccu", 1 },
 739 #endif
 740         { NULL, 0},
 741 };
 742
 743 static int
 744 ccu_h3_probe(device_t dev)
 745 {
 746
 747         if (!ofw_bus_status_okay(dev))
 748                 return (ENXIO);
 749
 750         if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
 751                 return (ENXIO);
 752
 753         device_set_desc(dev, "Allwinner H3/H5 Clock Control Unit NG");
 754         return (BUS_PROBE_DEFAULT);
 755 }
 756
 757 static int
 758 ccu_h3_attach(device_t dev)
 759 {
 760         struct aw_ccung_softc *sc;
 761
 762         sc = device_get_softc(dev);
 763
 764         sc->resets = h3_ccu_resets;
 765         sc->nresets = nitems(h3_ccu_resets);
 766         sc->gates = h3_ccu_gates;
 767         sc->ngates = nitems(h3_ccu_gates);
 768         sc->clks = h3_ccu_clks;
 769         sc->nclks = nitems(h3_ccu_clks);
 770         sc->clk_init = h3_init_clks;
 771         sc->n_clk_init = nitems(h3_init_clks);
 772
 773         return (aw_ccung_attach(dev));
 774 }
 775
 776 static device_method_t ccu_h3ng_methods[] = {
 777         /* Device interface */
 778         DEVMETHOD(device_probe,         ccu_h3_probe),
 779         DEVMETHOD(device_attach,        ccu_h3_attach),
 780
 781         DEVMETHOD_END
 782 };
 783
 784 static devclass_t ccu_h3ng_devclass;
 785
 786 DEFINE_CLASS_1(ccu_h3ng, ccu_h3ng_driver, ccu_h3ng_methods,
 787   sizeof(struct aw_ccung_softc), aw_ccung_driver);
 788
 789 EARLY_DRIVER_MODULE(ccu_h3ng, simplebus, ccu_h3ng_driver,
 790     ccu_h3ng_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_LAST);