2 * Copyright (c) 2017 Emmanuel Vadot <manu@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <dev/extres/clk/clk_div.h>
37 #include <dev/extres/clk/clk_fixed.h>
38 #include <dev/extres/clk/clk_mux.h>
40 #include <arm/allwinner/clkng/aw_ccung.h>
41 #include <arm/allwinner/clkng/aw_clk.h>
42 #include <arm/allwinner/clkng/aw_clk_nm.h>
43 #include <arm/allwinner/clkng/aw_clk_nkmp.h>
44 #include <arm/allwinner/clkng/aw_clk_prediv_mux.h>
46 #include <gnu/dts/include/dt-bindings/clock/sun8i-h3-ccu.h>
47 #include <gnu/dts/include/dt-bindings/reset/sun8i-h3-ccu.h>
51 /* Non-exported resets */
52 #define RST_BUS_SCR 53
54 /* Non-exported clocks */
55 #define CLK_PLL_CPUX 0
56 #define CLK_PLL_AUDIO_BASE 1
57 #define CLK_PLL_AUDIO 2
58 #define CLK_PLL_AUDIO_2X 3
59 #define CLK_PLL_AUDIO_4X 4
60 #define CLK_PLL_AUDIO_8X 5
61 #define CLK_PLL_VIDEO 6
64 #define CLK_PLL_PERIPH0_2X 10
65 #define CLK_PLL_GPU 11
66 #define CLK_PLL_PERIPH1 12
75 #define CLK_BUS_SCR 66
77 #define CLK_USBPHY0 88
78 #define CLK_USBPHY1 89
79 #define CLK_USBPHY2 90
80 #define CLK_USBPHY3 91
81 #define CLK_USBOHCI0 92
82 #define CLK_USBOHCI1 93
83 #define CLK_USBOHCI2 94
84 #define CLK_USBOHCI3 95
89 static struct aw_ccung_reset h3_ccu_resets[] = {
90 CCU_RESET(RST_USB_PHY0, 0xcc, 0)
91 CCU_RESET(RST_USB_PHY1, 0xcc, 1)
92 CCU_RESET(RST_USB_PHY2, 0xcc, 2)
93 CCU_RESET(RST_USB_PHY3, 0xcc, 3)
95 CCU_RESET(RST_MBUS, 0xfc, 31)
97 CCU_RESET(RST_BUS_CE, 0x2c0, 5)
98 CCU_RESET(RST_BUS_DMA, 0x2c0, 6)
99 CCU_RESET(RST_BUS_MMC0, 0x2c0, 8)
100 CCU_RESET(RST_BUS_MMC1, 0x2c0, 9)
101 CCU_RESET(RST_BUS_MMC2, 0x2c0, 10)
102 CCU_RESET(RST_BUS_NAND, 0x2c0, 13)
103 CCU_RESET(RST_BUS_DRAM, 0x2c0, 14)
104 CCU_RESET(RST_BUS_EMAC, 0x2c0, 17)
105 CCU_RESET(RST_BUS_TS, 0x2c0, 18)
106 CCU_RESET(RST_BUS_HSTIMER, 0x2c0, 19)
107 CCU_RESET(RST_BUS_SPI0, 0x2c0, 20)
108 CCU_RESET(RST_BUS_SPI1, 0x2c0, 21)
109 CCU_RESET(RST_BUS_OTG, 0x2c0, 23)
110 CCU_RESET(RST_BUS_EHCI0, 0x2c0, 24)
111 CCU_RESET(RST_BUS_EHCI1, 0x2c0, 25)
112 CCU_RESET(RST_BUS_EHCI2, 0x2c0, 26)
113 CCU_RESET(RST_BUS_EHCI3, 0x2c0, 27)
114 CCU_RESET(RST_BUS_OHCI0, 0x2c0, 28)
115 CCU_RESET(RST_BUS_OHCI1, 0x2c0, 29)
116 CCU_RESET(RST_BUS_OHCI2, 0x2c0, 30)
117 CCU_RESET(RST_BUS_OHCI3, 0x2c0, 31)
119 CCU_RESET(RST_BUS_VE, 0x2c4, 0)
120 CCU_RESET(RST_BUS_TCON0, 0x2c4, 3)
121 CCU_RESET(RST_BUS_TCON1, 0x2c4, 4)
122 CCU_RESET(RST_BUS_DEINTERLACE, 0x2c4, 5)
123 CCU_RESET(RST_BUS_CSI, 0x2c4, 8)
124 CCU_RESET(RST_BUS_TVE, 0x2c4, 9)
125 CCU_RESET(RST_BUS_HDMI0, 0x2c4, 10)
126 CCU_RESET(RST_BUS_HDMI1, 0x2c4, 11)
127 CCU_RESET(RST_BUS_DE, 0x2c4, 12)
128 CCU_RESET(RST_BUS_GPU, 0x2c4, 20)
129 CCU_RESET(RST_BUS_MSGBOX, 0x2c4, 21)
130 CCU_RESET(RST_BUS_SPINLOCK, 0x2c4, 22)
131 CCU_RESET(RST_BUS_DBG, 0x2c4, 31)
133 CCU_RESET(RST_BUS_EPHY, 0x2c8, 2)
135 CCU_RESET(RST_BUS_CODEC, 0x2d0, 0)
136 CCU_RESET(RST_BUS_SPDIF, 0x2d0, 1)
137 CCU_RESET(RST_BUS_THS, 0x2d0, 8)
138 CCU_RESET(RST_BUS_I2S0, 0x2d0, 12)
139 CCU_RESET(RST_BUS_I2S1, 0x2d0, 13)
140 CCU_RESET(RST_BUS_I2S2, 0x2d0, 14)
142 CCU_RESET(RST_BUS_I2C0, 0x2d8, 0)
143 CCU_RESET(RST_BUS_I2C1, 0x2d8, 1)
144 CCU_RESET(RST_BUS_I2C2, 0x2d8, 2)
145 CCU_RESET(RST_BUS_UART0, 0x2d8, 16)
146 CCU_RESET(RST_BUS_UART1, 0x2d8, 17)
147 CCU_RESET(RST_BUS_UART2, 0x2d8, 18)
148 CCU_RESET(RST_BUS_UART3, 0x2d8, 19)
149 CCU_RESET(RST_BUS_SCR, 0x2d8, 20)
152 static struct aw_ccung_gate h3_ccu_gates[] = {
153 CCU_GATE(CLK_BUS_CE, "bus-ce", "ahb1", 0x60, 5)
154 CCU_GATE(CLK_BUS_DMA, "bus-dma", "ahb1", 0x60, 6)
155 CCU_GATE(CLK_BUS_MMC0, "bus-mmc0", "ahb1", 0x60, 8)
156 CCU_GATE(CLK_BUS_MMC1, "bus-mmc1", "ahb1", 0x60, 9)
157 CCU_GATE(CLK_BUS_MMC2, "bus-mmc2", "ahb1", 0x60, 10)
158 CCU_GATE(CLK_BUS_NAND, "bus-nand", "ahb1", 0x60, 13)
159 CCU_GATE(CLK_BUS_DRAM, "bus-dram", "ahb1", 0x60, 14)
160 CCU_GATE(CLK_BUS_EMAC, "bus-emac", "ahb2", 0x60, 17)
161 CCU_GATE(CLK_BUS_TS, "bus-ts", "ahb1", 0x60, 18)
162 CCU_GATE(CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 0x60, 19)
163 CCU_GATE(CLK_BUS_SPI0, "bus-spi0", "ahb1", 0x60, 20)
164 CCU_GATE(CLK_BUS_SPI1, "bus-spi1", "ahb1", 0x60, 21)
165 CCU_GATE(CLK_BUS_OTG, "bus-otg", "ahb1", 0x60, 23)
166 CCU_GATE(CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 0x60, 24)
167 CCU_GATE(CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 0x60, 25)
168 CCU_GATE(CLK_BUS_EHCI2, "bus-ehci2", "ahb2", 0x60, 26)
169 CCU_GATE(CLK_BUS_EHCI3, "bus-ehci3", "ahb2", 0x60, 27)
170 CCU_GATE(CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 0x60, 28)
171 CCU_GATE(CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 0x60, 29)
172 CCU_GATE(CLK_BUS_OHCI2, "bus-ohci2", "ahb2", 0x60, 30)
173 CCU_GATE(CLK_BUS_OHCI3, "bus-ohci3", "ahb2", 0x60, 31)
175 CCU_GATE(CLK_BUS_VE, "bus-ve", "ahb1", 0x64, 0)
176 CCU_GATE(CLK_BUS_TCON0, "bus-tcon0", "ahb1", 0x64, 3)
177 CCU_GATE(CLK_BUS_TCON1, "bus-tcon1", "ahb1", 0x64, 4)
178 CCU_GATE(CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 0x64, 5)
179 CCU_GATE(CLK_BUS_CSI, "bus-csi", "ahb1", 0x64, 8)
180 CCU_GATE(CLK_BUS_TVE, "bus-tve", "ahb1", 0x64, 9)
181 CCU_GATE(CLK_BUS_HDMI, "bus-hdmi", "ahb1", 0x64, 11)
182 CCU_GATE(CLK_BUS_DE, "bus-de", "ahb1", 0x64, 12)
183 CCU_GATE(CLK_BUS_GPU, "bus-gpu", "ahb1", 0x64, 20)
184 CCU_GATE(CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 0x64, 21)
185 CCU_GATE(CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 0x64, 22)
187 CCU_GATE(CLK_BUS_CODEC, "bus-codec", "apb1", 0x68, 0)
188 CCU_GATE(CLK_BUS_SPDIF, "bus-spdif", "apb1", 0x68, 1)
189 CCU_GATE(CLK_BUS_PIO, "bus-pio", "apb1", 0x68, 5)
190 CCU_GATE(CLK_BUS_THS, "bus-ths", "apb1", 0x68, 8)
191 CCU_GATE(CLK_BUS_I2S0, "bus-i2s0", "apb1", 0x68, 12)
192 CCU_GATE(CLK_BUS_I2S1, "bus-i2s1", "apb1", 0x68, 13)
193 CCU_GATE(CLK_BUS_I2S2, "bus-i2s2", "apb1", 0x68, 14)
195 CCU_GATE(CLK_BUS_I2C0, "bus-i2c0", "apb2", 0x6c, 0)
196 CCU_GATE(CLK_BUS_I2C1, "bus-i2c1", "apb2", 0x6c, 1)
197 CCU_GATE(CLK_BUS_I2C2, "bus-i2c2", "apb2", 0x6c, 2)
198 CCU_GATE(CLK_BUS_UART0, "bus-uart0", "apb2", 0x6c, 16)
199 CCU_GATE(CLK_BUS_UART1, "bus-uart1", "apb2", 0x6c, 17)
200 CCU_GATE(CLK_BUS_UART2, "bus-uart2", "apb2", 0x6c, 18)
201 CCU_GATE(CLK_BUS_UART3, "bus-uart3", "apb2", 0x6c, 19)
202 CCU_GATE(CLK_BUS_SCR, "bus-scr", "apb2", 0x6c, 20)
204 CCU_GATE(CLK_BUS_EPHY, "bus-ephy", "ahb1", 0x70, 0)
205 CCU_GATE(CLK_BUS_DBG, "bus-dbg", "ahb1", 0x70, 7)
207 CCU_GATE(CLK_USBPHY0, "usb-phy0", "osc24M", 0xcc, 8)
208 CCU_GATE(CLK_USBPHY1, "usb-phy1", "osc24M", 0xcc, 9)
209 CCU_GATE(CLK_USBPHY2, "usb-phy2", "osc24M", 0xcc, 10)
210 CCU_GATE(CLK_USBPHY3, "usb-phy3", "osc24M", 0xcc, 11)
211 CCU_GATE(CLK_USBOHCI0, "usb-ohci0", "osc24M", 0xcc, 16)
212 CCU_GATE(CLK_USBOHCI1, "usb-ohci1", "osc24M", 0xcc, 17)
213 CCU_GATE(CLK_USBOHCI2, "usb-ohci2", "osc24M", 0xcc, 18)
214 CCU_GATE(CLK_USBOHCI3, "usb-ohci3", "osc24M", 0xcc, 19)
216 CCU_GATE(CLK_THS, "ths", "thsdiv", 0x74, 31)
217 CCU_GATE(CLK_I2S0, "i2s0", "i2s0mux", 0xB0, 31)
218 CCU_GATE(CLK_I2S1, "i2s1", "i2s1mux", 0xB4, 31)
219 CCU_GATE(CLK_I2S2, "i2s2", "i2s2mux", 0xB8, 31)
221 CCU_GATE(CLK_DRAM_VE, "dram-ve", "dram", 0x100, 0)
222 CCU_GATE(CLK_DRAM_CSI, "dram-csi", "dram", 0x100, 1)
223 CCU_GATE(CLK_DRAM_DEINTERLACE, "dram-deinterlace", "dram", 0x100, 2)
224 CCU_GATE(CLK_DRAM_TS, "dram-ts", "dram", 0x100, 3)
226 CCU_GATE(CLK_AC_DIG, "ac-dig", "pll_audio", 0x140, 31)
228 CCU_GATE(CLK_AVS, "avs", "osc24M", 0x144, 31)
230 CCU_GATE(CLK_CSI_MISC, "csi-misc", "osc24M", 0x130, 31)
232 CCU_GATE(CLK_HDMI_DDC, "hdmi-ddc", "osc24M", 0x154, 31)
235 static const char *pll_cpux_parents[] = {"osc24M"};
236 NKMP_CLK(pll_cpux_clk,
237 CLK_PLL_CPUX, /* id */
238 "pll_cpux", pll_cpux_parents, /* name, parents */
240 8, 5, 0, 0, /* n factor */
241 4, 2, 0, 0, /* k factor */
242 0, 2, 0, 0, /* m factor */
243 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */
246 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK | AW_CLK_SCALE_CHANGE); /* flags */
248 static const char *pll_audio_parents[] = {"osc24M"};
249 NKMP_CLK(pll_audio_clk,
250 CLK_PLL_AUDIO, /* id */
251 "pll_audio", pll_audio_parents, /* name, parents */
253 8, 7, 0, 0, /* n factor */
254 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */
255 0, 5, 0, 0, /* m factor */
256 16, 4, 0, 0, /* p factor */
259 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */
261 static const char *pll_audio_mult_parents[] = {"pll_audio"};
262 FIXED_CLK(pll_audio_2x_clk,
263 CLK_PLL_AUDIO_2X, /* id */
264 "pll_audio-2x", /* name */
265 pll_audio_mult_parents, /* parent */
270 FIXED_CLK(pll_audio_4x_clk,
271 CLK_PLL_AUDIO_4X, /* id */
272 "pll_audio-4x", /* name */
273 pll_audio_mult_parents, /* parent */
278 FIXED_CLK(pll_audio_8x_clk,
279 CLK_PLL_AUDIO_8X, /* id */
280 "pll_audio-8x", /* name */
281 pll_audio_mult_parents, /* parent */
287 static const char *pll_video_parents[] = {"osc24M"};
288 NM_CLK_WITH_FRAC(pll_video_clk,
289 CLK_PLL_VIDEO, /* id */
290 "pll_video", pll_video_parents, /* name, parents */
292 8, 7, 0, 0, /* n factor */
293 0, 4, 0, 0, /* m factor */
294 31, 28, 1000, /* gate, lock, lock retries */
295 AW_CLK_HAS_LOCK, /* flags */
296 270000000, 297000000, /* freq0, freq1 */
297 24, 25); /* mode sel, freq sel */
299 static const char *pll_ve_parents[] = {"osc24M"};
300 NM_CLK_WITH_FRAC(pll_ve_clk,
302 "pll_ve", pll_ve_parents, /* name, parents */
304 8, 7, 0, 0, /* n factor */
305 0, 4, 0, 0, /* m factor */
306 31, 28, 1000, /* gate, lock, lock retries */
307 AW_CLK_HAS_LOCK, /* flags */
308 270000000, 297000000, /* freq0, freq1 */
309 24, 25); /* mode sel, freq sel */
311 static const char *pll_ddr_parents[] = {"osc24M"};
312 NKMP_CLK_WITH_UPDATE(pll_ddr_clk,
313 CLK_PLL_DDR, /* id */
314 "pll_ddr", pll_ddr_parents, /* name, parents */
316 8, 5, 0, 0, /* n factor */
317 4, 2, 0, 0, /* k factor */
318 0, 2, 0, 0, /* m factor */
319 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */
323 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */
325 static const char *pll_periph0_parents[] = {"osc24M"};
326 static const char *pll_periph0_2x_parents[] = {"pll_periph0"};
327 NKMP_CLK(pll_periph0_clk,
328 CLK_PLL_PERIPH0, /* id */
329 "pll_periph0", pll_periph0_parents, /* name, parents */
331 8, 5, 0, 0, /* n factor */
332 4, 2, 0, 0, /* k factor */
333 0, 0, 2, AW_CLK_FACTOR_FIXED, /* m factor (fake) */
334 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */
337 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */
338 FIXED_CLK(pll_periph0_2x_clk,
339 CLK_PLL_PERIPH0_2X, /* id */
340 "pll_periph0-2x", /* name */
341 pll_periph0_2x_parents, /* parent */
347 static const char *pll_gpu_parents[] = {"osc24M"};
348 NM_CLK_WITH_FRAC(pll_gpu_clk,
349 CLK_PLL_GPU, /* id */
350 "pll_gpu", pll_gpu_parents, /* name, parents */
352 8, 7, 0, 0, /* n factor */
353 0, 4, 0, 0, /* m factor */
354 31, 28, 1000, /* gate, lock, lock retries */
355 AW_CLK_HAS_LOCK, /* flags */
356 270000000, 297000000, /* freq0, freq1 */
357 24, 25); /* mode sel, freq sel */
359 static const char *pll_periph1_parents[] = {"osc24M"};
360 NKMP_CLK(pll_periph1_clk,
361 CLK_PLL_PERIPH1, /* id */
362 "pll_periph1", pll_periph1_parents, /* name, parents */
364 8, 5, 0, 0, /* n factor */
365 4, 2, 0, 0, /* k factor */
366 0, 0, 2, AW_CLK_FACTOR_FIXED, /* m factor (fake) */
367 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */
370 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */
372 static const char *pll_de_parents[] = {"osc24M"};
373 NM_CLK_WITH_FRAC(pll_de_clk,
375 "pll_de", pll_de_parents, /* name, parents */
377 8, 7, 0, 0, /* n factor */
378 0, 4, 0, 0, /* m factor */
379 31, 28, 1000, /* gate, lock, lock retries */
380 AW_CLK_HAS_LOCK, /* flags */
381 270000000, 297000000, /* freq0, freq1 */
382 24, 25); /* mode sel, freq sel */
384 static const char *cpux_parents[] = {"osc32k", "osc24M", "pll_cpux", "pll_cpux"};
387 "cpux", cpux_parents, /* name, parents */
388 0x50, 16, 2); /* offset, shift, width */
390 static const char *axi_parents[] = {"cpux"};
393 "axi", axi_parents, /* name, parents */
395 0, 2, /* shift, width */
396 0, NULL); /* flags, div table */
398 static const char *ahb1_parents[] = {"osc32k", "osc24M", "axi", "pll_periph0"};
399 PREDIV_CLK(ahb1_clk, CLK_AHB1, /* id */
400 "ahb1", ahb1_parents, /* name, parents */
403 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */
404 6, 2, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */
405 12, 2, 3); /* prediv condition */
407 static const char *apb1_parents[] = {"ahb1"};
408 static struct clk_div_table apb1_div_table[] = {
409 { .value = 0, .divider = 2, },
410 { .value = 1, .divider = 2, },
411 { .value = 2, .divider = 4, },
412 { .value = 3, .divider = 8, },
417 "apb1", apb1_parents, /* name, parents */
419 8, 2, /* shift, width */
420 CLK_DIV_WITH_TABLE, /* flags */
421 apb1_div_table); /* div table */
423 static const char *apb2_parents[] = {"osc32k", "osc24M", "pll_periph0", "pll_periph0"};
426 "apb2", apb2_parents, /* name, parents */
428 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
429 0, 5, 0, 0, /* m factor */
434 static const char *ahb2_parents[] = {"ahb1", "pll_periph0"};
435 PREDIV_CLK(ahb2_clk, CLK_AHB2, /* id */
436 "ahb2", ahb2_parents, /* name, parents */
439 0, 0, 1, AW_CLK_FACTOR_FIXED, /* div */
440 0, 0, 2, AW_CLK_FACTOR_HAS_COND | AW_CLK_FACTOR_FIXED, /* prediv */
441 0, 2, 1); /* prediv condition */
443 static const char *ths_parents[] = {"osc24M"};
444 static struct clk_div_table ths_div_table[] = {
445 { .value = 0, .divider = 1, },
446 { .value = 1, .divider = 2, },
447 { .value = 2, .divider = 4, },
448 { .value = 3, .divider = 6, },
453 "thsdiv", ths_parents, /* name, parents */
455 0, 2, /* shift, width */
456 CLK_DIV_WITH_TABLE, /* flags */
457 ths_div_table); /* div table */
459 static const char *mod_parents[] = {"osc24M", "pll_periph0", "pll_periph1"};
461 CLK_NAND, "nand", mod_parents, /* id, name, parents */
463 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
464 0, 4, 0, 0, /* m factor */
467 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */
470 CLK_MMC0, "mmc0", mod_parents, /* id, name, parents */
472 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
473 0, 4, 0, 0, /* m factor */
476 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
477 AW_CLK_REPARENT); /* flags */
480 CLK_MMC1, "mmc1", mod_parents, /* id, name, parents */
482 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
483 0, 4, 0, 0, /* m factor */
486 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
487 AW_CLK_REPARENT); /* flags */
490 CLK_MMC2, "mmc2", mod_parents, /* id, name, parents */
492 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
493 0, 4, 0, 0, /* m factor */
496 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
497 AW_CLK_REPARENT); /* flags */
499 static const char *ts_parents[] = {"osc24M", "pll_periph0"};
501 CLK_TS, "ts", ts_parents, /* id, name, parents */
503 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
504 0, 4, 0, 0, /* m factor */
507 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */
510 CLK_CE, "ce", mod_parents, /* id, name, parents */
512 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
513 0, 4, 0, 0, /* m factor */
516 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */
519 CLK_SPI0, "spi0", mod_parents, /* id, name, parents */
521 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
522 0, 4, 0, 0, /* m factor */
525 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
526 AW_CLK_REPARENT); /* flags */
529 CLK_SPI1, "spi1", mod_parents, /* id, name, parents */
531 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
532 0, 4, 0, 0, /* m factor */
535 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
536 AW_CLK_REPARENT); /* flags */
538 static const char *i2s_parents[] = {"pll_audio-8x", "pll_audio-4x", "pll_audio-2x", "pll_audio"};
540 0, "i2s0mux", i2s_parents, /* id, name, parents */
541 0xb0, 16, 2); /* offset, mux shift, mux width */
543 0, "i2s1mux", i2s_parents, /* id, name, parents */
544 0xb4, 16, 2); /* offset, mux shift, mux width */
546 0, "i2s2mux", i2s_parents, /* id, name, parents */
547 0xb8, 16, 2); /* offset, mux shift, mux width */
549 static const char *spdif_parents[] = {"pll_audio"};
551 CLK_SPDIF, "spdif", spdif_parents, /* id, name, parents */
553 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake); */
554 0, 4, 0, 0, /* m factor */
557 AW_CLK_HAS_GATE); /* flags */
559 static const char *dram_parents[] = {"pll_ddr", "pll_periph0-2x"};
561 CLK_DRAM, "dram", dram_parents, /* id, name, parents */
563 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
564 0, 4, 0, 0, /* m factor */
567 AW_CLK_HAS_MUX); /* flags */
569 static const char *de_parents[] = {"pll_periph0-2x", "pll_de"};
571 CLK_DE, "de", de_parents, /* id, name, parents */
573 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
574 0, 4, 0, 0, /* m factor */
577 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
579 static const char *tcon0_parents[] = {"pll_video"};
581 CLK_TCON0, "tcon0", tcon0_parents, /* id, name, parents */
583 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
584 0, 4, 0, 0, /* m factor */
587 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
589 static const char *tve_parents[] = {"pll_de", "pll_periph1"};
591 CLK_TVE, "tve", tve_parents, /* id, name, parents */
593 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
594 0, 4, 0, 0, /* m factor */
597 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
599 static const char *deinterlace_parents[] = {"pll_periph0", "pll_periph1"};
600 NM_CLK(deinterlace_clk,
601 CLK_DEINTERLACE, "deinterlace", deinterlace_parents, /* id, name, parents */
603 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
604 0, 4, 0, 0, /* m factor */
607 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
609 static const char *csi_sclk_parents[] = {"pll_periph0", "pll_periph1"};
611 CLK_CSI_SCLK, "csi-sclk", csi_sclk_parents, /* id, name, parents */
613 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
614 16, 4, 0, 0, /* m factor */
617 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
619 static const char *csi_mclk_parents[] = {"osc24M", "pll_video", "pll_periph1"};
621 CLK_CSI_MCLK, "csi-mclk", csi_mclk_parents, /* id, name, parents */
623 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
624 0, 4, 0, 0, /* m factor */
627 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
629 static const char *ve_parents[] = {"pll_ve"};
631 CLK_VE, "ve", ve_parents, /* id, name, parents */
633 16, 3, 0, 0, /* n factor */
634 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */
637 AW_CLK_HAS_GATE); /* flags */
639 static const char *hdmi_parents[] = {"pll_video"};
641 CLK_HDMI, "hdmi", hdmi_parents, /* id, name, parents */
643 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
644 0, 4, 0, 0, /* m factor */
647 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
649 static const char *mbus_parents[] = {"osc24M", "pll_periph0-2x", "pll_ddr"};
651 CLK_MBUS, "mbus", mbus_parents, /* id, name, parents */
653 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */
654 0, 3, 0, 0, /* m factor */
657 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */
659 static const char *gpu_parents[] = {"pll_gpu"};
661 CLK_GPU, "gpu", gpu_parents, /* id, name, parents */
663 0, 2, 0, 0, /* n factor */
664 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */
667 AW_CLK_HAS_GATE); /* flags */
669 static struct aw_clk_nkmp_def *nkmp_clks[] = {
677 static struct aw_clk_nm_def *nm_clks[] = {
705 static struct aw_clk_prediv_mux_def *prediv_mux_clks[] = {
710 static struct clk_mux_def *mux_clks[] = {
717 static struct clk_div_def *div_clks[] = {
723 static struct clk_fixed_def *fixed_factor_clks[] = {
730 static struct aw_clk_init init_clks[] = {
731 {"ahb1", "pll_periph0", 0, false},
732 {"ahb2", "pll_periph0", 0, false},
733 {"dram", "pll_ddr", 0, false},
737 ccu_h3_register_clocks(struct aw_ccung_softc *sc)
741 sc->resets = h3_ccu_resets;
742 sc->nresets = nitems(h3_ccu_resets);
743 sc->gates = h3_ccu_gates;
744 sc->ngates = nitems(h3_ccu_gates);
745 sc->clk_init = init_clks;
746 sc->n_clk_init = nitems(init_clks);
748 for (i = 0; i < nitems(nkmp_clks); i++)
749 aw_clk_nkmp_register(sc->clkdom, nkmp_clks[i]);
750 for (i = 0; i < nitems(nm_clks); i++)
751 aw_clk_nm_register(sc->clkdom, nm_clks[i]);
752 for (i = 0; i < nitems(prediv_mux_clks); i++)
753 aw_clk_prediv_mux_register(sc->clkdom, prediv_mux_clks[i]);
755 for (i = 0; i < nitems(mux_clks); i++)
756 clknode_mux_register(sc->clkdom, mux_clks[i]);
757 for (i = 0; i < nitems(div_clks); i++)
758 clknode_div_register(sc->clkdom, div_clks[i]);
759 for (i = 0; i < nitems(fixed_factor_clks); i++)
760 clknode_fixed_register(sc->clkdom, fixed_factor_clks[i]);