2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2019 Emmanuel Vadot <manu@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
39 #include <machine/bus.h>
41 #include <dev/fdt/simplebus.h>
43 #include <dev/ofw/ofw_bus.h>
44 #include <dev/ofw/ofw_bus_subr.h>
46 #include <dev/extres/clk/clk_div.h>
47 #include <dev/extres/clk/clk_fixed.h>
48 #include <dev/extres/clk/clk_mux.h>
50 #include <arm/allwinner/clkng/aw_ccung.h>
52 #include <dt-bindings/clock/sun50i-h6-ccu.h>
53 #include <dt-bindings/reset/sun50i-h6-ccu.h>
55 /* Non-exported clocks */
57 #define CLK_PLL_CPUX 1
58 #define CLK_PLL_DDR0 2
59 #define CLK_PLL_PERIPH0_2X 4
60 #define CLK_PLL_PERIPH0_4X 5
61 #define CLK_PLL_PERIPH1 6
62 #define CLK_PLL_PERIPH1_2X 7
63 #define CLK_PLL_PERIPH1_4X 8
65 #define CLK_PLL_VIDEO0 10
66 #define CLK_PLL_VIDEO0_4X 11
67 #define CLK_PLL_VIDEO1 12
68 #define CLK_PLL_VIDEO1_4X 13
71 #define CLK_PLL_HSIC 16
73 #define CLK_PSI_AHB1_AHB2 24
77 static struct aw_ccung_reset h6_ccu_resets[] = {
79 CCU_RESET(RST_BUS_PSI, 0x79c, 16)
82 CCU_RESET(RST_BUS_MMC0, 0x84c, 16)
83 CCU_RESET(RST_BUS_MMC1, 0x84c, 17)
84 CCU_RESET(RST_BUS_MMC2, 0x84c, 18)
87 CCU_RESET(RST_BUS_UART0, 0x90c, 16)
88 CCU_RESET(RST_BUS_UART1, 0x90c, 17)
89 CCU_RESET(RST_BUS_UART2, 0x90c, 18)
90 CCU_RESET(RST_BUS_UART3, 0x90c, 19)
93 CCU_RESET(RST_BUS_I2C0, 0x91c, 16)
94 CCU_RESET(RST_BUS_I2C1, 0x91c, 17)
95 CCU_RESET(RST_BUS_I2C2, 0x91c, 18)
96 CCU_RESET(RST_BUS_I2C3, 0x91c, 19)
99 CCU_RESET(RST_BUS_EMAC, 0x97c, 16)
102 CCU_RESET(RST_USB_PHY0, 0xa70, 30)
105 CCU_RESET(RST_USB_PHY1, 0xa74, 30)
108 CCU_RESET(RST_USB_HSIC, 0xa7c, 28)
109 CCU_RESET(RST_USB_PHY3, 0xa7c, 30)
112 CCU_RESET(RST_BUS_OHCI0, 0xa8c, 16)
113 CCU_RESET(RST_BUS_OHCI3, 0xa8c, 19)
114 CCU_RESET(RST_BUS_EHCI0, 0xa8c, 20)
115 CCU_RESET(RST_BUS_XHCI, 0xa8c, 21)
116 CCU_RESET(RST_BUS_EHCI3, 0xa8c, 23)
117 CCU_RESET(RST_BUS_OTG, 0xa8c, 24)
120 static struct aw_ccung_gate h6_ccu_gates[] = {
122 CCU_GATE(CLK_BUS_PSI, "bus-psi", "psi_ahb1_ahb2", 0x79c, 0)
125 CCU_GATE(CLK_BUS_MMC0, "bus-mmc0", "ahb3", 0x84c, 0)
126 CCU_GATE(CLK_BUS_MMC1, "bus-mmc1", "ahb3", 0x84c, 1)
127 CCU_GATE(CLK_BUS_MMC2, "bus-mmc2", "ahb3", 0x84c, 2)
129 /* UART_BGR_REG Enabling the gate enable weir behavior ... */
130 /* CCU_GATE(CLK_BUS_UART0, "bus-uart0", "apb2", 0x90c, 0) */
131 /* CCU_GATE(CLK_BUS_UART1, "bus-uart1", "apb2", 0x90c, 1) */
132 /* CCU_GATE(CLK_BUS_UART2, "bus-uart2", "apb2", 0x90c, 2) */
133 /* CCU_GATE(CLK_BUS_UART3, "bus-uart3", "apb2", 0x90c, 3) */
136 CCU_GATE(CLK_BUS_I2C0, "bus-i2c0", "apb2", 0x91c, 0)
137 CCU_GATE(CLK_BUS_I2C1, "bus-i2c1", "apb2", 0x91c, 1)
138 CCU_GATE(CLK_BUS_I2C2, "bus-i2c2", "apb2", 0x91c, 2)
139 CCU_GATE(CLK_BUS_I2C3, "bus-i2c3", "apb2", 0x91c, 3)
142 CCU_GATE(CLK_BUS_EMAC, "bus-emac", "ahb3", 0x97c, 0)
145 CCU_GATE(CLK_USB_PHY0, "usb-phy0", "ahb3", 0xa70, 29)
146 CCU_GATE(CLK_USB_OHCI0, "usb-ohci0", "ahb3", 0xa70, 31)
149 CCU_GATE(CLK_USB_PHY1, "usb-phy1", "ahb3", 0xa74, 29)
152 CCU_GATE(CLK_USB_HSIC, "usb-hsic", "ahb3", 0xa7c, 26)
153 CCU_GATE(CLK_USB_HSIC_12M, "usb-hsic-12M", "ahb3", 0xa7c, 27)
154 CCU_GATE(CLK_USB_PHY3, "usb-phy3", "ahb3", 0xa7c, 29)
155 CCU_GATE(CLK_USB_OHCI3, "usb-ohci3", "ahb3", 0xa7c, 31)
158 CCU_GATE(CLK_BUS_OHCI0, "bus-ohci0", "ahb3", 0xa8c, 0)
159 CCU_GATE(CLK_BUS_OHCI3, "bus-ohci3", "ahb3", 0xa8c, 3)
160 CCU_GATE(CLK_BUS_EHCI0, "bus-ehci0", "ahb3", 0xa8c, 4)
161 CCU_GATE(CLK_BUS_XHCI, "bus-xhci", "ahb3", 0xa8c, 5)
162 CCU_GATE(CLK_BUS_EHCI3, "bus-ehci3", "ahb3", 0xa8c, 7)
163 CCU_GATE(CLK_BUS_OTG, "bus-otg", "ahb3", 0xa8c, 8)
166 static const char *osc12m_parents[] = {"osc24M"};
167 FIXED_CLK(osc12m_clk,
168 CLK_OSC_12M, /* id */
170 osc12m_parents, /* parent */
176 static const char *pll_cpux_parents[] = {"osc24M"};
178 CLK_PLL_CPUX, /* id */
179 "pll_cpux", pll_cpux_parents, /* name, parents */
181 8, 7, 0, 0, /* n factor */
182 0, 2, 0, 0, /* p factor */
185 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */
187 static const char *pll_ddr0_parents[] = {"osc24M"};
188 NMM_CLK(pll_ddr0_clk,
189 CLK_PLL_DDR0, /* id */
190 "pll_ddr0", pll_ddr0_parents, /* name, parents */
192 8, 7, 0, 0, /* n factor */
193 0, 1, 0, 0, /* m0 factor */
194 1, 1, 0, 0, /* m1 factor */
197 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */
199 static const char *pll_peri0_4x_parents[] = {"osc24M"};
200 NMM_CLK(pll_peri0_4x_clk,
201 CLK_PLL_PERIPH0_4X, /* id */
202 "pll_periph0_4x", pll_peri0_4x_parents, /* name, parents */
204 8, 7, 0, 0, /* n factor */
205 0, 1, 0, 0, /* m0 factor */
206 1, 1, 0, 0, /* m1 factor */
209 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */
210 static const char *pll_peri0_2x_parents[] = {"pll_periph0_4x"};
211 FIXED_CLK(pll_peri0_2x_clk,
212 CLK_PLL_PERIPH0_2X, /* id */
213 "pll_periph0_2x", /* name */
214 pll_peri0_2x_parents, /* parent */
219 static const char *pll_peri0_parents[] = {"pll_periph0_4x"};
220 FIXED_CLK(pll_peri0_clk,
221 CLK_PLL_PERIPH0, /* id */
222 "pll_periph0", /* name */
223 pll_peri0_parents, /* parent */
229 static const char *pll_peri1_4x_parents[] = {"osc24M"};
230 NMM_CLK(pll_peri1_4x_clk,
231 CLK_PLL_PERIPH1_4X, /* id */
232 "pll_periph1_4x", pll_peri1_4x_parents, /* name, parents */
234 8, 7, 0, 0, /* n factor */
235 0, 1, 0, 0, /* m0 factor */
236 1, 1, 0, 0, /* m1 factor */
239 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */
240 static const char *pll_peri1_2x_parents[] = {"pll_periph1_4x"};
241 FIXED_CLK(pll_peri1_2x_clk,
242 CLK_PLL_PERIPH1_2X, /* id */
243 "pll_periph1_2x", /* name */
244 pll_peri1_2x_parents, /* parent */
249 static const char *pll_peri1_parents[] = {"pll_periph1_4x"};
250 FIXED_CLK(pll_peri1_clk,
251 CLK_PLL_PERIPH1, /* id */
252 "pll_periph1", /* name */
253 pll_peri1_parents, /* parent */
259 static const char *pll_gpu_parents[] = {"osc24M"};
261 CLK_PLL_GPU, /* id */
262 "pll_gpu", pll_gpu_parents, /* name, parents */
264 8, 7, 0, 0, /* n factor */
265 0, 1, 0, 0, /* m0 factor */
266 1, 1, 0, 0, /* m1 factor */
269 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */
271 static const char *pll_video0_4x_parents[] = {"osc24M"};
272 NMM_CLK(pll_video0_4x_clk,
273 CLK_PLL_VIDEO0_4X, /* id */
274 "pll_video0_4x", pll_video0_4x_parents, /* name, parents */
276 8, 7, 0, 0, /* n factor */
277 0, 1, 0, 0, /* m0 factor */
278 1, 1, 0, 0, /* m1 factor */
281 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */
282 static const char *pll_video0_parents[] = {"pll_video0_4x"};
283 FIXED_CLK(pll_video0_clk,
284 CLK_PLL_VIDEO0, /* id */
285 "pll_video0", /* name */
286 pll_video0_parents, /* parent */
292 static const char *pll_video1_4x_parents[] = {"osc24M"};
293 NMM_CLK(pll_video1_4x_clk,
294 CLK_PLL_VIDEO1_4X, /* id */
295 "pll_video1_4x", pll_video1_4x_parents, /* name, parents */
297 8, 7, 0, 0, /* n factor */
298 0, 1, 0, 0, /* m0 factor */
299 1, 1, 0, 0, /* m1 factor */
302 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */
303 static const char *pll_video1_parents[] = {"pll_video1_4x"};
304 FIXED_CLK(pll_video1_clk,
305 CLK_PLL_VIDEO1, /* id */
306 "pll_video1", /* name */
307 pll_video1_parents, /* parent */
313 static const char *pll_ve_parents[] = {"osc24M"};
316 "pll_ve", pll_ve_parents, /* name, parents */
318 8, 7, 0, 0, /* n factor */
319 0, 1, 0, 0, /* m0 factor */
320 1, 1, 0, 0, /* m1 factor */
323 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */
325 static const char *pll_de_parents[] = {"osc24M"};
328 "pll_de", pll_de_parents, /* name, parents */
330 8, 7, 0, 0, /* n factor */
331 0, 1, 0, 0, /* m0 factor */
332 1, 1, 0, 0, /* m1 factor */
335 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */
337 static const char *pll_hsic_parents[] = {"osc24M"};
338 NMM_CLK(pll_hsic_clk,
339 CLK_PLL_HSIC, /* id */
340 "pll_hsic", pll_hsic_parents, /* name, parents */
342 8, 7, 0, 0, /* n factor */
343 0, 1, 0, 0, /* m0 factor */
344 1, 1, 0, 0, /* m1 factor */
347 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */
349 /* PLL_AUDIO missing */
351 /* CPUX_AXI missing */
353 static const char *psi_ahb1_ahb2_parents[] = {"osc24M", "osc32k", "iosc", "pll_periph0"};
354 NM_CLK(psi_ahb1_ahb2_clk,
355 CLK_PSI_AHB1_AHB2, "psi_ahb1_ahb2", psi_ahb1_ahb2_parents, /* id, name, parents */
357 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
358 0, 2, 0, 0, /* m factor */
361 AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */
363 static const char *ahb3_parents[] = {"osc24M", "osc32k", "psi_ahb1_ahb2", "pll_periph0"};
365 CLK_AHB3, "ahb3", ahb3_parents, /* id, name, parents */
367 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
368 0, 2, 0, 0, /* m factor */
371 AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */
373 static const char *apb1_parents[] = {"osc24M", "osc32k", "psi_ahb1_ahb2", "pll_periph0"};
375 CLK_APB1, "apb1", apb1_parents, /* id, name, parents */
377 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
378 0, 2, 0, 0, /* m factor */
381 AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */
383 static const char *apb2_parents[] = {"osc24M", "osc32k", "psi_ahb1_ahb2", "pll_periph0"};
385 CLK_APB2, "apb2", apb2_parents, /* id, name, parents */
387 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
388 0, 2, 0, 0, /* m factor */
391 AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */
393 /* Missing MBUS clock */
395 static const char *mod_parents[] = {"osc24M", "pll_periph0_2x", "pll_periph1_2x"};
397 CLK_MMC0, "mmc0", mod_parents, /* id, name, parents */
399 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
400 0, 4, 0, 0, /* m factor */
403 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
404 AW_CLK_REPARENT); /* flags */
407 CLK_MMC1, "mmc1", mod_parents, /* id, name, parents */
409 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
410 0, 4, 0, 0, /* m factor */
413 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
414 AW_CLK_REPARENT); /* flags */
417 CLK_MMC2, "mmc2", mod_parents, /* id, name, parents */
419 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */
420 0, 4, 0, 0, /* m factor */
423 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX |
424 AW_CLK_REPARENT); /* flags */
426 static struct aw_ccung_clk h6_ccu_clks[] = {
427 { .type = AW_CLK_NP, .clk.np = &pll_cpux_clk},
428 { .type = AW_CLK_NMM, .clk.nmm = &pll_ddr0_clk},
429 { .type = AW_CLK_NMM, .clk.nmm = &pll_peri0_4x_clk},
430 { .type = AW_CLK_NMM, .clk.nmm = &pll_peri1_4x_clk},
431 { .type = AW_CLK_NMM, .clk.nmm = &pll_gpu_clk},
432 { .type = AW_CLK_NMM, .clk.nmm = &pll_video0_4x_clk},
433 { .type = AW_CLK_NMM, .clk.nmm = &pll_video1_4x_clk},
434 { .type = AW_CLK_NMM, .clk.nmm = &pll_ve_clk},
435 { .type = AW_CLK_NMM, .clk.nmm = &pll_de_clk},
436 { .type = AW_CLK_NMM, .clk.nmm = &pll_hsic_clk},
438 { .type = AW_CLK_NM, .clk.nm = &psi_ahb1_ahb2_clk},
439 { .type = AW_CLK_NM, .clk.nm = &ahb3_clk},
440 { .type = AW_CLK_NM, .clk.nm = &apb1_clk},
441 { .type = AW_CLK_NM, .clk.nm = &apb2_clk},
443 { .type = AW_CLK_NM, .clk.nm = &mmc0_clk},
444 { .type = AW_CLK_NM, .clk.nm = &mmc1_clk},
445 { .type = AW_CLK_NM, .clk.nm = &mmc2_clk},
447 { .type = AW_CLK_FIXED, .clk.fixed = &osc12m_clk},
448 { .type = AW_CLK_FIXED, .clk.fixed = &pll_peri0_2x_clk},
449 { .type = AW_CLK_FIXED, .clk.fixed = &pll_peri0_clk},
450 { .type = AW_CLK_FIXED, .clk.fixed = &pll_peri1_2x_clk},
451 { .type = AW_CLK_FIXED, .clk.fixed = &pll_peri1_clk},
452 { .type = AW_CLK_FIXED, .clk.fixed = &pll_video0_clk},
453 { .type = AW_CLK_FIXED, .clk.fixed = &pll_video1_clk},
457 ccu_h6_probe(device_t dev)
460 if (!ofw_bus_status_okay(dev))
463 if (!ofw_bus_is_compatible(dev, "allwinner,sun50i-h6-ccu"))
466 device_set_desc(dev, "Allwinner H6 Clock Control Unit NG");
467 return (BUS_PROBE_DEFAULT);
471 ccu_h6_attach(device_t dev)
473 struct aw_ccung_softc *sc;
475 sc = device_get_softc(dev);
477 sc->resets = h6_ccu_resets;
478 sc->nresets = nitems(h6_ccu_resets);
479 sc->gates = h6_ccu_gates;
480 sc->ngates = nitems(h6_ccu_gates);
481 sc->clks = h6_ccu_clks;
482 sc->nclks = nitems(h6_ccu_clks);
484 return (aw_ccung_attach(dev));
487 static device_method_t ccu_h6ng_methods[] = {
488 /* Device interface */
489 DEVMETHOD(device_probe, ccu_h6_probe),
490 DEVMETHOD(device_attach, ccu_h6_attach),
495 DEFINE_CLASS_1(ccu_h6ng, ccu_h6ng_driver, ccu_h6ng_methods,
496 sizeof(struct aw_ccung_softc), aw_ccung_driver);
498 EARLY_DRIVER_MODULE(ccu_h6ng, simplebus, ccu_h6ng_driver, 0, 0,
499 BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);