2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Allwinner Gigabit Ethernet MAC (EMAC) controller
32 #include "opt_device_polling.h"
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include <sys/param.h>
38 #include <sys/systm.h>
41 #include <sys/kernel.h>
42 #include <sys/endian.h>
44 #include <sys/socket.h>
45 #include <sys/sockio.h>
46 #include <sys/module.h>
51 #include <net/ethernet.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
54 #include <net/if_types.h>
55 #include <net/if_var.h>
57 #include <machine/bus.h>
59 #include <dev/ofw/ofw_bus.h>
60 #include <dev/ofw/ofw_bus_subr.h>
62 #include <arm/allwinner/if_awgreg.h>
63 #include <arm/allwinner/aw_sid.h>
64 #include <dev/mii/mii.h>
65 #include <dev/mii/miivar.h>
67 #include <dev/extres/clk/clk.h>
68 #include <dev/extres/hwreset/hwreset.h>
69 #include <dev/extres/regulator/regulator.h>
70 #include <dev/extres/syscon/syscon.h>
72 #include "syscon_if.h"
73 #include "miibus_if.h"
76 #define RD4(sc, reg) bus_read_4((sc)->res[_RES_EMAC], (reg))
77 #define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_EMAC], (reg), (val))
79 #define AWG_LOCK(sc) mtx_lock(&(sc)->mtx)
80 #define AWG_UNLOCK(sc) mtx_unlock(&(sc)->mtx);
81 #define AWG_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
82 #define AWG_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED)
85 #define TX_DESC_COUNT 1024
86 #define TX_DESC_SIZE (sizeof(struct emac_desc) * TX_DESC_COUNT)
87 #define RX_DESC_COUNT 256
88 #define RX_DESC_SIZE (sizeof(struct emac_desc) * RX_DESC_COUNT)
90 #define DESC_OFF(n) ((n) * sizeof(struct emac_desc))
91 #define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1))
92 #define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT - 1))
93 #define RX_NEXT(n) (((n) + 1) & (RX_DESC_COUNT - 1))
95 #define TX_MAX_SEGS 20
97 #define SOFT_RST_RETRY 1000
98 #define MII_BUSY_RETRY 1000
99 #define MDIO_FREQ 2500000
101 #define BURST_LEN_DEFAULT 8
102 #define RX_TX_PRI_DEFAULT 0
103 #define PAUSE_TIME_DEFAULT 0x400
104 #define TX_INTERVAL_DEFAULT 64
105 #define RX_BATCH_DEFAULT 64
107 /* syscon EMAC clock register */
108 #define EMAC_CLK_REG 0x30
109 #define EMAC_CLK_EPHY_ADDR (0x1f << 20) /* H3 */
110 #define EMAC_CLK_EPHY_ADDR_SHIFT 20
111 #define EMAC_CLK_EPHY_LED_POL (1 << 17) /* H3 */
112 #define EMAC_CLK_EPHY_SHUTDOWN (1 << 16) /* H3 */
113 #define EMAC_CLK_EPHY_SELECT (1 << 15) /* H3 */
114 #define EMAC_CLK_RMII_EN (1 << 13)
115 #define EMAC_CLK_ETXDC (0x7 << 10)
116 #define EMAC_CLK_ETXDC_SHIFT 10
117 #define EMAC_CLK_ERXDC (0x1f << 5)
118 #define EMAC_CLK_ERXDC_SHIFT 5
119 #define EMAC_CLK_PIT (0x1 << 2)
120 #define EMAC_CLK_PIT_MII (0 << 2)
121 #define EMAC_CLK_PIT_RGMII (1 << 2)
122 #define EMAC_CLK_SRC (0x3 << 0)
123 #define EMAC_CLK_SRC_MII (0 << 0)
124 #define EMAC_CLK_SRC_EXT_RGMII (1 << 0)
125 #define EMAC_CLK_SRC_RGMII (2 << 0)
127 /* Burst length of RX and TX DMA transfers */
128 static int awg_burst_len = BURST_LEN_DEFAULT;
129 TUNABLE_INT("hw.awg.burst_len", &awg_burst_len);
131 /* RX / TX DMA priority. If 1, RX DMA has priority over TX DMA. */
132 static int awg_rx_tx_pri = RX_TX_PRI_DEFAULT;
133 TUNABLE_INT("hw.awg.rx_tx_pri", &awg_rx_tx_pri);
135 /* Pause time field in the transmitted control frame */
136 static int awg_pause_time = PAUSE_TIME_DEFAULT;
137 TUNABLE_INT("hw.awg.pause_time", &awg_pause_time);
139 /* Request a TX interrupt every <n> descriptors */
140 static int awg_tx_interval = TX_INTERVAL_DEFAULT;
141 TUNABLE_INT("hw.awg.tx_interval", &awg_tx_interval);
143 /* Maximum number of mbufs to send to if_input */
144 static int awg_rx_batch = RX_BATCH_DEFAULT;
145 TUNABLE_INT("hw.awg.rx_batch", &awg_rx_batch);
153 static struct ofw_compat_data compat_data[] = {
154 { "allwinner,sun8i-a83t-emac", EMAC_A83T },
155 { "allwinner,sun8i-h3-emac", EMAC_H3 },
156 { "allwinner,sun50i-a64-emac", EMAC_A64 },
166 bus_dma_tag_t desc_tag;
167 bus_dmamap_t desc_map;
168 struct emac_desc *desc_ring;
169 bus_addr_t desc_ring_paddr;
170 bus_dma_tag_t buf_tag;
171 struct awg_bufmap buf_map[TX_DESC_COUNT];
172 u_int cur, next, queued;
177 bus_dma_tag_t desc_tag;
178 bus_dmamap_t desc_map;
179 struct emac_desc *desc_ring;
180 bus_addr_t desc_ring_paddr;
181 bus_dma_tag_t buf_tag;
182 struct awg_bufmap buf_map[RX_DESC_COUNT];
183 bus_dmamap_t buf_spare_map;
195 struct resource *res[_RES_NITEMS];
200 struct callout stat_ch;
202 u_int mdc_div_ratio_m;
206 struct syscon *syscon;
208 struct awg_txring tx;
209 struct awg_rxring rx;
212 static struct resource_spec awg_spec[] = {
213 { SYS_RES_MEMORY, 0, RF_ACTIVE },
214 { SYS_RES_IRQ, 0, RF_ACTIVE },
215 { SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL },
219 static void awg_txeof(struct awg_softc *sc);
220 static void awg_start_locked(struct awg_softc *sc);
222 static void awg_tick(void *softc);
224 static int awg_parse_delay(device_t dev, uint32_t *tx_delay,
226 static uint32_t syscon_read_emac_clk_reg(device_t dev);
227 static void syscon_write_emac_clk_reg(device_t dev, uint32_t val);
228 static phandle_t awg_get_phy_node(device_t dev);
229 static bool awg_has_internal_phy(device_t dev);
236 awg_miibus_readreg(device_t dev, int phy, int reg)
238 struct awg_softc *sc;
241 sc = device_get_softc(dev);
244 WR4(sc, EMAC_MII_CMD,
245 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) |
246 (phy << PHY_ADDR_SHIFT) |
247 (reg << PHY_REG_ADDR_SHIFT) |
249 for (retry = MII_BUSY_RETRY; retry > 0; retry--) {
250 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) {
251 val = RD4(sc, EMAC_MII_DATA);
258 device_printf(dev, "phy read timeout, phy=%d reg=%d\n",
265 awg_miibus_writereg(device_t dev, int phy, int reg, int val)
267 struct awg_softc *sc;
270 sc = device_get_softc(dev);
272 WR4(sc, EMAC_MII_DATA, val);
273 WR4(sc, EMAC_MII_CMD,
274 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) |
275 (phy << PHY_ADDR_SHIFT) |
276 (reg << PHY_REG_ADDR_SHIFT) |
278 for (retry = MII_BUSY_RETRY; retry > 0; retry--) {
279 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0)
285 device_printf(dev, "phy write timeout, phy=%d reg=%d\n",
292 awg_miibus_statchg(device_t dev)
294 struct awg_softc *sc;
295 struct mii_data *mii;
298 sc = device_get_softc(dev);
300 AWG_ASSERT_LOCKED(sc);
302 if ((if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) == 0)
304 mii = device_get_softc(sc->miibus);
306 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
307 (IFM_ACTIVE | IFM_AVALID)) {
308 switch (IFM_SUBTYPE(mii->mii_media_active)) {
325 val = RD4(sc, EMAC_BASIC_CTL_0);
326 val &= ~(BASIC_CTL_SPEED | BASIC_CTL_DUPLEX);
328 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
329 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
330 val |= BASIC_CTL_SPEED_1000 << BASIC_CTL_SPEED_SHIFT;
331 else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX)
332 val |= BASIC_CTL_SPEED_100 << BASIC_CTL_SPEED_SHIFT;
334 val |= BASIC_CTL_SPEED_10 << BASIC_CTL_SPEED_SHIFT;
336 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
337 val |= BASIC_CTL_DUPLEX;
339 WR4(sc, EMAC_BASIC_CTL_0, val);
341 val = RD4(sc, EMAC_RX_CTL_0);
342 val &= ~RX_FLOW_CTL_EN;
343 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
344 val |= RX_FLOW_CTL_EN;
345 WR4(sc, EMAC_RX_CTL_0, val);
347 val = RD4(sc, EMAC_TX_FLOW_CTL);
348 val &= ~(PAUSE_TIME|TX_FLOW_CTL_EN);
349 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
350 val |= TX_FLOW_CTL_EN;
351 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
352 val |= awg_pause_time << PAUSE_TIME_SHIFT;
353 WR4(sc, EMAC_TX_FLOW_CTL, val);
361 awg_media_status(if_t ifp, struct ifmediareq *ifmr)
363 struct awg_softc *sc;
364 struct mii_data *mii;
366 sc = if_getsoftc(ifp);
367 mii = device_get_softc(sc->miibus);
371 ifmr->ifm_active = mii->mii_media_active;
372 ifmr->ifm_status = mii->mii_media_status;
377 awg_media_change(if_t ifp)
379 struct awg_softc *sc;
380 struct mii_data *mii;
383 sc = if_getsoftc(ifp);
384 mii = device_get_softc(sc->miibus);
387 error = mii_mediachg(mii);
397 /* Bit Reversal - http://aggregate.org/MAGIC/#Bit%20Reversal */
401 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1));
402 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2));
403 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4));
404 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8));
406 return (x >> 16) | (x << 16);
410 awg_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
412 uint32_t crc, hashreg, hashbit, *hash = arg;
414 crc = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN) & 0x7f;
415 crc = bitrev32(~crc) >> 26;
416 hashreg = (crc >> 5);
417 hashbit = (crc & 0x1f);
418 hash[hashreg] |= (1 << hashbit);
424 awg_setup_rxfilter(struct awg_softc *sc)
426 uint32_t val, hash[2], machi, maclo;
430 AWG_ASSERT_LOCKED(sc);
434 hash[0] = hash[1] = 0;
436 if (if_getflags(ifp) & IFF_PROMISC)
437 val |= DIS_ADDR_FILTER;
438 else if (if_getflags(ifp) & IFF_ALLMULTI) {
439 val |= RX_ALL_MULTICAST;
440 hash[0] = hash[1] = ~0;
441 } else if (if_foreach_llmaddr(ifp, awg_hash_maddr, hash) > 0)
442 val |= HASH_MULTICAST;
444 /* Write our unicast address */
445 eaddr = if_getlladdr(ifp);
446 machi = (eaddr[5] << 8) | eaddr[4];
447 maclo = (eaddr[3] << 24) | (eaddr[2] << 16) | (eaddr[1] << 8) |
449 WR4(sc, EMAC_ADDR_HIGH(0), machi);
450 WR4(sc, EMAC_ADDR_LOW(0), maclo);
452 /* Multicast hash filters */
453 WR4(sc, EMAC_RX_HASH_0, hash[1]);
454 WR4(sc, EMAC_RX_HASH_1, hash[0]);
456 /* RX frame filter config */
457 WR4(sc, EMAC_RX_FRM_FLT, val);
461 awg_setup_core(struct awg_softc *sc)
465 AWG_ASSERT_LOCKED(sc);
466 /* Configure DMA burst length and priorities */
467 val = awg_burst_len << BASIC_CTL_BURST_LEN_SHIFT;
469 val |= BASIC_CTL_RX_TX_PRI;
470 WR4(sc, EMAC_BASIC_CTL_1, val);
475 awg_enable_mac(struct awg_softc *sc, bool enable)
479 AWG_ASSERT_LOCKED(sc);
481 tx = RD4(sc, EMAC_TX_CTL_0);
482 rx = RD4(sc, EMAC_RX_CTL_0);
485 rx |= RX_EN | CHECK_CRC;
488 rx &= ~(RX_EN | CHECK_CRC);
491 WR4(sc, EMAC_TX_CTL_0, tx);
492 WR4(sc, EMAC_RX_CTL_0, rx);
496 awg_get_eaddr(device_t dev, uint8_t *eaddr)
498 struct awg_softc *sc;
499 uint32_t maclo, machi, rnd;
501 uint32_t rootkey_size;
503 sc = device_get_softc(dev);
505 machi = RD4(sc, EMAC_ADDR_HIGH(0)) & 0xffff;
506 maclo = RD4(sc, EMAC_ADDR_LOW(0));
508 rootkey_size = sizeof(rootkey);
509 if (maclo == 0xffffffff && machi == 0xffff) {
510 /* MAC address in hardware is invalid, create one */
511 if (aw_sid_get_fuse(AW_SID_FUSE_ROOTKEY, rootkey,
512 &rootkey_size) == 0 &&
513 (rootkey[3] | rootkey[12] | rootkey[13] | rootkey[14] |
515 /* MAC address is derived from the root key in SID */
516 maclo = (rootkey[13] << 24) | (rootkey[12] << 16) |
517 (rootkey[3] << 8) | 0x02;
518 machi = (rootkey[15] << 8) | rootkey[14];
522 maclo = 0x00f2 | (rnd & 0xffff0000);
523 machi = rnd & 0xffff;
527 eaddr[0] = maclo & 0xff;
528 eaddr[1] = (maclo >> 8) & 0xff;
529 eaddr[2] = (maclo >> 16) & 0xff;
530 eaddr[3] = (maclo >> 24) & 0xff;
531 eaddr[4] = machi & 0xff;
532 eaddr[5] = (machi >> 8) & 0xff;
540 awg_enable_dma_intr(struct awg_softc *sc)
542 /* Enable interrupts */
543 WR4(sc, EMAC_INT_EN, RX_INT_EN | TX_INT_EN | TX_BUF_UA_INT_EN);
547 awg_disable_dma_intr(struct awg_softc *sc)
549 /* Disable interrupts */
550 WR4(sc, EMAC_INT_EN, 0);
554 awg_init_dma(struct awg_softc *sc)
558 AWG_ASSERT_LOCKED(sc);
560 /* Enable interrupts */
561 #ifdef DEVICE_POLLING
562 if ((if_getcapenable(sc->ifp) & IFCAP_POLLING) == 0)
563 awg_enable_dma_intr(sc);
565 awg_disable_dma_intr(sc);
567 awg_enable_dma_intr(sc);
570 /* Enable transmit DMA */
571 val = RD4(sc, EMAC_TX_CTL_1);
572 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_EN | TX_MD | TX_NEXT_FRAME);
574 /* Enable receive DMA */
575 val = RD4(sc, EMAC_RX_CTL_1);
576 WR4(sc, EMAC_RX_CTL_1, val | RX_DMA_EN | RX_MD);
580 awg_stop_dma(struct awg_softc *sc)
584 AWG_ASSERT_LOCKED(sc);
586 /* Stop transmit DMA and flush data in the TX FIFO */
587 val = RD4(sc, EMAC_TX_CTL_1);
589 val |= FLUSH_TX_FIFO;
590 WR4(sc, EMAC_TX_CTL_1, val);
592 /* Disable interrupts */
593 awg_disable_dma_intr(sc);
595 /* Disable transmit DMA */
596 val = RD4(sc, EMAC_TX_CTL_1);
597 WR4(sc, EMAC_TX_CTL_1, val & ~TX_DMA_EN);
599 /* Disable receive DMA */
600 val = RD4(sc, EMAC_RX_CTL_1);
601 WR4(sc, EMAC_RX_CTL_1, val & ~RX_DMA_EN);
605 awg_encap(struct awg_softc *sc, struct mbuf **mp)
608 bus_dma_segment_t segs[TX_MAX_SEGS];
609 int error, nsegs, cur, first, last, i;
611 uint32_t flags, status;
614 cur = first = sc->tx.cur;
615 map = sc->tx.buf_map[first].map;
618 error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, map, m, segs,
619 &nsegs, BUS_DMA_NOWAIT);
620 if (error == EFBIG) {
621 m = m_collapse(m, M_NOWAIT, TX_MAX_SEGS);
623 device_printf(sc->dev, "awg_encap: m_collapse failed\n");
629 error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, map, m,
630 segs, &nsegs, BUS_DMA_NOWAIT);
637 device_printf(sc->dev, "awg_encap: bus_dmamap_load_mbuf_sg failed\n");
646 if (sc->tx.queued + nsegs > TX_DESC_COUNT) {
647 bus_dmamap_unload(sc->tx.buf_tag, map);
651 bus_dmamap_sync(sc->tx.buf_tag, map, BUS_DMASYNC_PREWRITE);
655 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) {
656 if ((m->m_pkthdr.csum_flags & (CSUM_TCP|CSUM_UDP)) != 0)
657 csum_flags = TX_CHECKSUM_CTL_FULL;
659 csum_flags = TX_CHECKSUM_CTL_IP;
660 flags |= (csum_flags << TX_CHECKSUM_CTL_SHIFT);
663 for (i = 0; i < nsegs; i++) {
665 if (i == nsegs - 1) {
666 flags |= TX_LAST_DESC;
668 * Can only request TX completion
669 * interrupt on last descriptor.
671 if (sc->tx.segs >= awg_tx_interval) {
677 sc->tx.desc_ring[cur].addr = htole32((uint32_t)segs[i].ds_addr);
678 sc->tx.desc_ring[cur].size = htole32(flags | segs[i].ds_len);
679 sc->tx.desc_ring[cur].status = htole32(status);
681 flags &= ~TX_FIR_DESC;
683 * Setting of the valid bit in the first descriptor is
684 * deferred until the whole chain is fully set up.
686 status = TX_DESC_CTL;
694 /* Store mapping and mbuf in the last segment */
695 last = TX_SKIP(cur, TX_DESC_COUNT - 1);
696 sc->tx.buf_map[first].map = sc->tx.buf_map[last].map;
697 sc->tx.buf_map[last].map = map;
698 sc->tx.buf_map[last].mbuf = m;
701 * The whole mbuf chain has been DMA mapped,
702 * fix the first descriptor.
704 sc->tx.desc_ring[first].status = htole32(TX_DESC_CTL);
710 awg_clean_txbuf(struct awg_softc *sc, int index)
712 struct awg_bufmap *bmap;
716 bmap = &sc->tx.buf_map[index];
717 if (bmap->mbuf != NULL) {
718 bus_dmamap_sync(sc->tx.buf_tag, bmap->map,
719 BUS_DMASYNC_POSTWRITE);
720 bus_dmamap_unload(sc->tx.buf_tag, bmap->map);
727 awg_setup_rxdesc(struct awg_softc *sc, int index, bus_addr_t paddr)
729 uint32_t status, size;
731 status = RX_DESC_CTL;
734 sc->rx.desc_ring[index].addr = htole32((uint32_t)paddr);
735 sc->rx.desc_ring[index].size = htole32(size);
736 sc->rx.desc_ring[index].status = htole32(status);
740 awg_reuse_rxdesc(struct awg_softc *sc, int index)
743 sc->rx.desc_ring[index].status = htole32(RX_DESC_CTL);
747 awg_newbuf_rx(struct awg_softc *sc, int index)
750 bus_dma_segment_t seg;
754 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
758 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
759 m_adj(m, ETHER_ALIGN);
761 if (bus_dmamap_load_mbuf_sg(sc->rx.buf_tag, sc->rx.buf_spare_map,
762 m, &seg, &nsegs, BUS_DMA_NOWAIT) != 0) {
767 if (sc->rx.buf_map[index].mbuf != NULL) {
768 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map,
769 BUS_DMASYNC_POSTREAD);
770 bus_dmamap_unload(sc->rx.buf_tag, sc->rx.buf_map[index].map);
772 map = sc->rx.buf_map[index].map;
773 sc->rx.buf_map[index].map = sc->rx.buf_spare_map;
774 sc->rx.buf_spare_map = map;
775 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map,
776 BUS_DMASYNC_PREREAD);
778 sc->rx.buf_map[index].mbuf = m;
779 awg_setup_rxdesc(sc, index, seg.ds_addr);
785 awg_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
789 *(bus_addr_t *)arg = segs[0].ds_addr;
793 awg_setup_dma(device_t dev)
795 struct awg_softc *sc;
798 sc = device_get_softc(dev);
801 error = bus_dma_tag_create(
802 bus_get_dma_tag(dev), /* Parent tag */
803 DESC_ALIGN, 0, /* alignment, boundary */
804 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
805 BUS_SPACE_MAXADDR, /* highaddr */
806 NULL, NULL, /* filter, filterarg */
807 TX_DESC_SIZE, 1, /* maxsize, nsegs */
808 TX_DESC_SIZE, /* maxsegsize */
810 NULL, NULL, /* lockfunc, lockarg */
813 device_printf(dev, "cannot create TX descriptor ring tag\n");
817 error = bus_dmamem_alloc(sc->tx.desc_tag, (void **)&sc->tx.desc_ring,
818 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->tx.desc_map);
820 device_printf(dev, "cannot allocate TX descriptor ring\n");
824 error = bus_dmamap_load(sc->tx.desc_tag, sc->tx.desc_map,
825 sc->tx.desc_ring, TX_DESC_SIZE, awg_dmamap_cb,
826 &sc->tx.desc_ring_paddr, 0);
828 device_printf(dev, "cannot load TX descriptor ring\n");
832 for (i = 0; i < TX_DESC_COUNT; i++)
833 sc->tx.desc_ring[i].next =
834 htole32(sc->tx.desc_ring_paddr + DESC_OFF(TX_NEXT(i)));
836 error = bus_dma_tag_create(
837 bus_get_dma_tag(dev), /* Parent tag */
838 1, 0, /* alignment, boundary */
839 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
840 BUS_SPACE_MAXADDR, /* highaddr */
841 NULL, NULL, /* filter, filterarg */
842 MCLBYTES, TX_MAX_SEGS, /* maxsize, nsegs */
843 MCLBYTES, /* maxsegsize */
845 NULL, NULL, /* lockfunc, lockarg */
848 device_printf(dev, "cannot create TX buffer tag\n");
853 for (i = 0; i < TX_DESC_COUNT; i++) {
854 error = bus_dmamap_create(sc->tx.buf_tag, 0,
855 &sc->tx.buf_map[i].map);
857 device_printf(dev, "cannot create TX buffer map\n");
863 error = bus_dma_tag_create(
864 bus_get_dma_tag(dev), /* Parent tag */
865 DESC_ALIGN, 0, /* alignment, boundary */
866 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
867 BUS_SPACE_MAXADDR, /* highaddr */
868 NULL, NULL, /* filter, filterarg */
869 RX_DESC_SIZE, 1, /* maxsize, nsegs */
870 RX_DESC_SIZE, /* maxsegsize */
872 NULL, NULL, /* lockfunc, lockarg */
875 device_printf(dev, "cannot create RX descriptor ring tag\n");
879 error = bus_dmamem_alloc(sc->rx.desc_tag, (void **)&sc->rx.desc_ring,
880 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rx.desc_map);
882 device_printf(dev, "cannot allocate RX descriptor ring\n");
886 error = bus_dmamap_load(sc->rx.desc_tag, sc->rx.desc_map,
887 sc->rx.desc_ring, RX_DESC_SIZE, awg_dmamap_cb,
888 &sc->rx.desc_ring_paddr, 0);
890 device_printf(dev, "cannot load RX descriptor ring\n");
894 error = bus_dma_tag_create(
895 bus_get_dma_tag(dev), /* Parent tag */
896 1, 0, /* alignment, boundary */
897 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
898 BUS_SPACE_MAXADDR, /* highaddr */
899 NULL, NULL, /* filter, filterarg */
900 MCLBYTES, 1, /* maxsize, nsegs */
901 MCLBYTES, /* maxsegsize */
903 NULL, NULL, /* lockfunc, lockarg */
906 device_printf(dev, "cannot create RX buffer tag\n");
910 error = bus_dmamap_create(sc->rx.buf_tag, 0, &sc->rx.buf_spare_map);
913 "cannot create RX buffer spare map\n");
917 for (i = 0; i < RX_DESC_COUNT; i++) {
918 sc->rx.desc_ring[i].next =
919 htole32(sc->rx.desc_ring_paddr + DESC_OFF(RX_NEXT(i)));
921 error = bus_dmamap_create(sc->rx.buf_tag, 0,
922 &sc->rx.buf_map[i].map);
924 device_printf(dev, "cannot create RX buffer map\n");
927 sc->rx.buf_map[i].mbuf = NULL;
928 error = awg_newbuf_rx(sc, i);
930 device_printf(dev, "cannot create RX buffer\n");
934 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
935 BUS_DMASYNC_PREWRITE);
937 /* Write transmit and receive descriptor base address registers */
938 WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr);
939 WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr);
945 awg_dma_start_tx(struct awg_softc *sc)
949 AWG_ASSERT_LOCKED(sc);
951 /* Start and run TX DMA */
952 val = RD4(sc, EMAC_TX_CTL_1);
953 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START);
961 awg_start_locked(struct awg_softc *sc)
967 AWG_ASSERT_LOCKED(sc);
974 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) !=
978 for (cnt = 0; ; cnt++) {
983 err = awg_encap(sc, &m);
986 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
988 if_sendq_prepend(ifp, m);
995 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map,
996 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
998 awg_dma_start_tx(sc);
1005 struct awg_softc *sc;
1007 sc = if_getsoftc(ifp);
1010 awg_start_locked(sc);
1015 awg_init_locked(struct awg_softc *sc)
1017 struct mii_data *mii;
1020 mii = device_get_softc(sc->miibus);
1023 AWG_ASSERT_LOCKED(sc);
1025 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1028 awg_setup_rxfilter(sc);
1030 awg_enable_mac(sc, true);
1033 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
1036 callout_reset(&sc->stat_ch, hz, awg_tick, sc);
1040 awg_init(void *softc)
1042 struct awg_softc *sc;
1047 awg_init_locked(sc);
1052 awg_stop(struct awg_softc *sc)
1058 AWG_ASSERT_LOCKED(sc);
1062 callout_stop(&sc->stat_ch);
1065 awg_enable_mac(sc, false);
1069 /* Finish handling transmitted buffers */
1072 /* Release any untransmitted buffers. */
1073 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) {
1074 val = le32toh(sc->tx.desc_ring[i].status);
1075 if ((val & TX_DESC_CTL) != 0)
1077 awg_clean_txbuf(sc, i);
1080 for (; sc->tx.queued > 0; i = TX_NEXT(i)) {
1081 sc->tx.desc_ring[i].status = 0;
1082 awg_clean_txbuf(sc, i);
1084 sc->tx.cur = sc->tx.next;
1085 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map,
1086 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1088 /* Setup RX buffers for reuse */
1089 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
1090 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1092 for (i = sc->rx.cur; ; i = RX_NEXT(i)) {
1093 val = le32toh(sc->rx.desc_ring[i].status);
1094 if ((val & RX_DESC_CTL) != 0)
1096 awg_reuse_rxdesc(sc, i);
1099 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
1100 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1102 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1106 awg_ioctl(if_t ifp, u_long cmd, caddr_t data)
1108 struct awg_softc *sc;
1109 struct mii_data *mii;
1111 int flags, mask, error;
1113 sc = if_getsoftc(ifp);
1114 mii = device_get_softc(sc->miibus);
1115 ifr = (struct ifreq *)data;
1121 if (if_getflags(ifp) & IFF_UP) {
1122 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1123 flags = if_getflags(ifp) ^ sc->if_flags;
1124 if ((flags & (IFF_PROMISC|IFF_ALLMULTI)) != 0)
1125 awg_setup_rxfilter(sc);
1127 awg_init_locked(sc);
1129 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1132 sc->if_flags = if_getflags(ifp);
1137 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1139 awg_setup_rxfilter(sc);
1145 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1148 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1149 #ifdef DEVICE_POLLING
1150 if (mask & IFCAP_POLLING) {
1151 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) {
1152 error = ether_poll_register(awg_poll, ifp);
1156 awg_disable_dma_intr(sc);
1157 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
1160 error = ether_poll_deregister(ifp);
1162 awg_enable_dma_intr(sc);
1163 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
1168 if (mask & IFCAP_VLAN_MTU)
1169 if_togglecapenable(ifp, IFCAP_VLAN_MTU);
1170 if (mask & IFCAP_RXCSUM)
1171 if_togglecapenable(ifp, IFCAP_RXCSUM);
1172 if (mask & IFCAP_TXCSUM)
1173 if_togglecapenable(ifp, IFCAP_TXCSUM);
1174 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
1175 if_sethwassistbits(ifp, CSUM_IP | CSUM_UDP | CSUM_TCP, 0);
1177 if_sethwassistbits(ifp, 0, CSUM_IP | CSUM_UDP | CSUM_TCP);
1180 error = ether_ioctl(ifp, cmd, data);
1188 * Interrupts functions
1192 awg_rxintr(struct awg_softc *sc)
1195 struct mbuf *m, *mh, *mt;
1196 int error, index, len, cnt, npkt;
1204 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
1205 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1207 for (index = sc->rx.cur; ; index = RX_NEXT(index)) {
1208 status = le32toh(sc->rx.desc_ring[index].status);
1209 if ((status & RX_DESC_CTL) != 0)
1212 len = (status & RX_FRM_LEN) >> RX_FRM_LEN_SHIFT;
1215 if ((status & (RX_NO_ENOUGH_BUF_ERR | RX_OVERFLOW_ERR)) != 0)
1216 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1217 awg_reuse_rxdesc(sc, index);
1221 m = sc->rx.buf_map[index].mbuf;
1223 error = awg_newbuf_rx(sc, index);
1225 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1226 awg_reuse_rxdesc(sc, index);
1230 m->m_pkthdr.rcvif = ifp;
1231 m->m_pkthdr.len = len;
1233 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1235 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 &&
1236 (status & RX_FRM_TYPE) != 0) {
1237 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
1238 if ((status & RX_HEADER_ERR) == 0)
1239 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1240 if ((status & RX_PAYLOAD_ERR) == 0) {
1241 m->m_pkthdr.csum_flags |=
1242 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1243 m->m_pkthdr.csum_data = 0xffff;
1247 m->m_nextpkt = NULL;
1256 if (cnt == awg_rx_batch) {
1265 if (index != sc->rx.cur) {
1266 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
1267 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1282 awg_txeof(struct awg_softc *sc)
1284 struct emac_desc *desc;
1285 uint32_t status, size;
1289 AWG_ASSERT_LOCKED(sc);
1291 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map,
1292 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1297 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) {
1298 desc = &sc->tx.desc_ring[i];
1299 status = le32toh(desc->status);
1300 if ((status & TX_DESC_CTL) != 0)
1302 size = le32toh(desc->size);
1303 if (size & TX_LAST_DESC) {
1304 if ((status & (TX_HEADER_ERR | TX_PAYLOAD_ERR)) != 0)
1305 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1307 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1310 awg_clean_txbuf(sc, i);
1315 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1322 struct awg_softc *sc;
1328 val = RD4(sc, EMAC_INT_STA);
1329 WR4(sc, EMAC_INT_STA, val);
1337 if (val & (TX_INT | TX_BUF_UA_INT)) {
1338 if (!if_sendq_empty(sc->ifp))
1339 awg_start_locked(sc);
1345 #ifdef DEVICE_POLLING
1347 awg_poll(if_t ifp, enum poll_cmd cmd, int count)
1349 struct awg_softc *sc;
1353 sc = if_getsoftc(ifp);
1358 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
1363 rx_npkts = awg_rxintr(sc);
1365 if (!if_sendq_empty(ifp))
1366 awg_start_locked(sc);
1368 if (cmd == POLL_AND_CHECK_STATUS) {
1369 val = RD4(sc, EMAC_INT_STA);
1371 WR4(sc, EMAC_INT_STA, val);
1384 syscon_read_emac_clk_reg(device_t dev)
1386 struct awg_softc *sc;
1388 sc = device_get_softc(dev);
1389 if (sc->syscon != NULL)
1390 return (SYSCON_READ_4(sc->syscon, EMAC_CLK_REG));
1391 else if (sc->res[_RES_SYSCON] != NULL)
1392 return (bus_read_4(sc->res[_RES_SYSCON], 0));
1398 syscon_write_emac_clk_reg(device_t dev, uint32_t val)
1400 struct awg_softc *sc;
1402 sc = device_get_softc(dev);
1403 if (sc->syscon != NULL)
1404 SYSCON_WRITE_4(sc->syscon, EMAC_CLK_REG, val);
1405 else if (sc->res[_RES_SYSCON] != NULL)
1406 bus_write_4(sc->res[_RES_SYSCON], 0, val);
1414 awg_get_phy_node(device_t dev)
1419 node = ofw_bus_get_node(dev);
1420 if (OF_getencprop(node, "phy-handle", (void *)&phy_handle,
1421 sizeof(phy_handle)) <= 0)
1424 return (OF_node_from_xref(phy_handle));
1428 awg_has_internal_phy(device_t dev)
1430 phandle_t node, phy_node;
1432 node = ofw_bus_get_node(dev);
1433 /* Legacy binding */
1434 if (OF_hasprop(node, "allwinner,use-internal-phy"))
1437 phy_node = awg_get_phy_node(dev);
1438 return (phy_node != 0 && ofw_bus_node_is_compatible(OF_parent(phy_node),
1439 "allwinner,sun8i-h3-mdio-internal") != 0);
1443 awg_parse_delay(device_t dev, uint32_t *tx_delay, uint32_t *rx_delay)
1448 if (tx_delay == NULL || rx_delay == NULL)
1450 *tx_delay = *rx_delay = 0;
1451 node = ofw_bus_get_node(dev);
1453 if (OF_getencprop(node, "tx-delay", &delay, sizeof(delay)) >= 0)
1455 else if (OF_getencprop(node, "allwinner,tx-delay-ps", &delay,
1456 sizeof(delay)) >= 0) {
1457 if ((delay % 100) != 0) {
1458 device_printf(dev, "tx-delay-ps is not a multiple of 100\n");
1461 *tx_delay = delay / 100;
1463 if (*tx_delay > 7) {
1464 device_printf(dev, "tx-delay out of range\n");
1468 if (OF_getencprop(node, "rx-delay", &delay, sizeof(delay)) >= 0)
1470 else if (OF_getencprop(node, "allwinner,rx-delay-ps", &delay,
1471 sizeof(delay)) >= 0) {
1472 if ((delay % 100) != 0) {
1473 device_printf(dev, "rx-delay-ps is not within documented domain\n");
1476 *rx_delay = delay / 100;
1478 if (*rx_delay > 31) {
1479 device_printf(dev, "rx-delay out of range\n");
1487 awg_setup_phy(device_t dev)
1489 struct awg_softc *sc;
1490 clk_t clk_tx, clk_tx_parent;
1491 const char *tx_parent_name;
1494 uint32_t reg, tx_delay, rx_delay;
1498 sc = device_get_softc(dev);
1499 node = ofw_bus_get_node(dev);
1502 if (OF_getprop_alloc(node, "phy-mode", (void **)&phy_type) == 0)
1505 if (sc->syscon != NULL || sc->res[_RES_SYSCON] != NULL)
1509 device_printf(dev, "PHY type: %s, conf mode: %s\n", phy_type,
1510 use_syscon ? "reg" : "clk");
1514 * Abstract away writing to syscon for devices like the pine64.
1515 * For the pine64, we get dtb from U-Boot and it still uses the
1516 * legacy setup of specifying syscon register in emac node
1517 * rather than as its own node and using an xref in emac.
1518 * These abstractions can go away once U-Boot dts is up-to-date.
1520 reg = syscon_read_emac_clk_reg(dev);
1521 reg &= ~(EMAC_CLK_PIT | EMAC_CLK_SRC | EMAC_CLK_RMII_EN);
1522 if (strncmp(phy_type, "rgmii", 5) == 0)
1523 reg |= EMAC_CLK_PIT_RGMII | EMAC_CLK_SRC_RGMII;
1524 else if (strcmp(phy_type, "rmii") == 0)
1525 reg |= EMAC_CLK_RMII_EN;
1527 reg |= EMAC_CLK_PIT_MII | EMAC_CLK_SRC_MII;
1530 * Fail attach if we fail to parse either of the delay
1531 * parameters. If we don't have the proper delay to write to
1532 * syscon, then awg likely won't function properly anyways.
1533 * Lack of delay is not an error!
1535 error = awg_parse_delay(dev, &tx_delay, &rx_delay);
1539 /* Default to 0 and we'll increase it if we need to. */
1540 reg &= ~(EMAC_CLK_ETXDC | EMAC_CLK_ERXDC);
1542 reg |= (tx_delay << EMAC_CLK_ETXDC_SHIFT);
1544 reg |= (rx_delay << EMAC_CLK_ERXDC_SHIFT);
1546 if (sc->type == EMAC_H3) {
1547 if (awg_has_internal_phy(dev)) {
1548 reg |= EMAC_CLK_EPHY_SELECT;
1549 reg &= ~EMAC_CLK_EPHY_SHUTDOWN;
1550 if (OF_hasprop(node,
1551 "allwinner,leds-active-low"))
1552 reg |= EMAC_CLK_EPHY_LED_POL;
1554 reg &= ~EMAC_CLK_EPHY_LED_POL;
1556 /* Set internal PHY addr to 1 */
1557 reg &= ~EMAC_CLK_EPHY_ADDR;
1558 reg |= (1 << EMAC_CLK_EPHY_ADDR_SHIFT);
1560 reg &= ~EMAC_CLK_EPHY_SELECT;
1565 device_printf(dev, "EMAC clock: 0x%08x\n", reg);
1566 syscon_write_emac_clk_reg(dev, reg);
1568 if (strncmp(phy_type, "rgmii", 5) == 0)
1569 tx_parent_name = "emac_int_tx";
1571 tx_parent_name = "mii_phy_tx";
1573 /* Get the TX clock */
1574 error = clk_get_by_ofw_name(dev, 0, "tx", &clk_tx);
1576 device_printf(dev, "cannot get tx clock\n");
1580 /* Find the desired parent clock based on phy-mode property */
1581 error = clk_get_by_name(dev, tx_parent_name, &clk_tx_parent);
1583 device_printf(dev, "cannot get clock '%s'\n",
1588 /* Set TX clock parent */
1589 error = clk_set_parent_by_clk(clk_tx, clk_tx_parent);
1591 device_printf(dev, "cannot set tx clock parent\n");
1595 /* Enable TX clock */
1596 error = clk_enable(clk_tx);
1598 device_printf(dev, "cannot enable tx clock\n");
1606 OF_prop_free(phy_type);
1611 awg_setup_extres(device_t dev)
1613 struct awg_softc *sc;
1614 phandle_t node, phy_node;
1615 hwreset_t rst_ahb, rst_ephy;
1616 clk_t clk_ahb, clk_ephy;
1621 sc = device_get_softc(dev);
1622 rst_ahb = rst_ephy = NULL;
1623 clk_ahb = clk_ephy = NULL;
1625 node = ofw_bus_get_node(dev);
1626 phy_node = awg_get_phy_node(dev);
1628 if (phy_node == 0 && OF_hasprop(node, "phy-handle")) {
1630 device_printf(dev, "cannot get phy handle\n");
1634 /* Get AHB clock and reset resources */
1635 error = hwreset_get_by_ofw_name(dev, 0, "stmmaceth", &rst_ahb);
1637 error = hwreset_get_by_ofw_name(dev, 0, "ahb", &rst_ahb);
1639 device_printf(dev, "cannot get ahb reset\n");
1642 if (hwreset_get_by_ofw_name(dev, 0, "ephy", &rst_ephy) != 0)
1643 if (phy_node == 0 || hwreset_get_by_ofw_idx(dev, phy_node, 0,
1646 error = clk_get_by_ofw_name(dev, 0, "stmmaceth", &clk_ahb);
1648 error = clk_get_by_ofw_name(dev, 0, "ahb", &clk_ahb);
1650 device_printf(dev, "cannot get ahb clock\n");
1653 if (clk_get_by_ofw_name(dev, 0, "ephy", &clk_ephy) != 0)
1654 if (phy_node == 0 || clk_get_by_ofw_index(dev, phy_node, 0,
1658 if (OF_hasprop(node, "syscon") && syscon_get_by_ofw_property(dev, node,
1659 "syscon", &sc->syscon) != 0) {
1660 device_printf(dev, "cannot get syscon driver handle\n");
1664 /* Configure PHY for MII or RGMII mode */
1665 if (awg_setup_phy(dev) != 0)
1669 error = clk_enable(clk_ahb);
1671 device_printf(dev, "cannot enable ahb clock\n");
1674 if (clk_ephy != NULL) {
1675 error = clk_enable(clk_ephy);
1677 device_printf(dev, "cannot enable ephy clock\n");
1682 /* De-assert reset */
1683 error = hwreset_deassert(rst_ahb);
1685 device_printf(dev, "cannot de-assert ahb reset\n");
1688 if (rst_ephy != NULL) {
1690 * The ephy reset is left de-asserted by U-Boot. Assert it
1691 * here to make sure that we're in a known good state going
1692 * into the PHY reset.
1694 hwreset_assert(rst_ephy);
1695 error = hwreset_deassert(rst_ephy);
1697 device_printf(dev, "cannot de-assert ephy reset\n");
1702 /* Enable PHY regulator if applicable */
1703 if (regulator_get_by_ofw_property(dev, 0, "phy-supply", ®) == 0) {
1704 error = regulator_enable(reg);
1706 device_printf(dev, "cannot enable PHY regulator\n");
1711 /* Determine MDC clock divide ratio based on AHB clock */
1712 error = clk_get_freq(clk_ahb, &freq);
1714 device_printf(dev, "cannot get AHB clock frequency\n");
1717 div = freq / MDIO_FREQ;
1719 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_16;
1721 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_32;
1723 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_64;
1724 else if (div <= 128)
1725 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_128;
1727 device_printf(dev, "cannot determine MDC clock divide ratio\n");
1733 device_printf(dev, "AHB frequency %ju Hz, MDC div: 0x%x\n",
1734 (uintmax_t)freq, sc->mdc_div_ratio_m);
1740 regulator_release(reg);
1741 if (clk_ephy != NULL)
1742 clk_release(clk_ephy);
1743 if (clk_ahb != NULL)
1744 clk_release(clk_ahb);
1745 if (rst_ephy != NULL)
1746 hwreset_release(rst_ephy);
1747 if (rst_ahb != NULL)
1748 hwreset_release(rst_ahb);
1754 awg_dump_regs(device_t dev)
1756 static const struct {
1760 { "BASIC_CTL_0", EMAC_BASIC_CTL_0 },
1761 { "BASIC_CTL_1", EMAC_BASIC_CTL_1 },
1762 { "INT_STA", EMAC_INT_STA },
1763 { "INT_EN", EMAC_INT_EN },
1764 { "TX_CTL_0", EMAC_TX_CTL_0 },
1765 { "TX_CTL_1", EMAC_TX_CTL_1 },
1766 { "TX_FLOW_CTL", EMAC_TX_FLOW_CTL },
1767 { "TX_DMA_LIST", EMAC_TX_DMA_LIST },
1768 { "RX_CTL_0", EMAC_RX_CTL_0 },
1769 { "RX_CTL_1", EMAC_RX_CTL_1 },
1770 { "RX_DMA_LIST", EMAC_RX_DMA_LIST },
1771 { "RX_FRM_FLT", EMAC_RX_FRM_FLT },
1772 { "RX_HASH_0", EMAC_RX_HASH_0 },
1773 { "RX_HASH_1", EMAC_RX_HASH_1 },
1774 { "MII_CMD", EMAC_MII_CMD },
1775 { "ADDR_HIGH0", EMAC_ADDR_HIGH(0) },
1776 { "ADDR_LOW0", EMAC_ADDR_LOW(0) },
1777 { "TX_DMA_STA", EMAC_TX_DMA_STA },
1778 { "TX_DMA_CUR_DESC", EMAC_TX_DMA_CUR_DESC },
1779 { "TX_DMA_CUR_BUF", EMAC_TX_DMA_CUR_BUF },
1780 { "RX_DMA_STA", EMAC_RX_DMA_STA },
1781 { "RX_DMA_CUR_DESC", EMAC_RX_DMA_CUR_DESC },
1782 { "RX_DMA_CUR_BUF", EMAC_RX_DMA_CUR_BUF },
1783 { "RGMII_STA", EMAC_RGMII_STA },
1785 struct awg_softc *sc;
1788 sc = device_get_softc(dev);
1790 for (n = 0; n < nitems(regs); n++)
1791 device_printf(dev, " %-20s %08x\n", regs[n].name,
1792 RD4(sc, regs[n].reg));
1796 #define GPIO_ACTIVE_LOW 1
1799 awg_phy_reset(device_t dev)
1801 pcell_t gpio_prop[4], delay_prop[3];
1802 phandle_t node, gpio_node;
1804 uint32_t pin, flags;
1807 node = ofw_bus_get_node(dev);
1808 if (OF_getencprop(node, "allwinner,reset-gpio", gpio_prop,
1809 sizeof(gpio_prop)) <= 0)
1812 if (OF_getencprop(node, "allwinner,reset-delays-us", delay_prop,
1813 sizeof(delay_prop)) <= 0)
1816 gpio_node = OF_node_from_xref(gpio_prop[0]);
1817 if ((gpio = OF_device_from_xref(gpio_prop[0])) == NULL)
1820 if (GPIO_MAP_GPIOS(gpio, node, gpio_node, nitems(gpio_prop) - 1,
1821 gpio_prop + 1, &pin, &flags) != 0)
1824 pin_value = GPIO_PIN_LOW;
1825 if (OF_hasprop(node, "allwinner,reset-active-low"))
1826 pin_value = GPIO_PIN_HIGH;
1828 if (flags & GPIO_ACTIVE_LOW)
1829 pin_value = !pin_value;
1831 GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT);
1832 GPIO_PIN_SET(gpio, pin, pin_value);
1833 DELAY(delay_prop[0]);
1834 GPIO_PIN_SET(gpio, pin, !pin_value);
1835 DELAY(delay_prop[1]);
1836 GPIO_PIN_SET(gpio, pin, pin_value);
1837 DELAY(delay_prop[2]);
1843 awg_reset(device_t dev)
1845 struct awg_softc *sc;
1848 sc = device_get_softc(dev);
1850 /* Reset PHY if necessary */
1851 if (awg_phy_reset(dev) != 0) {
1852 device_printf(dev, "failed to reset PHY\n");
1856 /* Soft reset all registers and logic */
1857 WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST);
1859 /* Wait for soft reset bit to self-clear */
1860 for (retry = SOFT_RST_RETRY; retry > 0; retry--) {
1861 if ((RD4(sc, EMAC_BASIC_CTL_1) & BASIC_CTL_SOFT_RST) == 0)
1866 device_printf(dev, "soft reset timed out\n");
1881 awg_tick(void *softc)
1883 struct awg_softc *sc;
1884 struct mii_data *mii;
1890 mii = device_get_softc(sc->miibus);
1892 AWG_ASSERT_LOCKED(sc);
1894 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
1899 if (sc->link && !link)
1900 awg_start_locked(sc);
1902 callout_reset(&sc->stat_ch, hz, awg_tick, sc);
1906 * Probe/attach functions
1910 awg_probe(device_t dev)
1912 if (!ofw_bus_status_okay(dev))
1915 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
1918 device_set_desc(dev, "Allwinner Gigabit Ethernet");
1919 return (BUS_PROBE_DEFAULT);
1923 awg_attach(device_t dev)
1925 uint8_t eaddr[ETHER_ADDR_LEN];
1926 struct awg_softc *sc;
1929 sc = device_get_softc(dev);
1931 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
1933 if (bus_alloc_resources(dev, awg_spec, sc->res) != 0) {
1934 device_printf(dev, "cannot allocate resources for device\n");
1938 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF);
1939 callout_init_mtx(&sc->stat_ch, &sc->mtx, 0);
1941 /* Setup clocks and regulators */
1942 error = awg_setup_extres(dev);
1946 /* Read MAC address before resetting the chip */
1947 awg_get_eaddr(dev, eaddr);
1949 /* Soft reset EMAC core */
1950 error = awg_reset(dev);
1954 /* Setup DMA descriptors */
1955 error = awg_setup_dma(dev);
1959 /* Install interrupt handler */
1960 error = bus_setup_intr(dev, sc->res[_RES_IRQ],
1961 INTR_TYPE_NET | INTR_MPSAFE, NULL, awg_intr, sc, &sc->ih);
1963 device_printf(dev, "cannot setup interrupt handler\n");
1967 /* Setup ethernet interface */
1968 sc->ifp = if_alloc(IFT_ETHER);
1969 if_setsoftc(sc->ifp, sc);
1970 if_initname(sc->ifp, device_get_name(dev), device_get_unit(dev));
1971 if_setflags(sc->ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
1972 if_setstartfn(sc->ifp, awg_start);
1973 if_setioctlfn(sc->ifp, awg_ioctl);
1974 if_setinitfn(sc->ifp, awg_init);
1975 if_setsendqlen(sc->ifp, TX_DESC_COUNT - 1);
1976 if_setsendqready(sc->ifp);
1977 if_sethwassist(sc->ifp, CSUM_IP | CSUM_UDP | CSUM_TCP);
1978 if_setcapabilities(sc->ifp, IFCAP_VLAN_MTU | IFCAP_HWCSUM);
1979 if_setcapenable(sc->ifp, if_getcapabilities(sc->ifp));
1980 #ifdef DEVICE_POLLING
1981 if_setcapabilitiesbit(sc->ifp, IFCAP_POLLING, 0);
1984 /* Attach MII driver */
1985 error = mii_attach(dev, &sc->miibus, sc->ifp, awg_media_change,
1986 awg_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
1989 device_printf(dev, "cannot attach PHY\n");
1993 /* Attach ethernet interface */
1994 ether_ifattach(sc->ifp, eaddr);
1999 static device_method_t awg_methods[] = {
2000 /* Device interface */
2001 DEVMETHOD(device_probe, awg_probe),
2002 DEVMETHOD(device_attach, awg_attach),
2005 DEVMETHOD(miibus_readreg, awg_miibus_readreg),
2006 DEVMETHOD(miibus_writereg, awg_miibus_writereg),
2007 DEVMETHOD(miibus_statchg, awg_miibus_statchg),
2012 static driver_t awg_driver = {
2015 sizeof(struct awg_softc),
2018 DRIVER_MODULE(awg, simplebus, awg_driver, 0, 0);
2019 DRIVER_MODULE(miibus, awg, miibus_driver, 0, 0);
2020 MODULE_DEPEND(awg, ether, 1, 1, 1);
2021 MODULE_DEPEND(awg, miibus, 1, 1, 1);
2022 MODULE_DEPEND(awg, aw_sid, 1, 1, 1);
2023 SIMPLEBUS_PNP_INFO(compat_data);