2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Allwinner Gigabit Ethernet
33 #ifndef __IF_AWGREG_H__
34 #define __IF_AWGREG_H__
36 #define EMAC_BASIC_CTL_0 0x00
37 #define BASIC_CTL_SPEED (0x3 << 2)
38 #define BASIC_CTL_SPEED_SHIFT 2
39 #define BASIC_CTL_SPEED_1000 0
40 #define BASIC_CTL_SPEED_10 2
41 #define BASIC_CTL_SPEED_100 3
42 #define BASIC_CTL_LOOPBACK (1 << 1)
43 #define BASIC_CTL_DUPLEX (1 << 0)
44 #define EMAC_BASIC_CTL_1 0x04
45 #define BASIC_CTL_BURST_LEN (0x3f << 24)
46 #define BASIC_CTL_BURST_LEN_SHIFT 24
47 #define BASIC_CTL_RX_TX_PRI (1 << 1)
48 #define BASIC_CTL_SOFT_RST (1 << 0)
49 #define EMAC_INT_STA 0x08
50 #define RX_BUF_UA_INT (1 << 10)
51 #define RX_INT (1 << 8)
52 #define TX_UNDERFLOW_INT (1 << 4)
53 #define TX_BUF_UA_INT (1 << 2)
54 #define TX_DMA_STOPPED_INT (1 << 1)
55 #define TX_INT (1 << 0)
56 #define EMAC_INT_EN 0x0c
57 #define RX_BUF_UA_INT_EN (1 << 10)
58 #define RX_INT_EN (1 << 8)
59 #define TX_UNDERFLOW_INT_EN (1 << 4)
60 #define TX_BUF_UA_INT_EN (1 << 2)
61 #define TX_DMA_STOPPED_INT_EN (1 << 1)
62 #define TX_INT_EN (1 << 0)
63 #define EMAC_TX_CTL_0 0x10
64 #define TX_EN (1 << 31)
65 #define EMAC_TX_CTL_1 0x14
66 #define TX_DMA_START (1 << 31)
67 #define TX_DMA_EN (1 << 30)
68 #define TX_NEXT_FRAME (1 << 2)
69 #define TX_MD (1 << 1)
70 #define FLUSH_TX_FIFO (1 << 0)
71 #define EMAC_TX_FLOW_CTL 0x1c
72 #define PAUSE_TIME (0xffff << 4)
73 #define PAUSE_TIME_SHIFT 4
74 #define TX_FLOW_CTL_EN (1 << 0)
75 #define EMAC_TX_DMA_LIST 0x20
76 #define EMAC_RX_CTL_0 0x24
77 #define RX_EN (1 << 31)
78 #define JUMBO_FRM_EN (1 << 29)
79 #define STRIP_FCS (1 << 28)
80 #define CHECK_CRC (1 << 27)
81 #define RX_FLOW_CTL_EN (1 << 16)
82 #define EMAC_RX_CTL_1 0x28
83 #define RX_DMA_START (1 << 31)
84 #define RX_DMA_EN (1 << 30)
85 #define RX_MD (1 << 1)
86 #define EMAC_RX_DMA_LIST 0x34
87 #define EMAC_RX_FRM_FLT 0x38
88 #define DIS_ADDR_FILTER (1 << 31)
89 #define DIS_BROADCAST (1 << 17)
90 #define RX_ALL_MULTICAST (1 << 16)
91 #define CTL_FRM_FILTER (0x3 << 12)
92 #define CTL_FRM_FILTER_SHIFT 12
93 #define HASH_MULTICAST (1 << 9)
94 #define HASH_UNICAST (1 << 8)
95 #define SA_FILTER_EN (1 << 6)
96 #define SA_INV_FILTER (1 << 5)
97 #define DA_INV_FILTER (1 << 4)
98 #define FLT_MD (1 << 1)
99 #define RX_ALL (1 << 0)
100 #define EMAC_RX_HASH_0 0x40
101 #define EMAC_RX_HASH_1 0x44
102 #define EMAC_MII_CMD 0x48
103 #define MDC_DIV_RATIO_M (0x7 << 20)
104 #define MDC_DIV_RATIO_M_16 0
105 #define MDC_DIV_RATIO_M_32 1
106 #define MDC_DIV_RATIO_M_64 2
107 #define MDC_DIV_RATIO_M_128 3
108 #define MDC_DIV_RATIO_M_SHIFT 20
109 #define PHY_ADDR (0x1f << 12)
110 #define PHY_ADDR_SHIFT 12
111 #define PHY_REG_ADDR (0x1f << 4)
112 #define PHY_REG_ADDR_SHIFT 4
113 #define MII_WR (1 << 1)
114 #define MII_BUSY (1 << 0)
115 #define EMAC_MII_DATA 0x4c
116 #define EMAC_ADDR_HIGH(n) (0x50 + (n) * 8)
117 #define EMAC_ADDR_LOW(n) (0x54 + (n) * 8)
118 #define EMAC_TX_DMA_STA 0xb0
119 #define EMAC_TX_DMA_CUR_DESC 0xb4
120 #define EMAC_TX_DMA_CUR_BUF 0xb8
121 #define EMAC_RX_DMA_STA 0xc0
122 #define EMAC_RX_DMA_CUR_DESC 0xc4
123 #define EMAC_RX_DMA_CUR_BUF 0xc8
124 #define EMAC_RGMII_STA 0xd0
129 #define TX_DESC_CTL (1 << 31)
130 #define TX_HEADER_ERR (1 << 16)
131 #define TX_LENGTH_ERR (1 << 14)
132 #define TX_PAYLOAD_ERR (1 << 12)
133 #define TX_CRS_ERR (1 << 10)
134 #define TX_COL_ERR_0 (1 << 9)
135 #define TX_COL_ERR_1 (1 << 8)
136 #define TX_COL_CNT (0xf << 3)
137 #define TX_COL_CNT_SHIFT 3
138 #define TX_DEFER_ERR (1 << 2)
139 #define TX_UNDERFLOW_ERR (1 << 1)
140 #define TX_DEFER (1 << 0)
142 #define RX_DESC_CTL (1 << 31)
143 #define RX_DAF_FAIL (1 << 30)
144 #define RX_FRM_LEN (0x3fff << 16)
145 #define RX_FRM_LEN_SHIFT 16
146 #define RX_NO_ENOUGH_BUF_ERR (1 << 14)
147 #define RX_SAF_FAIL (1 << 13)
148 #define RX_OVERFLOW_ERR (1 << 11)
149 #define RX_FIR_DESC (1 << 9)
150 #define RX_LAST_DESC (1 << 8)
151 #define RX_HEADER_ERR (1 << 7)
152 #define RX_COL_ERR (1 << 6)
153 #define RX_FRM_TYPE (1 << 5)
154 #define RX_LENGTH_ERR (1 << 4)
155 #define RX_PHY_ERR (1 << 3)
156 #define RX_CRC_ERR (1 << 1)
157 #define RX_PAYLOAD_ERR (1 << 0)
161 #define TX_INT_CTL (1 << 31)
162 #define TX_LAST_DESC (1 << 30)
163 #define TX_FIR_DESC (1 << 29)
164 #define TX_CHECKSUM_CTL (0x3 << 27)
165 #define TX_CHECKSUM_CTL_IP 1
166 #define TX_CHECKSUM_CTL_NO_PSE 2
167 #define TX_CHECKSUM_CTL_FULL 3
168 #define TX_CHECKSUM_CTL_SHIFT 27
169 #define TX_CRC_CTL (1 << 26)
170 #define TX_BUF_SIZE (0xfff << 0)
171 #define TX_BUF_SIZE_SHIFT 0
173 #define RX_INT_CTL (1 << 31)
174 #define RX_BUF_SIZE (0xfff << 0)
175 #define RX_BUF_SIZE_SHIFT 0
182 #endif /* !__IF_AWGREG_H__ */