2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 /* A10/A20 EMAC driver */
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
43 #include <sys/mutex.h>
45 #include <sys/socket.h>
46 #include <sys/sockio.h>
47 #include <sys/sysctl.h>
50 #include <machine/bus.h>
51 #include <machine/resource.h>
52 #include <machine/intr.h>
55 #include <net/if_var.h>
56 #include <net/if_arp.h>
57 #include <net/if_dl.h>
58 #include <net/if_media.h>
59 #include <net/if_types.h>
60 #include <net/if_mib.h>
61 #include <net/ethernet.h>
62 #include <net/if_vlan_var.h>
65 #include <netinet/in.h>
66 #include <netinet/in_systm.h>
67 #include <netinet/in_var.h>
68 #include <netinet/ip.h>
72 #include <net/bpfdesc.h>
74 #include <dev/ofw/ofw_bus.h>
75 #include <dev/ofw/ofw_bus_subr.h>
77 #include <dev/mii/mii.h>
78 #include <dev/mii/miivar.h>
80 #include <arm/allwinner/if_emacreg.h>
81 #include <arm/allwinner/aw_sid.h>
83 #include <dev/extres/clk/clk.h>
85 #include "miibus_if.h"
89 #include "a10_sramc.h"
92 struct ifnet *emac_ifp;
95 bus_space_handle_t emac_handle;
96 bus_space_tag_t emac_tag;
97 struct resource *emac_res;
98 struct resource *emac_irq;
103 struct callout emac_tick_ch;
104 int emac_watchdog_timer;
105 int emac_rx_process_limit;
107 uint32_t emac_fifo_mask;
110 static int emac_probe(device_t);
111 static int emac_attach(device_t);
112 static int emac_detach(device_t);
113 static int emac_shutdown(device_t);
114 static int emac_suspend(device_t);
115 static int emac_resume(device_t);
117 static int emac_sys_setup(struct emac_softc *);
118 static void emac_reset(struct emac_softc *);
120 static void emac_init_locked(struct emac_softc *);
121 static void emac_start_locked(struct ifnet *);
122 static void emac_init(void *);
123 static void emac_stop_locked(struct emac_softc *);
124 static void emac_intr(void *);
125 static int emac_ioctl(struct ifnet *, u_long, caddr_t);
127 static void emac_rxeof(struct emac_softc *, int);
128 static void emac_txeof(struct emac_softc *, uint32_t);
130 static int emac_miibus_readreg(device_t, int, int);
131 static int emac_miibus_writereg(device_t, int, int, int);
132 static void emac_miibus_statchg(device_t);
134 static int emac_ifmedia_upd(struct ifnet *);
135 static void emac_ifmedia_sts(struct ifnet *, struct ifmediareq *);
137 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
138 static int sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS);
140 #define EMAC_READ_REG(sc, reg) \
141 bus_space_read_4(sc->emac_tag, sc->emac_handle, reg)
142 #define EMAC_WRITE_REG(sc, reg, val) \
143 bus_space_write_4(sc->emac_tag, sc->emac_handle, reg, val)
146 emac_sys_setup(struct emac_softc *sc)
150 /* Activate EMAC clock. */
151 error = clk_get_by_ofw_index(sc->emac_dev, 0, 0, &sc->emac_clk);
153 device_printf(sc->emac_dev, "cannot get clock\n");
156 error = clk_enable(sc->emac_clk);
158 device_printf(sc->emac_dev, "cannot enable clock\n");
169 emac_get_hwaddr(struct emac_softc *sc, uint8_t *hwaddr)
171 uint32_t val0, val1, rnd;
176 * Try to get MAC address from running hardware.
177 * If there is something non-zero there just use it.
179 * Otherwise set the address to a convenient locally assigned address,
180 * using the SID rootkey.
181 * This is was uboot does so we end up with the same mac as if uboot
183 * If we can't get the root key, generate a random one,
184 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally
185 * assigned bit set, and the broadcast/multicast bit clear.
187 val0 = EMAC_READ_REG(sc, EMAC_MAC_A0);
188 val1 = EMAC_READ_REG(sc, EMAC_MAC_A1);
189 if ((val0 | val1) != 0 && (val0 | val1) != 0xffffff) {
190 hwaddr[0] = (val1 >> 16) & 0xff;
191 hwaddr[1] = (val1 >> 8) & 0xff;
192 hwaddr[2] = (val1 >> 0) & 0xff;
193 hwaddr[3] = (val0 >> 16) & 0xff;
194 hwaddr[4] = (val0 >> 8) & 0xff;
195 hwaddr[5] = (val0 >> 0) & 0xff;
197 rootkey_size = sizeof(rootkey);
198 if (aw_sid_get_fuse(AW_SID_FUSE_ROOTKEY, rootkey,
199 &rootkey_size) == 0) {
201 hwaddr[1] = rootkey[3];
202 hwaddr[2] = rootkey[12];
203 hwaddr[3] = rootkey[13];
204 hwaddr[4] = rootkey[14];
205 hwaddr[5] = rootkey[15];
208 rnd = arc4random() & 0x00ffffff;
212 hwaddr[3] = (rnd >> 16) & 0xff;
213 hwaddr[4] = (rnd >> 8) & 0xff;
214 hwaddr[5] = (rnd >> 0) & 0xff;
218 printf("MAC address: %s\n", ether_sprintf(hwaddr));
222 emac_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
224 uint32_t h, *hashes = arg;
226 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
227 hashes[h >> 5] |= 1 << (h & 0x1f);
233 emac_set_rx_mode(struct emac_softc *sc)
239 EMAC_ASSERT_LOCKED(sc);
243 rcr = EMAC_READ_REG(sc, EMAC_RX_CTL);
245 /* Unicast packet and DA filtering */
251 if (ifp->if_flags & IFF_ALLMULTI) {
252 hashes[0] = 0xffffffff;
253 hashes[1] = 0xffffffff;
255 if_foreach_llmaddr(ifp, emac_hash_maddr, hashes);
258 EMAC_WRITE_REG(sc, EMAC_RX_HASH0, hashes[0]);
259 EMAC_WRITE_REG(sc, EMAC_RX_HASH1, hashes[1]);
261 if (ifp->if_flags & IFF_BROADCAST) {
266 if (ifp->if_flags & IFF_PROMISC)
271 EMAC_WRITE_REG(sc, EMAC_RX_CTL, rcr);
275 emac_reset(struct emac_softc *sc)
278 EMAC_WRITE_REG(sc, EMAC_CTL, 0);
280 EMAC_WRITE_REG(sc, EMAC_CTL, 1);
285 emac_drain_rxfifo(struct emac_softc *sc)
289 while (EMAC_READ_REG(sc, EMAC_RX_FBC) > 0)
290 data = EMAC_READ_REG(sc, EMAC_RX_IO_DATA);
294 emac_txeof(struct emac_softc *sc, uint32_t status)
298 EMAC_ASSERT_LOCKED(sc);
301 status &= (EMAC_TX_FIFO0 | EMAC_TX_FIFO1);
302 sc->emac_fifo_mask &= ~status;
303 if (status == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1))
304 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 2);
306 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
307 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
309 /* Unarm watchdog timer if no TX */
310 sc->emac_watchdog_timer = 0;
314 emac_rxeof(struct emac_softc *sc, int count)
318 uint32_t reg_val, rxcount;
325 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; count--) {
327 * Race warning: The first packet might arrive with
328 * the interrupts disabled, but the second will fix
330 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC);
333 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC);
337 /* Check packet header */
338 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA);
339 if (reg_val != EMAC_PACKET_HEADER) {
340 /* Packet header is wrong */
342 if_printf(ifp, "wrong packet header\n");
344 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
345 reg_val &= ~EMAC_CTL_RX_EN;
346 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
349 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL);
350 reg_val |= EMAC_RX_FLUSH_FIFO;
351 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
352 for (i = 100; i > 0; i--) {
354 if ((EMAC_READ_REG(sc, EMAC_RX_CTL) &
355 EMAC_RX_FLUSH_FIFO) == 0)
359 device_printf(sc->emac_dev,
360 "flush FIFO timeout\n");
361 /* Reinitialize controller */
362 emac_init_locked(sc);
366 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
367 reg_val |= EMAC_CTL_RX_EN;
368 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
373 /* Get packet size and status */
374 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA);
375 len = reg_val & 0xffff;
376 status = (reg_val >> 16) & 0xffff;
378 if (len < 64 || (status & EMAC_PKT_OK) == 0) {
381 "bad packet: len = %i status = %i\n",
383 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
384 emac_drain_rxfifo(sc);
388 if (status & (EMAC_CRCERR | EMAC_LENERR)) {
390 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
391 if (status & EMAC_CRCERR)
392 if_printf(ifp, "crc error\n");
393 if (status & EMAC_LENERR)
394 if_printf(ifp, "length error\n");
397 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
399 emac_drain_rxfifo(sc);
402 m->m_len = m->m_pkthdr.len = MCLBYTES;
404 /* Copy entire frame to mbuf first. */
405 bus_space_read_multi_4(sc->emac_tag, sc->emac_handle,
406 EMAC_RX_IO_DATA, mtod(m, uint32_t *), roundup2(len, 4) / 4);
408 m->m_pkthdr.rcvif = ifp;
409 m->m_len = m->m_pkthdr.len = len - ETHER_CRC_LEN;
412 * Emac controller needs strict aligment, so to avoid
413 * copying over an entire frame to align, we allocate
414 * a new mbuf and copy ethernet header + IP header to
415 * the new mbuf. The new mbuf is prepended into the
416 * existing mbuf chain.
418 if (m->m_len <= (MHLEN - ETHER_HDR_LEN)) {
419 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
420 m->m_data += ETHER_HDR_LEN;
421 } else if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN) &&
422 m->m_len > (MHLEN - ETHER_HDR_LEN)) {
423 MGETHDR(m0, M_NOWAIT, MT_DATA);
425 len = ETHER_HDR_LEN + m->m_pkthdr.l2hlen;
426 bcopy(m->m_data, m0->m_data, len);
430 M_MOVE_PKTHDR(m0, m);
434 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
439 } else if (m->m_len > EMAC_MAC_MAXF) {
440 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
445 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
447 (*ifp->if_input)(ifp, m);
453 emac_watchdog(struct emac_softc *sc)
457 EMAC_ASSERT_LOCKED(sc);
459 if (sc->emac_watchdog_timer == 0 || --sc->emac_watchdog_timer)
464 if (sc->emac_link == 0) {
466 if_printf(sc->emac_ifp, "watchdog timeout "
469 if_printf(sc->emac_ifp, "watchdog timeout -- resetting\n");
471 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
472 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
473 emac_init_locked(sc);
474 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
475 emac_start_locked(ifp);
481 struct emac_softc *sc;
482 struct mii_data *mii;
484 sc = (struct emac_softc *)arg;
485 mii = device_get_softc(sc->emac_miibus);
489 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc);
495 struct emac_softc *sc;
497 sc = (struct emac_softc *)xcs;
499 emac_init_locked(sc);
504 emac_init_locked(struct emac_softc *sc)
507 struct mii_data *mii;
511 EMAC_ASSERT_LOCKED(sc);
514 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
518 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL);
519 reg_val |= EMAC_RX_FLUSH_FIFO;
520 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
524 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0);
525 reg_val &= (~EMAC_MAC_CTL0_SOFT_RST);
526 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val);
529 reg_val = EMAC_READ_REG(sc, EMAC_MAC_MCFG);
530 reg_val &= (~(0xf << 2));
531 reg_val |= (0xd << 2);
532 EMAC_WRITE_REG(sc, EMAC_MAC_MCFG, reg_val);
534 /* Clear RX counter */
535 EMAC_WRITE_REG(sc, EMAC_RX_FBC, 0);
537 /* Disable all interrupt and clear interrupt status */
538 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0);
539 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA);
540 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
544 reg_val = EMAC_READ_REG(sc, EMAC_TX_MODE);
545 reg_val |= EMAC_TX_AB_M;
546 reg_val &= EMAC_TX_TM;
547 EMAC_WRITE_REG(sc, EMAC_TX_MODE, reg_val);
550 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL);
551 reg_val |= EMAC_RX_SETUP;
552 reg_val &= EMAC_RX_TM;
553 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
555 /* Set up MAC CTL0. */
556 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0);
557 reg_val |= EMAC_MAC_CTL0_SETUP;
558 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val);
560 /* Set up MAC CTL1. */
561 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL1);
562 reg_val |= EMAC_MAC_CTL1_SETUP;
563 EMAC_WRITE_REG(sc, EMAC_MAC_CTL1, reg_val);
566 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, EMAC_MAC_IPGT_FD);
569 EMAC_WRITE_REG(sc, EMAC_MAC_IPGR, EMAC_MAC_NBTB_IPG2 |
570 (EMAC_MAC_NBTB_IPG1 << 8));
572 /* Set up Collison window */
573 EMAC_WRITE_REG(sc, EMAC_MAC_CLRT, EMAC_MAC_RM | (EMAC_MAC_CW << 8));
575 /* Set up Max Frame Length */
576 EMAC_WRITE_REG(sc, EMAC_MAC_MAXF, EMAC_MAC_MFL);
578 /* Setup ethernet address */
579 eaddr = IF_LLADDR(ifp);
580 EMAC_WRITE_REG(sc, EMAC_MAC_A1, eaddr[0] << 16 |
581 eaddr[1] << 8 | eaddr[2]);
582 EMAC_WRITE_REG(sc, EMAC_MAC_A0, eaddr[3] << 16 |
583 eaddr[4] << 8 | eaddr[5]);
585 /* Setup rx filter */
586 emac_set_rx_mode(sc);
588 /* Enable RX/TX0/RX Hlevel interrupt */
589 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL);
590 reg_val |= EMAC_INT_EN;
591 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val);
593 ifp->if_drv_flags |= IFF_DRV_RUNNING;
594 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
598 /* Switch to the current media. */
599 mii = device_get_softc(sc->emac_miibus);
602 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc);
607 emac_start(struct ifnet *ifp)
609 struct emac_softc *sc;
613 emac_start_locked(ifp);
618 emac_start_locked(struct ifnet *ifp)
620 struct emac_softc *sc;
625 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
627 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1))
629 if (sc->emac_link == 0)
631 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
636 if (sc->emac_fifo_mask & EMAC_TX_FIFO0)
640 sc->emac_fifo_mask |= (1 << fifo);
641 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1))
642 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
643 EMAC_WRITE_REG(sc, EMAC_TX_INS, fifo);
646 * Emac controller wants 4 byte aligned TX buffers.
647 * We have to copy pretty much all the time.
649 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0) {
650 m0 = m_defrag(m, M_NOWAIT);
659 bus_space_write_multi_4(sc->emac_tag, sc->emac_handle,
660 EMAC_TX_IO_DATA, mtod(m, uint32_t *),
661 roundup2(m->m_len, 4) / 4);
663 /* Send the data lengh. */
664 reg = (fifo == 0) ? EMAC_TX_PL0 : EMAC_TX_PL1;
665 EMAC_WRITE_REG(sc, reg, m->m_len);
667 /* Start translate from fifo to phy. */
668 reg = (fifo == 0) ? EMAC_TX_CTL0 : EMAC_TX_CTL1;
669 EMAC_WRITE_REG(sc, reg, EMAC_READ_REG(sc, reg) | 1);
672 sc->emac_watchdog_timer = 5;
674 /* Data have been sent to hardware, it is okay to free the mbuf now. */
680 emac_stop_locked(struct emac_softc *sc)
685 EMAC_ASSERT_LOCKED(sc);
688 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
691 /* Disable all interrupt and clear interrupt status */
692 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0);
693 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA);
694 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
697 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
698 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN);
699 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
701 callout_stop(&sc->emac_tick_ch);
707 struct emac_softc *sc;
711 sc = (struct emac_softc *)arg;
714 /* Disable all interrupts */
715 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0);
716 /* Get EMAC interrupt status */
717 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA);
718 /* Clear ISR status */
719 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
721 /* Received incoming packet */
722 if (reg_val & EMAC_INT_STA_RX)
723 emac_rxeof(sc, sc->emac_rx_process_limit);
725 /* Transmit Interrupt check */
726 if (reg_val & EMAC_INT_STA_TX) {
727 emac_txeof(sc, reg_val);
729 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
730 emac_start_locked(ifp);
733 /* Re-enable interrupt mask */
734 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL);
735 reg_val |= EMAC_INT_EN;
736 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val);
741 emac_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
743 struct emac_softc *sc;
744 struct mii_data *mii;
749 ifr = (struct ifreq *)data;
754 if (ifp->if_flags & IFF_UP) {
755 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
756 if ((ifp->if_flags ^ sc->emac_if_flags) &
757 (IFF_PROMISC | IFF_ALLMULTI))
758 emac_set_rx_mode(sc);
760 emac_init_locked(sc);
762 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
763 emac_stop_locked(sc);
765 sc->emac_if_flags = ifp->if_flags;
771 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
772 emac_set_rx_mode(sc);
778 mii = device_get_softc(sc->emac_miibus);
779 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
782 error = ether_ioctl(ifp, command, data);
789 emac_probe(device_t dev)
792 if (!ofw_bus_status_okay(dev))
795 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-emac"))
798 device_set_desc(dev, "A10/A20 EMAC ethernet controller");
799 return (BUS_PROBE_DEFAULT);
803 emac_detach(device_t dev)
805 struct emac_softc *sc;
807 sc = device_get_softc(dev);
808 sc->emac_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
809 if (device_is_attached(dev)) {
810 ether_ifdetach(sc->emac_ifp);
812 emac_stop_locked(sc);
814 callout_drain(&sc->emac_tick_ch);
817 if (sc->emac_intrhand != NULL)
818 bus_teardown_intr(sc->emac_dev, sc->emac_irq,
821 if (sc->emac_miibus != NULL) {
822 device_delete_child(sc->emac_dev, sc->emac_miibus);
823 bus_generic_detach(sc->emac_dev);
826 if (sc->emac_clk != NULL)
827 clk_disable(sc->emac_clk);
829 if (sc->emac_res != NULL)
830 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->emac_res);
832 if (sc->emac_irq != NULL)
833 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->emac_irq);
835 if (sc->emac_ifp != NULL)
836 if_free(sc->emac_ifp);
838 if (mtx_initialized(&sc->emac_mtx))
839 mtx_destroy(&sc->emac_mtx);
845 emac_shutdown(device_t dev)
848 return (emac_suspend(dev));
852 emac_suspend(device_t dev)
854 struct emac_softc *sc;
857 sc = device_get_softc(dev);
861 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
862 emac_stop_locked(sc);
869 emac_resume(device_t dev)
871 struct emac_softc *sc;
874 sc = device_get_softc(dev);
878 if ((ifp->if_flags & IFF_UP) != 0) {
879 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
880 emac_init_locked(sc);
888 emac_attach(device_t dev)
890 struct emac_softc *sc;
893 uint8_t eaddr[ETHER_ADDR_LEN];
895 sc = device_get_softc(dev);
899 mtx_init(&sc->emac_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
901 callout_init_mtx(&sc->emac_tick_ch, &sc->emac_mtx, 0);
904 sc->emac_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
906 if (sc->emac_res == NULL) {
907 device_printf(dev, "unable to map memory\n");
912 sc->emac_tag = rman_get_bustag(sc->emac_res);
913 sc->emac_handle = rman_get_bushandle(sc->emac_res);
916 sc->emac_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
917 RF_SHAREABLE | RF_ACTIVE);
918 if (sc->emac_irq == NULL) {
919 device_printf(dev, "cannot allocate IRQ resources.\n");
923 /* Create device sysctl node. */
924 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
925 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
926 OID_AUTO, "process_limit",
927 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
928 &sc->emac_rx_process_limit, 0, sysctl_hw_emac_proc_limit, "I",
929 "max number of Rx events to process");
931 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT;
932 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
933 "process_limit", &sc->emac_rx_process_limit);
935 if (sc->emac_rx_process_limit < EMAC_PROC_MIN ||
936 sc->emac_rx_process_limit > EMAC_PROC_MAX) {
937 device_printf(dev, "process_limit value out of range; "
938 "using default: %d\n", EMAC_PROC_DEFAULT);
939 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT;
943 error = emac_sys_setup(sc);
949 ifp = sc->emac_ifp = if_alloc(IFT_ETHER);
951 device_printf(dev, "unable to allocate ifp\n");
958 error = mii_attach(dev, &sc->emac_miibus, ifp, emac_ifmedia_upd,
959 emac_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
961 device_printf(dev, "PHY probe failed\n");
965 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
966 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
967 ifp->if_start = emac_start;
968 ifp->if_ioctl = emac_ioctl;
969 ifp->if_init = emac_init;
970 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
972 /* Get MAC address */
973 emac_get_hwaddr(sc, eaddr);
974 ether_ifattach(ifp, eaddr);
976 /* VLAN capability setup. */
977 ifp->if_capabilities |= IFCAP_VLAN_MTU;
978 ifp->if_capenable = ifp->if_capabilities;
979 /* Tell the upper layer we support VLAN over-sized frames. */
980 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
982 error = bus_setup_intr(dev, sc->emac_irq, INTR_TYPE_NET | INTR_MPSAFE,
983 NULL, emac_intr, sc, &sc->emac_intrhand);
985 device_printf(dev, "could not set up interrupt handler.\n");
997 emac_miibus_iowait(struct emac_softc *sc)
1001 for (timeout = 100; timeout != 0; --timeout) {
1003 if ((EMAC_READ_REG(sc, EMAC_MAC_MIND) & 0x1) == 0)
1011 * The MII bus interface
1014 emac_miibus_readreg(device_t dev, int phy, int reg)
1016 struct emac_softc *sc;
1019 sc = device_get_softc(dev);
1021 /* Issue phy address and reg */
1022 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg);
1023 /* Pull up the phy io line */
1024 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1);
1025 if (!emac_miibus_iowait(sc)) {
1026 device_printf(dev, "timeout waiting for mii read\n");
1029 /* Push down the phy io line */
1030 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0);
1032 rval = EMAC_READ_REG(sc, EMAC_MAC_MRDD);
1038 emac_miibus_writereg(device_t dev, int phy, int reg, int data)
1040 struct emac_softc *sc;
1042 sc = device_get_softc(dev);
1044 /* Issue phy address and reg */
1045 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg);
1047 EMAC_WRITE_REG(sc, EMAC_MAC_MWTD, data);
1048 /* Pull up the phy io line */
1049 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1);
1050 if (!emac_miibus_iowait(sc)) {
1051 device_printf(dev, "timeout waiting for mii write\n");
1054 /* Push down the phy io line */
1055 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0);
1061 emac_miibus_statchg(device_t dev)
1063 struct emac_softc *sc;
1064 struct mii_data *mii;
1068 sc = device_get_softc(dev);
1070 mii = device_get_softc(sc->emac_miibus);
1072 if (mii == NULL || ifp == NULL ||
1073 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1077 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1078 (IFM_ACTIVE | IFM_AVALID)) {
1079 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1088 /* Program MACs with resolved speed/duplex. */
1089 if (sc->emac_link != 0) {
1090 reg_val = EMAC_READ_REG(sc, EMAC_MAC_IPGT);
1091 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1092 reg_val &= ~EMAC_MAC_IPGT_HD;
1093 reg_val |= EMAC_MAC_IPGT_FD;
1095 reg_val &= ~EMAC_MAC_IPGT_FD;
1096 reg_val |= EMAC_MAC_IPGT_HD;
1098 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, reg_val);
1100 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
1101 reg_val |= EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN;
1102 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
1105 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
1106 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN);
1107 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
1112 emac_ifmedia_upd(struct ifnet *ifp)
1114 struct emac_softc *sc;
1115 struct mii_data *mii;
1116 struct mii_softc *miisc;
1120 mii = device_get_softc(sc->emac_miibus);
1122 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1124 error = mii_mediachg(mii);
1131 emac_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1133 struct emac_softc *sc;
1134 struct mii_data *mii;
1137 mii = device_get_softc(sc->emac_miibus);
1141 ifmr->ifm_active = mii->mii_media_active;
1142 ifmr->ifm_status = mii->mii_media_status;
1146 static device_method_t emac_methods[] = {
1147 /* Device interface */
1148 DEVMETHOD(device_probe, emac_probe),
1149 DEVMETHOD(device_attach, emac_attach),
1150 DEVMETHOD(device_detach, emac_detach),
1151 DEVMETHOD(device_shutdown, emac_shutdown),
1152 DEVMETHOD(device_suspend, emac_suspend),
1153 DEVMETHOD(device_resume, emac_resume),
1155 /* bus interface, for miibus */
1156 DEVMETHOD(bus_print_child, bus_generic_print_child),
1157 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
1160 DEVMETHOD(miibus_readreg, emac_miibus_readreg),
1161 DEVMETHOD(miibus_writereg, emac_miibus_writereg),
1162 DEVMETHOD(miibus_statchg, emac_miibus_statchg),
1167 static driver_t emac_driver = {
1170 sizeof(struct emac_softc)
1173 static devclass_t emac_devclass;
1175 DRIVER_MODULE(emac, simplebus, emac_driver, emac_devclass, 0, 0);
1176 DRIVER_MODULE(miibus, emac, miibus_driver, miibus_devclass, 0, 0);
1177 MODULE_DEPEND(emac, miibus, 1, 1, 1);
1178 MODULE_DEPEND(emac, ether, 1, 1, 1);
1181 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
1187 value = *(int *)arg1;
1188 error = sysctl_handle_int(oidp, &value, 0, req);
1189 if (error || req->newptr == NULL)
1191 if (value < low || value > high)
1193 *(int *)arg1 = value;
1199 sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS)
1202 return (sysctl_int_range(oidp, arg1, arg2, req,
1203 EMAC_PROC_MIN, EMAC_PROC_MAX));