2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 /* A10/A20 EMAC driver */
31 #include <sys/cdefs.h>
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
39 #include <sys/mutex.h>
41 #include <sys/socket.h>
42 #include <sys/sockio.h>
43 #include <sys/sysctl.h>
46 #include <machine/bus.h>
47 #include <machine/resource.h>
48 #include <machine/intr.h>
51 #include <net/if_var.h>
52 #include <net/if_arp.h>
53 #include <net/if_dl.h>
54 #include <net/if_media.h>
55 #include <net/if_types.h>
56 #include <net/if_mib.h>
57 #include <net/ethernet.h>
58 #include <net/if_vlan_var.h>
61 #include <netinet/in.h>
62 #include <netinet/in_systm.h>
63 #include <netinet/in_var.h>
64 #include <netinet/ip.h>
68 #include <net/bpfdesc.h>
70 #include <dev/ofw/ofw_bus.h>
71 #include <dev/ofw/ofw_bus_subr.h>
73 #include <dev/mii/mii.h>
74 #include <dev/mii/miivar.h>
76 #include <arm/allwinner/if_emacreg.h>
77 #include <arm/allwinner/aw_sid.h>
79 #include <dev/extres/clk/clk.h>
81 #include "miibus_if.h"
85 #include "a10_sramc.h"
91 bus_space_handle_t emac_handle;
92 bus_space_tag_t emac_tag;
93 struct resource *emac_res;
94 struct resource *emac_irq;
99 struct callout emac_tick_ch;
100 int emac_watchdog_timer;
101 int emac_rx_process_limit;
103 uint32_t emac_fifo_mask;
106 static int emac_probe(device_t);
107 static int emac_attach(device_t);
108 static int emac_detach(device_t);
109 static int emac_shutdown(device_t);
110 static int emac_suspend(device_t);
111 static int emac_resume(device_t);
113 static int emac_sys_setup(struct emac_softc *);
114 static void emac_reset(struct emac_softc *);
116 static void emac_init_locked(struct emac_softc *);
117 static void emac_start_locked(if_t);
118 static void emac_init(void *);
119 static void emac_stop_locked(struct emac_softc *);
120 static void emac_intr(void *);
121 static int emac_ioctl(if_t, u_long, caddr_t);
123 static void emac_rxeof(struct emac_softc *, int);
124 static void emac_txeof(struct emac_softc *, uint32_t);
126 static int emac_miibus_readreg(device_t, int, int);
127 static int emac_miibus_writereg(device_t, int, int, int);
128 static void emac_miibus_statchg(device_t);
130 static int emac_ifmedia_upd(if_t);
131 static void emac_ifmedia_sts(if_t, struct ifmediareq *);
133 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
134 static int sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS);
136 #define EMAC_READ_REG(sc, reg) \
137 bus_space_read_4(sc->emac_tag, sc->emac_handle, reg)
138 #define EMAC_WRITE_REG(sc, reg, val) \
139 bus_space_write_4(sc->emac_tag, sc->emac_handle, reg, val)
142 emac_sys_setup(struct emac_softc *sc)
146 /* Activate EMAC clock. */
147 error = clk_get_by_ofw_index(sc->emac_dev, 0, 0, &sc->emac_clk);
149 device_printf(sc->emac_dev, "cannot get clock\n");
152 error = clk_enable(sc->emac_clk);
154 device_printf(sc->emac_dev, "cannot enable clock\n");
165 emac_get_hwaddr(struct emac_softc *sc, uint8_t *hwaddr)
167 uint32_t val0, val1, rnd;
172 * Try to get MAC address from running hardware.
173 * If there is something non-zero there just use it.
175 * Otherwise set the address to a convenient locally assigned address,
176 * using the SID rootkey.
177 * This is was uboot does so we end up with the same mac as if uboot
179 * If we can't get the root key, generate a random one,
180 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally
181 * assigned bit set, and the broadcast/multicast bit clear.
183 val0 = EMAC_READ_REG(sc, EMAC_MAC_A0);
184 val1 = EMAC_READ_REG(sc, EMAC_MAC_A1);
185 if ((val0 | val1) != 0 && (val0 | val1) != 0xffffff) {
186 hwaddr[0] = (val1 >> 16) & 0xff;
187 hwaddr[1] = (val1 >> 8) & 0xff;
188 hwaddr[2] = (val1 >> 0) & 0xff;
189 hwaddr[3] = (val0 >> 16) & 0xff;
190 hwaddr[4] = (val0 >> 8) & 0xff;
191 hwaddr[5] = (val0 >> 0) & 0xff;
193 rootkey_size = sizeof(rootkey);
194 if (aw_sid_get_fuse(AW_SID_FUSE_ROOTKEY, rootkey,
195 &rootkey_size) == 0) {
197 hwaddr[1] = rootkey[3];
198 hwaddr[2] = rootkey[12];
199 hwaddr[3] = rootkey[13];
200 hwaddr[4] = rootkey[14];
201 hwaddr[5] = rootkey[15];
204 rnd = arc4random() & 0x00ffffff;
208 hwaddr[3] = (rnd >> 16) & 0xff;
209 hwaddr[4] = (rnd >> 8) & 0xff;
210 hwaddr[5] = (rnd >> 0) & 0xff;
214 printf("MAC address: %s\n", ether_sprintf(hwaddr));
218 emac_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
220 uint32_t h, *hashes = arg;
222 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
223 hashes[h >> 5] |= 1 << (h & 0x1f);
229 emac_set_rx_mode(struct emac_softc *sc)
235 EMAC_ASSERT_LOCKED(sc);
239 rcr = EMAC_READ_REG(sc, EMAC_RX_CTL);
241 /* Unicast packet and DA filtering */
247 if (if_getflags(ifp) & IFF_ALLMULTI) {
248 hashes[0] = 0xffffffff;
249 hashes[1] = 0xffffffff;
251 if_foreach_llmaddr(ifp, emac_hash_maddr, hashes);
254 EMAC_WRITE_REG(sc, EMAC_RX_HASH0, hashes[0]);
255 EMAC_WRITE_REG(sc, EMAC_RX_HASH1, hashes[1]);
257 if (if_getflags(ifp) & IFF_BROADCAST) {
262 if (if_getflags(ifp) & IFF_PROMISC)
267 EMAC_WRITE_REG(sc, EMAC_RX_CTL, rcr);
271 emac_reset(struct emac_softc *sc)
274 EMAC_WRITE_REG(sc, EMAC_CTL, 0);
276 EMAC_WRITE_REG(sc, EMAC_CTL, 1);
281 emac_drain_rxfifo(struct emac_softc *sc)
284 while (EMAC_READ_REG(sc, EMAC_RX_FBC) > 0)
285 (void)EMAC_READ_REG(sc, EMAC_RX_IO_DATA);
289 emac_txeof(struct emac_softc *sc, uint32_t status)
293 EMAC_ASSERT_LOCKED(sc);
296 status &= (EMAC_TX_FIFO0 | EMAC_TX_FIFO1);
297 sc->emac_fifo_mask &= ~status;
298 if (status == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1))
299 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 2);
301 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
302 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
304 /* Unarm watchdog timer if no TX */
305 sc->emac_watchdog_timer = 0;
309 emac_rxeof(struct emac_softc *sc, int count)
313 uint32_t reg_val, rxcount;
320 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0; count--) {
322 * Race warning: The first packet might arrive with
323 * the interrupts disabled, but the second will fix
325 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC);
328 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC);
332 /* Check packet header */
333 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA);
334 if (reg_val != EMAC_PACKET_HEADER) {
335 /* Packet header is wrong */
337 if_printf(ifp, "wrong packet header\n");
339 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
340 reg_val &= ~EMAC_CTL_RX_EN;
341 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
344 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL);
345 reg_val |= EMAC_RX_FLUSH_FIFO;
346 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
347 for (i = 100; i > 0; i--) {
349 if ((EMAC_READ_REG(sc, EMAC_RX_CTL) &
350 EMAC_RX_FLUSH_FIFO) == 0)
354 device_printf(sc->emac_dev,
355 "flush FIFO timeout\n");
356 /* Reinitialize controller */
357 emac_init_locked(sc);
361 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
362 reg_val |= EMAC_CTL_RX_EN;
363 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
368 /* Get packet size and status */
369 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA);
370 len = reg_val & 0xffff;
371 status = (reg_val >> 16) & 0xffff;
373 if (len < 64 || (status & EMAC_PKT_OK) == 0) {
376 "bad packet: len = %i status = %i\n",
378 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
379 emac_drain_rxfifo(sc);
383 if (status & (EMAC_CRCERR | EMAC_LENERR)) {
385 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
386 if (status & EMAC_CRCERR)
387 if_printf(ifp, "crc error\n");
388 if (status & EMAC_LENERR)
389 if_printf(ifp, "length error\n");
392 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
394 emac_drain_rxfifo(sc);
397 m->m_len = m->m_pkthdr.len = MCLBYTES;
399 /* Copy entire frame to mbuf first. */
400 bus_space_read_multi_4(sc->emac_tag, sc->emac_handle,
401 EMAC_RX_IO_DATA, mtod(m, uint32_t *), roundup2(len, 4) / 4);
403 m->m_pkthdr.rcvif = ifp;
404 m->m_len = m->m_pkthdr.len = len - ETHER_CRC_LEN;
407 * Emac controller needs strict alignment, so to avoid
408 * copying over an entire frame to align, we allocate
409 * a new mbuf and copy ethernet header + IP header to
410 * the new mbuf. The new mbuf is prepended into the
411 * existing mbuf chain.
413 if (m->m_len <= (MHLEN - ETHER_HDR_LEN)) {
414 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
415 m->m_data += ETHER_HDR_LEN;
416 } else if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN) &&
417 m->m_len > (MHLEN - ETHER_HDR_LEN)) {
418 MGETHDR(m0, M_NOWAIT, MT_DATA);
420 len = ETHER_HDR_LEN + m->m_pkthdr.l2hlen;
421 bcopy(m->m_data, m0->m_data, len);
425 M_MOVE_PKTHDR(m0, m);
429 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
434 } else if (m->m_len > EMAC_MAC_MAXF) {
435 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
440 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
448 emac_watchdog(struct emac_softc *sc)
452 EMAC_ASSERT_LOCKED(sc);
454 if (sc->emac_watchdog_timer == 0 || --sc->emac_watchdog_timer)
459 if (sc->emac_link == 0) {
461 if_printf(sc->emac_ifp, "watchdog timeout "
464 if_printf(sc->emac_ifp, "watchdog timeout -- resetting\n");
466 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
467 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
468 emac_init_locked(sc);
469 if (!if_sendq_empty(ifp))
470 emac_start_locked(ifp);
476 struct emac_softc *sc;
477 struct mii_data *mii;
479 sc = (struct emac_softc *)arg;
480 mii = device_get_softc(sc->emac_miibus);
484 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc);
490 struct emac_softc *sc;
492 sc = (struct emac_softc *)xcs;
494 emac_init_locked(sc);
499 emac_init_locked(struct emac_softc *sc)
502 struct mii_data *mii;
506 EMAC_ASSERT_LOCKED(sc);
509 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
513 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL);
514 reg_val |= EMAC_RX_FLUSH_FIFO;
515 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
519 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0);
520 reg_val &= (~EMAC_MAC_CTL0_SOFT_RST);
521 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val);
524 reg_val = EMAC_READ_REG(sc, EMAC_MAC_MCFG);
525 reg_val &= (~(0xf << 2));
526 reg_val |= (0xd << 2);
527 EMAC_WRITE_REG(sc, EMAC_MAC_MCFG, reg_val);
529 /* Clear RX counter */
530 EMAC_WRITE_REG(sc, EMAC_RX_FBC, 0);
532 /* Disable all interrupt and clear interrupt status */
533 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0);
534 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA);
535 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
539 reg_val = EMAC_READ_REG(sc, EMAC_TX_MODE);
540 reg_val |= EMAC_TX_AB_M;
541 reg_val &= EMAC_TX_TM;
542 EMAC_WRITE_REG(sc, EMAC_TX_MODE, reg_val);
545 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL);
546 reg_val |= EMAC_RX_SETUP;
547 reg_val &= EMAC_RX_TM;
548 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
550 /* Set up MAC CTL0. */
551 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0);
552 reg_val |= EMAC_MAC_CTL0_SETUP;
553 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val);
555 /* Set up MAC CTL1. */
556 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL1);
557 reg_val |= EMAC_MAC_CTL1_SETUP;
558 EMAC_WRITE_REG(sc, EMAC_MAC_CTL1, reg_val);
561 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, EMAC_MAC_IPGT_FD);
564 EMAC_WRITE_REG(sc, EMAC_MAC_IPGR, EMAC_MAC_NBTB_IPG2 |
565 (EMAC_MAC_NBTB_IPG1 << 8));
567 /* Set up Collison window */
568 EMAC_WRITE_REG(sc, EMAC_MAC_CLRT, EMAC_MAC_RM | (EMAC_MAC_CW << 8));
570 /* Set up Max Frame Length */
571 EMAC_WRITE_REG(sc, EMAC_MAC_MAXF, EMAC_MAC_MFL);
573 /* Setup ethernet address */
574 eaddr = if_getlladdr(ifp);
575 EMAC_WRITE_REG(sc, EMAC_MAC_A1, eaddr[0] << 16 |
576 eaddr[1] << 8 | eaddr[2]);
577 EMAC_WRITE_REG(sc, EMAC_MAC_A0, eaddr[3] << 16 |
578 eaddr[4] << 8 | eaddr[5]);
580 /* Setup rx filter */
581 emac_set_rx_mode(sc);
583 /* Enable RX/TX0/RX Hlevel interrupt */
584 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL);
585 reg_val |= EMAC_INT_EN;
586 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val);
588 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
589 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
593 /* Switch to the current media. */
594 mii = device_get_softc(sc->emac_miibus);
597 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc);
603 struct emac_softc *sc;
605 sc = if_getsoftc(ifp);
607 emac_start_locked(ifp);
612 emac_start_locked(if_t ifp)
614 struct emac_softc *sc;
618 sc = if_getsoftc(ifp);
619 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
621 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1))
623 if (sc->emac_link == 0)
630 if (sc->emac_fifo_mask & EMAC_TX_FIFO0)
634 sc->emac_fifo_mask |= (1 << fifo);
635 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1))
636 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
637 EMAC_WRITE_REG(sc, EMAC_TX_INS, fifo);
640 * Emac controller wants 4 byte aligned TX buffers.
641 * We have to copy pretty much all the time.
643 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0) {
644 m0 = m_defrag(m, M_NOWAIT);
653 bus_space_write_multi_4(sc->emac_tag, sc->emac_handle,
654 EMAC_TX_IO_DATA, mtod(m, uint32_t *),
655 roundup2(m->m_len, 4) / 4);
657 /* Send the data lengh. */
658 reg = (fifo == 0) ? EMAC_TX_PL0 : EMAC_TX_PL1;
659 EMAC_WRITE_REG(sc, reg, m->m_len);
661 /* Start translate from fifo to phy. */
662 reg = (fifo == 0) ? EMAC_TX_CTL0 : EMAC_TX_CTL1;
663 EMAC_WRITE_REG(sc, reg, EMAC_READ_REG(sc, reg) | 1);
666 sc->emac_watchdog_timer = 5;
668 /* Data have been sent to hardware, it is okay to free the mbuf now. */
674 emac_stop_locked(struct emac_softc *sc)
679 EMAC_ASSERT_LOCKED(sc);
682 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
685 /* Disable all interrupt and clear interrupt status */
686 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0);
687 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA);
688 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
691 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
692 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN);
693 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
695 callout_stop(&sc->emac_tick_ch);
701 struct emac_softc *sc;
705 sc = (struct emac_softc *)arg;
708 /* Disable all interrupts */
709 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0);
710 /* Get EMAC interrupt status */
711 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA);
712 /* Clear ISR status */
713 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
715 /* Received incoming packet */
716 if (reg_val & EMAC_INT_STA_RX)
717 emac_rxeof(sc, sc->emac_rx_process_limit);
719 /* Transmit Interrupt check */
720 if (reg_val & EMAC_INT_STA_TX) {
721 emac_txeof(sc, reg_val);
723 if (!if_sendq_empty(ifp))
724 emac_start_locked(ifp);
727 /* Re-enable interrupt mask */
728 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL);
729 reg_val |= EMAC_INT_EN;
730 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val);
735 emac_ioctl(if_t ifp, u_long command, caddr_t data)
737 struct emac_softc *sc;
738 struct mii_data *mii;
742 sc = if_getsoftc(ifp);
743 ifr = (struct ifreq *)data;
748 if (if_getflags(ifp) & IFF_UP) {
749 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
750 if ((if_getflags(ifp) ^ sc->emac_if_flags) &
751 (IFF_PROMISC | IFF_ALLMULTI))
752 emac_set_rx_mode(sc);
754 emac_init_locked(sc);
756 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
757 emac_stop_locked(sc);
759 sc->emac_if_flags = if_getflags(ifp);
765 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
766 emac_set_rx_mode(sc);
772 mii = device_get_softc(sc->emac_miibus);
773 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
776 error = ether_ioctl(ifp, command, data);
783 emac_probe(device_t dev)
786 if (!ofw_bus_status_okay(dev))
789 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-emac"))
792 device_set_desc(dev, "A10/A20 EMAC ethernet controller");
793 return (BUS_PROBE_DEFAULT);
797 emac_detach(device_t dev)
799 struct emac_softc *sc;
801 sc = device_get_softc(dev);
802 if_setdrvflagbits(sc->emac_ifp, 0, IFF_DRV_RUNNING);
803 if (device_is_attached(dev)) {
804 ether_ifdetach(sc->emac_ifp);
806 emac_stop_locked(sc);
808 callout_drain(&sc->emac_tick_ch);
811 if (sc->emac_intrhand != NULL)
812 bus_teardown_intr(sc->emac_dev, sc->emac_irq,
815 if (sc->emac_miibus != NULL) {
816 device_delete_child(sc->emac_dev, sc->emac_miibus);
817 bus_generic_detach(sc->emac_dev);
820 if (sc->emac_clk != NULL)
821 clk_disable(sc->emac_clk);
823 if (sc->emac_res != NULL)
824 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->emac_res);
826 if (sc->emac_irq != NULL)
827 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->emac_irq);
829 if (sc->emac_ifp != NULL)
830 if_free(sc->emac_ifp);
832 if (mtx_initialized(&sc->emac_mtx))
833 mtx_destroy(&sc->emac_mtx);
839 emac_shutdown(device_t dev)
842 return (emac_suspend(dev));
846 emac_suspend(device_t dev)
848 struct emac_softc *sc;
851 sc = device_get_softc(dev);
855 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
856 emac_stop_locked(sc);
863 emac_resume(device_t dev)
865 struct emac_softc *sc;
868 sc = device_get_softc(dev);
872 if ((if_getflags(ifp) & IFF_UP) != 0) {
873 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
874 emac_init_locked(sc);
882 emac_attach(device_t dev)
884 struct emac_softc *sc;
887 uint8_t eaddr[ETHER_ADDR_LEN];
889 sc = device_get_softc(dev);
893 mtx_init(&sc->emac_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
895 callout_init_mtx(&sc->emac_tick_ch, &sc->emac_mtx, 0);
898 sc->emac_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
900 if (sc->emac_res == NULL) {
901 device_printf(dev, "unable to map memory\n");
906 sc->emac_tag = rman_get_bustag(sc->emac_res);
907 sc->emac_handle = rman_get_bushandle(sc->emac_res);
910 sc->emac_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
911 RF_SHAREABLE | RF_ACTIVE);
912 if (sc->emac_irq == NULL) {
913 device_printf(dev, "cannot allocate IRQ resources.\n");
917 /* Create device sysctl node. */
918 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
919 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
920 OID_AUTO, "process_limit",
921 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
922 &sc->emac_rx_process_limit, 0, sysctl_hw_emac_proc_limit, "I",
923 "max number of Rx events to process");
925 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT;
926 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
927 "process_limit", &sc->emac_rx_process_limit);
929 if (sc->emac_rx_process_limit < EMAC_PROC_MIN ||
930 sc->emac_rx_process_limit > EMAC_PROC_MAX) {
931 device_printf(dev, "process_limit value out of range; "
932 "using default: %d\n", EMAC_PROC_DEFAULT);
933 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT;
937 error = emac_sys_setup(sc);
943 ifp = sc->emac_ifp = if_alloc(IFT_ETHER);
945 device_printf(dev, "unable to allocate ifp\n");
949 if_setsoftc(ifp, sc);
952 error = mii_attach(dev, &sc->emac_miibus, ifp, emac_ifmedia_upd,
953 emac_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
955 device_printf(dev, "PHY probe failed\n");
959 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
960 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
961 if_setstartfn(ifp, emac_start);
962 if_setioctlfn(ifp, emac_ioctl);
963 if_setinitfn(ifp, emac_init);
964 if_setsendqlen(ifp, IFQ_MAXLEN);
966 /* Get MAC address */
967 emac_get_hwaddr(sc, eaddr);
968 ether_ifattach(ifp, eaddr);
970 /* VLAN capability setup. */
971 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
972 if_setcapenable(ifp, if_getcapabilities(ifp));
973 /* Tell the upper layer we support VLAN over-sized frames. */
974 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
976 error = bus_setup_intr(dev, sc->emac_irq, INTR_TYPE_NET | INTR_MPSAFE,
977 NULL, emac_intr, sc, &sc->emac_intrhand);
979 device_printf(dev, "could not set up interrupt handler.\n");
991 emac_miibus_iowait(struct emac_softc *sc)
995 for (timeout = 100; timeout != 0; --timeout) {
997 if ((EMAC_READ_REG(sc, EMAC_MAC_MIND) & 0x1) == 0)
1005 * The MII bus interface
1008 emac_miibus_readreg(device_t dev, int phy, int reg)
1010 struct emac_softc *sc;
1013 sc = device_get_softc(dev);
1015 /* Issue phy address and reg */
1016 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg);
1017 /* Pull up the phy io line */
1018 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1);
1019 if (!emac_miibus_iowait(sc)) {
1020 device_printf(dev, "timeout waiting for mii read\n");
1023 /* Push down the phy io line */
1024 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0);
1026 rval = EMAC_READ_REG(sc, EMAC_MAC_MRDD);
1032 emac_miibus_writereg(device_t dev, int phy, int reg, int data)
1034 struct emac_softc *sc;
1036 sc = device_get_softc(dev);
1038 /* Issue phy address and reg */
1039 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg);
1041 EMAC_WRITE_REG(sc, EMAC_MAC_MWTD, data);
1042 /* Pull up the phy io line */
1043 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1);
1044 if (!emac_miibus_iowait(sc)) {
1045 device_printf(dev, "timeout waiting for mii write\n");
1048 /* Push down the phy io line */
1049 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0);
1055 emac_miibus_statchg(device_t dev)
1057 struct emac_softc *sc;
1058 struct mii_data *mii;
1062 sc = device_get_softc(dev);
1064 mii = device_get_softc(sc->emac_miibus);
1066 if (mii == NULL || ifp == NULL ||
1067 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
1071 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1072 (IFM_ACTIVE | IFM_AVALID)) {
1073 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1082 /* Program MACs with resolved speed/duplex. */
1083 if (sc->emac_link != 0) {
1084 reg_val = EMAC_READ_REG(sc, EMAC_MAC_IPGT);
1085 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1086 reg_val &= ~EMAC_MAC_IPGT_HD;
1087 reg_val |= EMAC_MAC_IPGT_FD;
1089 reg_val &= ~EMAC_MAC_IPGT_FD;
1090 reg_val |= EMAC_MAC_IPGT_HD;
1092 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, reg_val);
1094 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
1095 reg_val |= EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN;
1096 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
1099 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
1100 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN);
1101 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
1106 emac_ifmedia_upd(if_t ifp)
1108 struct emac_softc *sc;
1109 struct mii_data *mii;
1110 struct mii_softc *miisc;
1113 sc = if_getsoftc(ifp);
1114 mii = device_get_softc(sc->emac_miibus);
1116 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1118 error = mii_mediachg(mii);
1125 emac_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
1127 struct emac_softc *sc;
1128 struct mii_data *mii;
1130 sc = if_getsoftc(ifp);
1131 mii = device_get_softc(sc->emac_miibus);
1135 ifmr->ifm_active = mii->mii_media_active;
1136 ifmr->ifm_status = mii->mii_media_status;
1140 static device_method_t emac_methods[] = {
1141 /* Device interface */
1142 DEVMETHOD(device_probe, emac_probe),
1143 DEVMETHOD(device_attach, emac_attach),
1144 DEVMETHOD(device_detach, emac_detach),
1145 DEVMETHOD(device_shutdown, emac_shutdown),
1146 DEVMETHOD(device_suspend, emac_suspend),
1147 DEVMETHOD(device_resume, emac_resume),
1149 /* bus interface, for miibus */
1150 DEVMETHOD(bus_print_child, bus_generic_print_child),
1151 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
1154 DEVMETHOD(miibus_readreg, emac_miibus_readreg),
1155 DEVMETHOD(miibus_writereg, emac_miibus_writereg),
1156 DEVMETHOD(miibus_statchg, emac_miibus_statchg),
1161 static driver_t emac_driver = {
1164 sizeof(struct emac_softc)
1167 DRIVER_MODULE(emac, simplebus, emac_driver, 0, 0);
1168 DRIVER_MODULE(miibus, emac, miibus_driver, 0, 0);
1169 MODULE_DEPEND(emac, miibus, 1, 1, 1);
1170 MODULE_DEPEND(emac, ether, 1, 1, 1);
1173 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
1179 value = *(int *)arg1;
1180 error = sysctl_handle_int(oidp, &value, 0, req);
1181 if (error || req->newptr == NULL)
1183 if (value < low || value > high)
1185 *(int *)arg1 = value;
1191 sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS)
1194 return (sysctl_int_range(oidp, arg1, arg2, req,
1195 EMAC_PROC_MIN, EMAC_PROC_MAX));