2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 /* A10/A20 EMAC driver */
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
43 #include <sys/mutex.h>
45 #include <sys/socket.h>
46 #include <sys/sockio.h>
47 #include <sys/sysctl.h>
50 #include <machine/bus.h>
51 #include <machine/resource.h>
52 #include <machine/intr.h>
55 #include <net/if_var.h>
56 #include <net/if_arp.h>
57 #include <net/if_dl.h>
58 #include <net/if_media.h>
59 #include <net/if_types.h>
60 #include <net/if_mib.h>
61 #include <net/ethernet.h>
62 #include <net/if_vlan_var.h>
65 #include <netinet/in.h>
66 #include <netinet/in_systm.h>
67 #include <netinet/in_var.h>
68 #include <netinet/ip.h>
72 #include <net/bpfdesc.h>
74 #include <dev/ofw/ofw_bus.h>
75 #include <dev/ofw/ofw_bus_subr.h>
77 #include <dev/mii/mii.h>
78 #include <dev/mii/miivar.h>
80 #include <arm/allwinner/if_emacreg.h>
81 #include <arm/allwinner/aw_sid.h>
83 #include <dev/extres/clk/clk.h>
85 #include "miibus_if.h"
89 #include "a10_sramc.h"
92 struct ifnet *emac_ifp;
95 bus_space_handle_t emac_handle;
96 bus_space_tag_t emac_tag;
97 struct resource *emac_res;
98 struct resource *emac_irq;
103 struct callout emac_tick_ch;
104 int emac_watchdog_timer;
105 int emac_rx_process_limit;
107 uint32_t emac_fifo_mask;
110 static int emac_probe(device_t);
111 static int emac_attach(device_t);
112 static int emac_detach(device_t);
113 static int emac_shutdown(device_t);
114 static int emac_suspend(device_t);
115 static int emac_resume(device_t);
117 static int emac_sys_setup(struct emac_softc *);
118 static void emac_reset(struct emac_softc *);
120 static void emac_init_locked(struct emac_softc *);
121 static void emac_start_locked(struct ifnet *);
122 static void emac_init(void *);
123 static void emac_stop_locked(struct emac_softc *);
124 static void emac_intr(void *);
125 static int emac_ioctl(struct ifnet *, u_long, caddr_t);
127 static void emac_rxeof(struct emac_softc *, int);
128 static void emac_txeof(struct emac_softc *, uint32_t);
130 static int emac_miibus_readreg(device_t, int, int);
131 static int emac_miibus_writereg(device_t, int, int, int);
132 static void emac_miibus_statchg(device_t);
134 static int emac_ifmedia_upd(struct ifnet *);
135 static void emac_ifmedia_sts(struct ifnet *, struct ifmediareq *);
137 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
138 static int sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS);
140 #define EMAC_READ_REG(sc, reg) \
141 bus_space_read_4(sc->emac_tag, sc->emac_handle, reg)
142 #define EMAC_WRITE_REG(sc, reg, val) \
143 bus_space_write_4(sc->emac_tag, sc->emac_handle, reg, val)
146 emac_sys_setup(struct emac_softc *sc)
150 /* Activate EMAC clock. */
151 error = clk_get_by_ofw_index(sc->emac_dev, 0, 0, &sc->emac_clk);
153 device_printf(sc->emac_dev, "cannot get clock\n");
156 error = clk_enable(sc->emac_clk);
158 device_printf(sc->emac_dev, "cannot enable clock\n");
169 emac_get_hwaddr(struct emac_softc *sc, uint8_t *hwaddr)
171 uint32_t val0, val1, rnd;
175 * Try to get MAC address from running hardware.
176 * If there is something non-zero there just use it.
178 * Otherwise set the address to a convenient locally assigned address,
179 * using the SID rootkey.
180 * This is was uboot does so we end up with the same mac as if uboot
182 * If we can't get the root key, generate a random one,
183 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally
184 * assigned bit set, and the broadcast/multicast bit clear.
186 val0 = EMAC_READ_REG(sc, EMAC_MAC_A0);
187 val1 = EMAC_READ_REG(sc, EMAC_MAC_A1);
188 if ((val0 | val1) != 0 && (val0 | val1) != 0xffffff) {
189 hwaddr[0] = (val1 >> 16) & 0xff;
190 hwaddr[1] = (val1 >> 8) & 0xff;
191 hwaddr[2] = (val1 >> 0) & 0xff;
192 hwaddr[3] = (val0 >> 16) & 0xff;
193 hwaddr[4] = (val0 >> 8) & 0xff;
194 hwaddr[5] = (val0 >> 0) & 0xff;
196 if (aw_sid_get_rootkey(rootkey) == 0) {
198 hwaddr[1] = rootkey[3];
199 hwaddr[2] = rootkey[12];
200 hwaddr[3] = rootkey[13];
201 hwaddr[4] = rootkey[14];
202 hwaddr[5] = rootkey[15];
205 rnd = arc4random() & 0x00ffffff;
209 hwaddr[3] = (rnd >> 16) & 0xff;
210 hwaddr[4] = (rnd >> 8) & 0xff;
211 hwaddr[5] = (rnd >> 0) & 0xff;
215 printf("MAC address: %s\n", ether_sprintf(hwaddr));
219 emac_set_rx_mode(struct emac_softc *sc)
222 struct ifmultiaddr *ifma;
223 uint32_t h, hashes[2];
226 EMAC_ASSERT_LOCKED(sc);
230 rcr = EMAC_READ_REG(sc, EMAC_RX_CTL);
232 /* Unicast packet and DA filtering */
238 if (ifp->if_flags & IFF_ALLMULTI) {
239 hashes[0] = 0xffffffff;
240 hashes[1] = 0xffffffff;
243 TAILQ_FOREACH(ifma, &sc->emac_ifp->if_multiaddrs, ifma_link) {
244 if (ifma->ifma_addr->sa_family != AF_LINK)
246 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
247 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
248 hashes[h >> 5] |= 1 << (h & 0x1f);
250 if_maddr_runlock(ifp);
254 EMAC_WRITE_REG(sc, EMAC_RX_HASH0, hashes[0]);
255 EMAC_WRITE_REG(sc, EMAC_RX_HASH1, hashes[1]);
257 if (ifp->if_flags & IFF_BROADCAST) {
262 if (ifp->if_flags & IFF_PROMISC)
267 EMAC_WRITE_REG(sc, EMAC_RX_CTL, rcr);
271 emac_reset(struct emac_softc *sc)
274 EMAC_WRITE_REG(sc, EMAC_CTL, 0);
276 EMAC_WRITE_REG(sc, EMAC_CTL, 1);
281 emac_drain_rxfifo(struct emac_softc *sc)
285 while (EMAC_READ_REG(sc, EMAC_RX_FBC) > 0)
286 data = EMAC_READ_REG(sc, EMAC_RX_IO_DATA);
290 emac_txeof(struct emac_softc *sc, uint32_t status)
294 EMAC_ASSERT_LOCKED(sc);
297 status &= (EMAC_TX_FIFO0 | EMAC_TX_FIFO1);
298 sc->emac_fifo_mask &= ~status;
299 if (status == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1))
300 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 2);
302 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
303 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
305 /* Unarm watchdog timer if no TX */
306 sc->emac_watchdog_timer = 0;
310 emac_rxeof(struct emac_softc *sc, int count)
314 uint32_t reg_val, rxcount;
321 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; count--) {
323 * Race warning: The first packet might arrive with
324 * the interrupts disabled, but the second will fix
326 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC);
329 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC);
333 /* Check packet header */
334 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA);
335 if (reg_val != EMAC_PACKET_HEADER) {
336 /* Packet header is wrong */
338 if_printf(ifp, "wrong packet header\n");
340 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
341 reg_val &= ~EMAC_CTL_RX_EN;
342 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
345 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL);
346 reg_val |= EMAC_RX_FLUSH_FIFO;
347 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
348 for (i = 100; i > 0; i--) {
350 if ((EMAC_READ_REG(sc, EMAC_RX_CTL) &
351 EMAC_RX_FLUSH_FIFO) == 0)
355 device_printf(sc->emac_dev,
356 "flush FIFO timeout\n");
357 /* Reinitialize controller */
358 emac_init_locked(sc);
362 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
363 reg_val |= EMAC_CTL_RX_EN;
364 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
369 /* Get packet size and status */
370 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA);
371 len = reg_val & 0xffff;
372 status = (reg_val >> 16) & 0xffff;
374 if (len < 64 || (status & EMAC_PKT_OK) == 0) {
377 "bad packet: len = %i status = %i\n",
379 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
380 emac_drain_rxfifo(sc);
384 if (status & (EMAC_CRCERR | EMAC_LENERR)) {
386 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
387 if (status & EMAC_CRCERR)
388 if_printf(ifp, "crc error\n");
389 if (status & EMAC_LENERR)
390 if_printf(ifp, "length error\n");
393 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
395 emac_drain_rxfifo(sc);
398 m->m_len = m->m_pkthdr.len = MCLBYTES;
400 /* Copy entire frame to mbuf first. */
401 bus_space_read_multi_4(sc->emac_tag, sc->emac_handle,
402 EMAC_RX_IO_DATA, mtod(m, uint32_t *), roundup2(len, 4) / 4);
404 m->m_pkthdr.rcvif = ifp;
405 m->m_len = m->m_pkthdr.len = len - ETHER_CRC_LEN;
408 * Emac controller needs strict aligment, so to avoid
409 * copying over an entire frame to align, we allocate
410 * a new mbuf and copy ethernet header + IP header to
411 * the new mbuf. The new mbuf is prepended into the
412 * existing mbuf chain.
414 if (m->m_len <= (MHLEN - ETHER_HDR_LEN)) {
415 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
416 m->m_data += ETHER_HDR_LEN;
417 } else if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN) &&
418 m->m_len > (MHLEN - ETHER_HDR_LEN)) {
419 MGETHDR(m0, M_NOWAIT, MT_DATA);
421 len = ETHER_HDR_LEN + m->m_pkthdr.l2hlen;
422 bcopy(m->m_data, m0->m_data, len);
426 M_MOVE_PKTHDR(m0, m);
430 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
435 } else if (m->m_len > EMAC_MAC_MAXF) {
436 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
441 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
443 (*ifp->if_input)(ifp, m);
449 emac_watchdog(struct emac_softc *sc)
453 EMAC_ASSERT_LOCKED(sc);
455 if (sc->emac_watchdog_timer == 0 || --sc->emac_watchdog_timer)
460 if (sc->emac_link == 0) {
462 if_printf(sc->emac_ifp, "watchdog timeout "
465 if_printf(sc->emac_ifp, "watchdog timeout -- resetting\n");
467 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
468 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
469 emac_init_locked(sc);
470 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
471 emac_start_locked(ifp);
477 struct emac_softc *sc;
478 struct mii_data *mii;
480 sc = (struct emac_softc *)arg;
481 mii = device_get_softc(sc->emac_miibus);
485 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc);
491 struct emac_softc *sc;
493 sc = (struct emac_softc *)xcs;
495 emac_init_locked(sc);
500 emac_init_locked(struct emac_softc *sc)
503 struct mii_data *mii;
507 EMAC_ASSERT_LOCKED(sc);
510 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
514 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL);
515 reg_val |= EMAC_RX_FLUSH_FIFO;
516 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
520 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0);
521 reg_val &= (~EMAC_MAC_CTL0_SOFT_RST);
522 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val);
525 reg_val = EMAC_READ_REG(sc, EMAC_MAC_MCFG);
526 reg_val &= (~(0xf << 2));
527 reg_val |= (0xd << 2);
528 EMAC_WRITE_REG(sc, EMAC_MAC_MCFG, reg_val);
530 /* Clear RX counter */
531 EMAC_WRITE_REG(sc, EMAC_RX_FBC, 0);
533 /* Disable all interrupt and clear interrupt status */
534 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0);
535 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA);
536 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
540 reg_val = EMAC_READ_REG(sc, EMAC_TX_MODE);
541 reg_val |= EMAC_TX_AB_M;
542 reg_val &= EMAC_TX_TM;
543 EMAC_WRITE_REG(sc, EMAC_TX_MODE, reg_val);
546 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL);
547 reg_val |= EMAC_RX_SETUP;
548 reg_val &= EMAC_RX_TM;
549 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
551 /* Set up MAC CTL0. */
552 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0);
553 reg_val |= EMAC_MAC_CTL0_SETUP;
554 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val);
556 /* Set up MAC CTL1. */
557 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL1);
558 reg_val |= EMAC_MAC_CTL1_SETUP;
559 EMAC_WRITE_REG(sc, EMAC_MAC_CTL1, reg_val);
562 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, EMAC_MAC_IPGT_FD);
565 EMAC_WRITE_REG(sc, EMAC_MAC_IPGR, EMAC_MAC_NBTB_IPG2 |
566 (EMAC_MAC_NBTB_IPG1 << 8));
568 /* Set up Collison window */
569 EMAC_WRITE_REG(sc, EMAC_MAC_CLRT, EMAC_MAC_RM | (EMAC_MAC_CW << 8));
571 /* Set up Max Frame Length */
572 EMAC_WRITE_REG(sc, EMAC_MAC_MAXF, EMAC_MAC_MFL);
574 /* Setup ethernet address */
575 eaddr = IF_LLADDR(ifp);
576 EMAC_WRITE_REG(sc, EMAC_MAC_A1, eaddr[0] << 16 |
577 eaddr[1] << 8 | eaddr[2]);
578 EMAC_WRITE_REG(sc, EMAC_MAC_A0, eaddr[3] << 16 |
579 eaddr[4] << 8 | eaddr[5]);
581 /* Setup rx filter */
582 emac_set_rx_mode(sc);
584 /* Enable RX/TX0/RX Hlevel interrupt */
585 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL);
586 reg_val |= EMAC_INT_EN;
587 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val);
589 ifp->if_drv_flags |= IFF_DRV_RUNNING;
590 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
594 /* Switch to the current media. */
595 mii = device_get_softc(sc->emac_miibus);
598 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc);
603 emac_start(struct ifnet *ifp)
605 struct emac_softc *sc;
609 emac_start_locked(ifp);
614 emac_start_locked(struct ifnet *ifp)
616 struct emac_softc *sc;
621 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
623 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1))
625 if (sc->emac_link == 0)
627 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
632 if (sc->emac_fifo_mask & EMAC_TX_FIFO0)
636 sc->emac_fifo_mask |= (1 << fifo);
637 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1))
638 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
639 EMAC_WRITE_REG(sc, EMAC_TX_INS, fifo);
642 * Emac controller wants 4 byte aligned TX buffers.
643 * We have to copy pretty much all the time.
645 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0) {
646 m0 = m_defrag(m, M_NOWAIT);
655 bus_space_write_multi_4(sc->emac_tag, sc->emac_handle,
656 EMAC_TX_IO_DATA, mtod(m, uint32_t *),
657 roundup2(m->m_len, 4) / 4);
659 /* Send the data lengh. */
660 reg = (fifo == 0) ? EMAC_TX_PL0 : EMAC_TX_PL1;
661 EMAC_WRITE_REG(sc, reg, m->m_len);
663 /* Start translate from fifo to phy. */
664 reg = (fifo == 0) ? EMAC_TX_CTL0 : EMAC_TX_CTL1;
665 EMAC_WRITE_REG(sc, reg, EMAC_READ_REG(sc, reg) | 1);
668 sc->emac_watchdog_timer = 5;
670 /* Data have been sent to hardware, it is okay to free the mbuf now. */
676 emac_stop_locked(struct emac_softc *sc)
681 EMAC_ASSERT_LOCKED(sc);
684 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
687 /* Disable all interrupt and clear interrupt status */
688 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0);
689 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA);
690 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
693 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
694 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN);
695 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
697 callout_stop(&sc->emac_tick_ch);
703 struct emac_softc *sc;
707 sc = (struct emac_softc *)arg;
710 /* Disable all interrupts */
711 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0);
712 /* Get EMAC interrupt status */
713 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA);
714 /* Clear ISR status */
715 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
717 /* Received incoming packet */
718 if (reg_val & EMAC_INT_STA_RX)
719 emac_rxeof(sc, sc->emac_rx_process_limit);
721 /* Transmit Interrupt check */
722 if (reg_val & EMAC_INT_STA_TX) {
723 emac_txeof(sc, reg_val);
725 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
726 emac_start_locked(ifp);
729 /* Re-enable interrupt mask */
730 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL);
731 reg_val |= EMAC_INT_EN;
732 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val);
737 emac_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
739 struct emac_softc *sc;
740 struct mii_data *mii;
745 ifr = (struct ifreq *)data;
750 if (ifp->if_flags & IFF_UP) {
751 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
752 if ((ifp->if_flags ^ sc->emac_if_flags) &
753 (IFF_PROMISC | IFF_ALLMULTI))
754 emac_set_rx_mode(sc);
756 emac_init_locked(sc);
758 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
759 emac_stop_locked(sc);
761 sc->emac_if_flags = ifp->if_flags;
767 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
768 emac_set_rx_mode(sc);
774 mii = device_get_softc(sc->emac_miibus);
775 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
778 error = ether_ioctl(ifp, command, data);
785 emac_probe(device_t dev)
788 if (!ofw_bus_status_okay(dev))
791 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-emac"))
794 device_set_desc(dev, "A10/A20 EMAC ethernet controller");
795 return (BUS_PROBE_DEFAULT);
799 emac_detach(device_t dev)
801 struct emac_softc *sc;
803 sc = device_get_softc(dev);
804 sc->emac_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
805 if (device_is_attached(dev)) {
806 ether_ifdetach(sc->emac_ifp);
808 emac_stop_locked(sc);
810 callout_drain(&sc->emac_tick_ch);
813 if (sc->emac_intrhand != NULL)
814 bus_teardown_intr(sc->emac_dev, sc->emac_irq,
817 if (sc->emac_miibus != NULL) {
818 device_delete_child(sc->emac_dev, sc->emac_miibus);
819 bus_generic_detach(sc->emac_dev);
822 if (sc->emac_clk != NULL)
823 clk_disable(sc->emac_clk);
825 if (sc->emac_res != NULL)
826 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->emac_res);
828 if (sc->emac_irq != NULL)
829 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->emac_irq);
831 if (sc->emac_ifp != NULL)
832 if_free(sc->emac_ifp);
834 if (mtx_initialized(&sc->emac_mtx))
835 mtx_destroy(&sc->emac_mtx);
841 emac_shutdown(device_t dev)
844 return (emac_suspend(dev));
848 emac_suspend(device_t dev)
850 struct emac_softc *sc;
853 sc = device_get_softc(dev);
857 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
858 emac_stop_locked(sc);
865 emac_resume(device_t dev)
867 struct emac_softc *sc;
870 sc = device_get_softc(dev);
874 if ((ifp->if_flags & IFF_UP) != 0) {
875 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
876 emac_init_locked(sc);
884 emac_attach(device_t dev)
886 struct emac_softc *sc;
889 uint8_t eaddr[ETHER_ADDR_LEN];
891 sc = device_get_softc(dev);
895 mtx_init(&sc->emac_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
897 callout_init_mtx(&sc->emac_tick_ch, &sc->emac_mtx, 0);
900 sc->emac_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
902 if (sc->emac_res == NULL) {
903 device_printf(dev, "unable to map memory\n");
908 sc->emac_tag = rman_get_bustag(sc->emac_res);
909 sc->emac_handle = rman_get_bushandle(sc->emac_res);
912 sc->emac_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
913 RF_SHAREABLE | RF_ACTIVE);
914 if (sc->emac_irq == NULL) {
915 device_printf(dev, "cannot allocate IRQ resources.\n");
919 /* Create device sysctl node. */
920 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
921 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
922 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW,
923 &sc->emac_rx_process_limit, 0, sysctl_hw_emac_proc_limit, "I",
924 "max number of Rx events to process");
926 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT;
927 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
928 "process_limit", &sc->emac_rx_process_limit);
930 if (sc->emac_rx_process_limit < EMAC_PROC_MIN ||
931 sc->emac_rx_process_limit > EMAC_PROC_MAX) {
932 device_printf(dev, "process_limit value out of range; "
933 "using default: %d\n", EMAC_PROC_DEFAULT);
934 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT;
938 error = emac_sys_setup(sc);
944 ifp = sc->emac_ifp = if_alloc(IFT_ETHER);
946 device_printf(dev, "unable to allocate ifp\n");
953 error = mii_attach(dev, &sc->emac_miibus, ifp, emac_ifmedia_upd,
954 emac_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
956 device_printf(dev, "PHY probe failed\n");
960 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
961 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
962 ifp->if_start = emac_start;
963 ifp->if_ioctl = emac_ioctl;
964 ifp->if_init = emac_init;
965 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
967 /* Get MAC address */
968 emac_get_hwaddr(sc, eaddr);
969 ether_ifattach(ifp, eaddr);
971 /* VLAN capability setup. */
972 ifp->if_capabilities |= IFCAP_VLAN_MTU;
973 ifp->if_capenable = ifp->if_capabilities;
974 /* Tell the upper layer we support VLAN over-sized frames. */
975 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
977 error = bus_setup_intr(dev, sc->emac_irq, INTR_TYPE_NET | INTR_MPSAFE,
978 NULL, emac_intr, sc, &sc->emac_intrhand);
980 device_printf(dev, "could not set up interrupt handler.\n");
992 emac_miibus_iowait(struct emac_softc *sc)
996 for (timeout = 100; timeout != 0; --timeout) {
998 if ((EMAC_READ_REG(sc, EMAC_MAC_MIND) & 0x1) == 0)
1006 * The MII bus interface
1009 emac_miibus_readreg(device_t dev, int phy, int reg)
1011 struct emac_softc *sc;
1014 sc = device_get_softc(dev);
1016 /* Issue phy address and reg */
1017 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg);
1018 /* Pull up the phy io line */
1019 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1);
1020 if (!emac_miibus_iowait(sc)) {
1021 device_printf(dev, "timeout waiting for mii read\n");
1024 /* Push down the phy io line */
1025 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0);
1027 rval = EMAC_READ_REG(sc, EMAC_MAC_MRDD);
1033 emac_miibus_writereg(device_t dev, int phy, int reg, int data)
1035 struct emac_softc *sc;
1037 sc = device_get_softc(dev);
1039 /* Issue phy address and reg */
1040 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg);
1042 EMAC_WRITE_REG(sc, EMAC_MAC_MWTD, data);
1043 /* Pull up the phy io line */
1044 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1);
1045 if (!emac_miibus_iowait(sc)) {
1046 device_printf(dev, "timeout waiting for mii write\n");
1049 /* Push down the phy io line */
1050 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0);
1056 emac_miibus_statchg(device_t dev)
1058 struct emac_softc *sc;
1059 struct mii_data *mii;
1063 sc = device_get_softc(dev);
1065 mii = device_get_softc(sc->emac_miibus);
1067 if (mii == NULL || ifp == NULL ||
1068 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1072 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1073 (IFM_ACTIVE | IFM_AVALID)) {
1074 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1083 /* Program MACs with resolved speed/duplex. */
1084 if (sc->emac_link != 0) {
1085 reg_val = EMAC_READ_REG(sc, EMAC_MAC_IPGT);
1086 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1087 reg_val &= ~EMAC_MAC_IPGT_HD;
1088 reg_val |= EMAC_MAC_IPGT_FD;
1090 reg_val &= ~EMAC_MAC_IPGT_FD;
1091 reg_val |= EMAC_MAC_IPGT_HD;
1093 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, reg_val);
1095 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
1096 reg_val |= EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN;
1097 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
1100 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
1101 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN);
1102 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
1107 emac_ifmedia_upd(struct ifnet *ifp)
1109 struct emac_softc *sc;
1110 struct mii_data *mii;
1111 struct mii_softc *miisc;
1115 mii = device_get_softc(sc->emac_miibus);
1117 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1119 error = mii_mediachg(mii);
1126 emac_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1128 struct emac_softc *sc;
1129 struct mii_data *mii;
1132 mii = device_get_softc(sc->emac_miibus);
1136 ifmr->ifm_active = mii->mii_media_active;
1137 ifmr->ifm_status = mii->mii_media_status;
1141 static device_method_t emac_methods[] = {
1142 /* Device interface */
1143 DEVMETHOD(device_probe, emac_probe),
1144 DEVMETHOD(device_attach, emac_attach),
1145 DEVMETHOD(device_detach, emac_detach),
1146 DEVMETHOD(device_shutdown, emac_shutdown),
1147 DEVMETHOD(device_suspend, emac_suspend),
1148 DEVMETHOD(device_resume, emac_resume),
1150 /* bus interface, for miibus */
1151 DEVMETHOD(bus_print_child, bus_generic_print_child),
1152 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
1155 DEVMETHOD(miibus_readreg, emac_miibus_readreg),
1156 DEVMETHOD(miibus_writereg, emac_miibus_writereg),
1157 DEVMETHOD(miibus_statchg, emac_miibus_statchg),
1162 static driver_t emac_driver = {
1165 sizeof(struct emac_softc)
1168 static devclass_t emac_devclass;
1170 DRIVER_MODULE(emac, simplebus, emac_driver, emac_devclass, 0, 0);
1171 DRIVER_MODULE(miibus, emac, miibus_driver, miibus_devclass, 0, 0);
1172 MODULE_DEPEND(emac, miibus, 1, 1, 1);
1173 MODULE_DEPEND(emac, ether, 1, 1, 1);
1176 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
1182 value = *(int *)arg1;
1183 error = sysctl_handle_int(oidp, &value, 0, req);
1184 if (error || req->newptr == NULL)
1186 if (value < low || value > high)
1188 *(int *)arg1 = value;
1194 sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS)
1197 return (sysctl_int_range(oidp, arg1, arg2, req,
1198 EMAC_PROC_MIN, EMAC_PROC_MAX));