2 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 /* A10/A20 EMAC driver */
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/module.h>
41 #include <sys/mutex.h>
43 #include <sys/socket.h>
44 #include <sys/sockio.h>
45 #include <sys/sysctl.h>
48 #include <machine/bus.h>
49 #include <machine/resource.h>
50 #include <machine/intr.h>
53 #include <net/if_var.h>
54 #include <net/if_arp.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/if_types.h>
58 #include <net/if_mib.h>
59 #include <net/ethernet.h>
60 #include <net/if_vlan_var.h>
63 #include <netinet/in.h>
64 #include <netinet/in_systm.h>
65 #include <netinet/in_var.h>
66 #include <netinet/ip.h>
70 #include <net/bpfdesc.h>
72 #include <dev/fdt/fdt_common.h>
73 #include <dev/ofw/ofw_bus.h>
74 #include <dev/ofw/ofw_bus_subr.h>
76 #include <dev/mii/mii.h>
77 #include <dev/mii/miivar.h>
79 #include <arm/allwinner/if_emacreg.h>
81 #include <dev/extres/clk/clk.h>
83 #include "miibus_if.h"
87 #include "a10_sramc.h"
90 struct ifnet *emac_ifp;
93 bus_space_handle_t emac_handle;
94 bus_space_tag_t emac_tag;
95 struct resource *emac_res;
96 struct resource *emac_irq;
101 struct callout emac_tick_ch;
102 int emac_watchdog_timer;
103 int emac_rx_process_limit;
105 uint32_t emac_fifo_mask;
108 static int emac_probe(device_t);
109 static int emac_attach(device_t);
110 static int emac_detach(device_t);
111 static int emac_shutdown(device_t);
112 static int emac_suspend(device_t);
113 static int emac_resume(device_t);
115 static int emac_sys_setup(struct emac_softc *);
116 static void emac_reset(struct emac_softc *);
118 static void emac_init_locked(struct emac_softc *);
119 static void emac_start_locked(struct ifnet *);
120 static void emac_init(void *);
121 static void emac_stop_locked(struct emac_softc *);
122 static void emac_intr(void *);
123 static int emac_ioctl(struct ifnet *, u_long, caddr_t);
125 static void emac_rxeof(struct emac_softc *, int);
126 static void emac_txeof(struct emac_softc *, uint32_t);
128 static int emac_miibus_readreg(device_t, int, int);
129 static int emac_miibus_writereg(device_t, int, int, int);
130 static void emac_miibus_statchg(device_t);
132 static int emac_ifmedia_upd(struct ifnet *);
133 static void emac_ifmedia_sts(struct ifnet *, struct ifmediareq *);
135 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
136 static int sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS);
138 #define EMAC_READ_REG(sc, reg) \
139 bus_space_read_4(sc->emac_tag, sc->emac_handle, reg)
140 #define EMAC_WRITE_REG(sc, reg, val) \
141 bus_space_write_4(sc->emac_tag, sc->emac_handle, reg, val)
144 emac_sys_setup(struct emac_softc *sc)
148 /* Activate EMAC clock. */
149 error = clk_get_by_ofw_index(sc->emac_dev, 0, &sc->emac_clk);
151 device_printf(sc->emac_dev, "cannot get clock\n");
154 error = clk_enable(sc->emac_clk);
156 device_printf(sc->emac_dev, "cannot enable clock\n");
167 emac_get_hwaddr(struct emac_softc *sc, uint8_t *hwaddr)
169 uint32_t val0, val1, rnd;
172 * Try to get MAC address from running hardware.
173 * If there is something non-zero there just use it.
175 * Otherwise set the address to a convenient locally assigned address,
176 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally
177 * assigned bit set, and the broadcast/multicast bit clear.
179 val0 = EMAC_READ_REG(sc, EMAC_MAC_A0);
180 val1 = EMAC_READ_REG(sc, EMAC_MAC_A1);
181 if ((val0 | val1) != 0 && (val0 | val1) != 0xffffff) {
182 hwaddr[0] = (val1 >> 16) & 0xff;
183 hwaddr[1] = (val1 >> 8) & 0xff;
184 hwaddr[2] = (val1 >> 0) & 0xff;
185 hwaddr[3] = (val0 >> 16) & 0xff;
186 hwaddr[4] = (val0 >> 8) & 0xff;
187 hwaddr[5] = (val0 >> 0) & 0xff;
189 rnd = arc4random() & 0x00ffffff;
193 hwaddr[3] = (rnd >> 16) & 0xff;
194 hwaddr[4] = (rnd >> 8) & 0xff;
195 hwaddr[5] = (rnd >> 0) & 0xff;
198 printf("MAC address: %s\n", ether_sprintf(hwaddr));
202 emac_set_rx_mode(struct emac_softc *sc)
205 struct ifmultiaddr *ifma;
206 uint32_t h, hashes[2];
209 EMAC_ASSERT_LOCKED(sc);
213 rcr = EMAC_READ_REG(sc, EMAC_RX_CTL);
215 /* Unicast packet and DA filtering */
221 if (ifp->if_flags & IFF_ALLMULTI) {
222 hashes[0] = 0xffffffff;
223 hashes[1] = 0xffffffff;
226 TAILQ_FOREACH(ifma, &sc->emac_ifp->if_multiaddrs, ifma_link) {
227 if (ifma->ifma_addr->sa_family != AF_LINK)
229 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
230 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
231 hashes[h >> 5] |= 1 << (h & 0x1f);
233 if_maddr_runlock(ifp);
237 EMAC_WRITE_REG(sc, EMAC_RX_HASH0, hashes[0]);
238 EMAC_WRITE_REG(sc, EMAC_RX_HASH1, hashes[1]);
240 if (ifp->if_flags & IFF_BROADCAST) {
245 if (ifp->if_flags & IFF_PROMISC)
250 EMAC_WRITE_REG(sc, EMAC_RX_CTL, rcr);
254 emac_reset(struct emac_softc *sc)
257 EMAC_WRITE_REG(sc, EMAC_CTL, 0);
259 EMAC_WRITE_REG(sc, EMAC_CTL, 1);
264 emac_drain_rxfifo(struct emac_softc *sc)
268 while (EMAC_READ_REG(sc, EMAC_RX_FBC) > 0)
269 data = EMAC_READ_REG(sc, EMAC_RX_IO_DATA);
273 emac_txeof(struct emac_softc *sc, uint32_t status)
277 EMAC_ASSERT_LOCKED(sc);
280 status &= (EMAC_TX_FIFO0 | EMAC_TX_FIFO1);
281 sc->emac_fifo_mask &= ~status;
282 if (status == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1))
283 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 2);
285 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
286 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
288 /* Unarm watchdog timer if no TX */
289 sc->emac_watchdog_timer = 0;
293 emac_rxeof(struct emac_softc *sc, int count)
297 uint32_t reg_val, rxcount;
304 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; count--) {
306 * Race warning: The first packet might arrive with
307 * the interrupts disabled, but the second will fix
309 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC);
312 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC);
316 /* Check packet header */
317 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA);
318 if (reg_val != EMAC_PACKET_HEADER) {
319 /* Packet header is wrong */
321 if_printf(ifp, "wrong packet header\n");
323 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
324 reg_val &= ~EMAC_CTL_RX_EN;
325 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
328 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL);
329 reg_val |= EMAC_RX_FLUSH_FIFO;
330 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
331 for (i = 100; i > 0; i--) {
333 if ((EMAC_READ_REG(sc, EMAC_RX_CTL) &
334 EMAC_RX_FLUSH_FIFO) == 0)
338 device_printf(sc->emac_dev,
339 "flush FIFO timeout\n");
340 /* Reinitialize controller */
341 emac_init_locked(sc);
345 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
346 reg_val |= EMAC_CTL_RX_EN;
347 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
352 /* Get packet size and status */
353 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA);
354 len = reg_val & 0xffff;
355 status = (reg_val >> 16) & 0xffff;
357 if (len < 64 || (status & EMAC_PKT_OK) == 0) {
360 "bad packet: len = %i status = %i\n",
362 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
363 emac_drain_rxfifo(sc);
367 if (status & (EMAC_CRCERR | EMAC_LENERR)) {
369 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
370 if (status & EMAC_CRCERR)
371 if_printf(ifp, "crc error\n");
372 if (status & EMAC_LENERR)
373 if_printf(ifp, "length error\n");
376 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
378 emac_drain_rxfifo(sc);
381 m->m_len = m->m_pkthdr.len = MCLBYTES;
383 /* Copy entire frame to mbuf first. */
384 bus_space_read_multi_4(sc->emac_tag, sc->emac_handle,
385 EMAC_RX_IO_DATA, mtod(m, uint32_t *), roundup2(len, 4) / 4);
387 m->m_pkthdr.rcvif = ifp;
388 m->m_len = m->m_pkthdr.len = len - ETHER_CRC_LEN;
391 * Emac controller needs strict aligment, so to avoid
392 * copying over an entire frame to align, we allocate
393 * a new mbuf and copy ethernet header + IP header to
394 * the new mbuf. The new mbuf is prepended into the
395 * existing mbuf chain.
397 if (m->m_len <= (MHLEN - ETHER_HDR_LEN)) {
398 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
399 m->m_data += ETHER_HDR_LEN;
400 } else if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN) &&
401 m->m_len > (MHLEN - ETHER_HDR_LEN)) {
402 MGETHDR(m0, M_NOWAIT, MT_DATA);
404 len = ETHER_HDR_LEN + m->m_pkthdr.l2hlen;
405 bcopy(m->m_data, m0->m_data, len);
409 M_MOVE_PKTHDR(m0, m);
413 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
418 } else if (m->m_len > EMAC_MAC_MAXF) {
419 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
424 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
426 (*ifp->if_input)(ifp, m);
432 emac_watchdog(struct emac_softc *sc)
436 EMAC_ASSERT_LOCKED(sc);
438 if (sc->emac_watchdog_timer == 0 || --sc->emac_watchdog_timer)
443 if (sc->emac_link == 0) {
445 if_printf(sc->emac_ifp, "watchdog timeout "
448 if_printf(sc->emac_ifp, "watchdog timeout -- resetting\n");
450 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
451 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
452 emac_init_locked(sc);
453 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
454 emac_start_locked(ifp);
460 struct emac_softc *sc;
461 struct mii_data *mii;
463 sc = (struct emac_softc *)arg;
464 mii = device_get_softc(sc->emac_miibus);
468 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc);
474 struct emac_softc *sc;
476 sc = (struct emac_softc *)xcs;
478 emac_init_locked(sc);
483 emac_init_locked(struct emac_softc *sc)
486 struct mii_data *mii;
490 EMAC_ASSERT_LOCKED(sc);
493 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
497 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL);
498 reg_val |= EMAC_RX_FLUSH_FIFO;
499 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
503 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0);
504 reg_val &= (~EMAC_MAC_CTL0_SOFT_RST);
505 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val);
508 reg_val = EMAC_READ_REG(sc, EMAC_MAC_MCFG);
509 reg_val &= (~(0xf << 2));
510 reg_val |= (0xd << 2);
511 EMAC_WRITE_REG(sc, EMAC_MAC_MCFG, reg_val);
513 /* Clear RX counter */
514 EMAC_WRITE_REG(sc, EMAC_RX_FBC, 0);
516 /* Disable all interrupt and clear interrupt status */
517 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0);
518 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA);
519 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
523 reg_val = EMAC_READ_REG(sc, EMAC_TX_MODE);
524 reg_val |= EMAC_TX_AB_M;
525 reg_val &= EMAC_TX_TM;
526 EMAC_WRITE_REG(sc, EMAC_TX_MODE, reg_val);
529 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL);
530 reg_val |= EMAC_RX_SETUP;
531 reg_val &= EMAC_RX_TM;
532 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val);
534 /* Set up MAC CTL0. */
535 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0);
536 reg_val |= EMAC_MAC_CTL0_SETUP;
537 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val);
539 /* Set up MAC CTL1. */
540 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL1);
541 reg_val |= EMAC_MAC_CTL1_SETUP;
542 EMAC_WRITE_REG(sc, EMAC_MAC_CTL1, reg_val);
545 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, EMAC_MAC_IPGT_FD);
548 EMAC_WRITE_REG(sc, EMAC_MAC_IPGR, EMAC_MAC_NBTB_IPG2 |
549 (EMAC_MAC_NBTB_IPG1 << 8));
551 /* Set up Collison window */
552 EMAC_WRITE_REG(sc, EMAC_MAC_CLRT, EMAC_MAC_RM | (EMAC_MAC_CW << 8));
554 /* Set up Max Frame Length */
555 EMAC_WRITE_REG(sc, EMAC_MAC_MAXF, EMAC_MAC_MFL);
557 /* Setup ethernet address */
558 eaddr = IF_LLADDR(ifp);
559 EMAC_WRITE_REG(sc, EMAC_MAC_A1, eaddr[0] << 16 |
560 eaddr[1] << 8 | eaddr[2]);
561 EMAC_WRITE_REG(sc, EMAC_MAC_A0, eaddr[3] << 16 |
562 eaddr[4] << 8 | eaddr[5]);
564 /* Setup rx filter */
565 emac_set_rx_mode(sc);
567 /* Enable RX/TX0/RX Hlevel interrupt */
568 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL);
569 reg_val |= EMAC_INT_EN;
570 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val);
572 ifp->if_drv_flags |= IFF_DRV_RUNNING;
573 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
577 /* Switch to the current media. */
578 mii = device_get_softc(sc->emac_miibus);
581 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc);
586 emac_start(struct ifnet *ifp)
588 struct emac_softc *sc;
592 emac_start_locked(ifp);
597 emac_start_locked(struct ifnet *ifp)
599 struct emac_softc *sc;
604 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
606 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1))
608 if (sc->emac_link == 0)
610 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
615 if (sc->emac_fifo_mask & EMAC_TX_FIFO0)
619 sc->emac_fifo_mask |= (1 << fifo);
620 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1))
621 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
622 EMAC_WRITE_REG(sc, EMAC_TX_INS, fifo);
625 * Emac controller wants 4 byte aligned TX buffers.
626 * We have to copy pretty much all the time.
628 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0) {
629 m0 = m_defrag(m, M_NOWAIT);
638 bus_space_write_multi_4(sc->emac_tag, sc->emac_handle,
639 EMAC_TX_IO_DATA, mtod(m, uint32_t *),
640 roundup2(m->m_len, 4) / 4);
642 /* Send the data lengh. */
643 reg = (fifo == 0) ? EMAC_TX_PL0 : EMAC_TX_PL1;
644 EMAC_WRITE_REG(sc, reg, m->m_len);
646 /* Start translate from fifo to phy. */
647 reg = (fifo == 0) ? EMAC_TX_CTL0 : EMAC_TX_CTL1;
648 EMAC_WRITE_REG(sc, reg, EMAC_READ_REG(sc, reg) | 1);
651 sc->emac_watchdog_timer = 5;
653 /* Data have been sent to hardware, it is okay to free the mbuf now. */
659 emac_stop_locked(struct emac_softc *sc)
664 EMAC_ASSERT_LOCKED(sc);
667 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
670 /* Disable all interrupt and clear interrupt status */
671 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0);
672 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA);
673 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
676 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
677 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN);
678 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
680 callout_stop(&sc->emac_tick_ch);
686 struct emac_softc *sc;
690 sc = (struct emac_softc *)arg;
693 /* Disable all interrupts */
694 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0);
695 /* Get EMAC interrupt status */
696 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA);
697 /* Clear ISR status */
698 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val);
700 /* Received incoming packet */
701 if (reg_val & EMAC_INT_STA_RX)
702 emac_rxeof(sc, sc->emac_rx_process_limit);
704 /* Transmit Interrupt check */
705 if (reg_val & EMAC_INT_STA_TX) {
706 emac_txeof(sc, reg_val);
708 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
709 emac_start_locked(ifp);
712 /* Re-enable interrupt mask */
713 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL);
714 reg_val |= EMAC_INT_EN;
715 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val);
720 emac_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
722 struct emac_softc *sc;
723 struct mii_data *mii;
728 ifr = (struct ifreq *)data;
733 if (ifp->if_flags & IFF_UP) {
734 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
735 if ((ifp->if_flags ^ sc->emac_if_flags) &
736 (IFF_PROMISC | IFF_ALLMULTI))
737 emac_set_rx_mode(sc);
739 emac_init_locked(sc);
741 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
742 emac_stop_locked(sc);
744 sc->emac_if_flags = ifp->if_flags;
750 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
751 emac_set_rx_mode(sc);
757 mii = device_get_softc(sc->emac_miibus);
758 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
761 error = ether_ioctl(ifp, command, data);
768 emac_probe(device_t dev)
771 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-emac"))
774 device_set_desc(dev, "A10/A20 EMAC ethernet controller");
775 return (BUS_PROBE_DEFAULT);
779 emac_detach(device_t dev)
781 struct emac_softc *sc;
783 sc = device_get_softc(dev);
784 sc->emac_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
785 if (device_is_attached(dev)) {
786 ether_ifdetach(sc->emac_ifp);
788 emac_stop_locked(sc);
790 callout_drain(&sc->emac_tick_ch);
793 if (sc->emac_intrhand != NULL)
794 bus_teardown_intr(sc->emac_dev, sc->emac_irq,
797 if (sc->emac_miibus != NULL) {
798 device_delete_child(sc->emac_dev, sc->emac_miibus);
799 bus_generic_detach(sc->emac_dev);
802 if (sc->emac_clk != NULL)
803 clk_disable(sc->emac_clk);
805 if (sc->emac_res != NULL)
806 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->emac_res);
808 if (sc->emac_irq != NULL)
809 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->emac_irq);
811 if (sc->emac_ifp != NULL)
812 if_free(sc->emac_ifp);
814 if (mtx_initialized(&sc->emac_mtx))
815 mtx_destroy(&sc->emac_mtx);
821 emac_shutdown(device_t dev)
824 return (emac_suspend(dev));
828 emac_suspend(device_t dev)
830 struct emac_softc *sc;
833 sc = device_get_softc(dev);
837 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
838 emac_stop_locked(sc);
845 emac_resume(device_t dev)
847 struct emac_softc *sc;
850 sc = device_get_softc(dev);
854 if ((ifp->if_flags & IFF_UP) != 0) {
855 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
856 emac_init_locked(sc);
864 emac_attach(device_t dev)
866 struct emac_softc *sc;
869 uint8_t eaddr[ETHER_ADDR_LEN];
871 sc = device_get_softc(dev);
875 mtx_init(&sc->emac_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
877 callout_init_mtx(&sc->emac_tick_ch, &sc->emac_mtx, 0);
880 sc->emac_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
882 if (sc->emac_res == NULL) {
883 device_printf(dev, "unable to map memory\n");
888 sc->emac_tag = rman_get_bustag(sc->emac_res);
889 sc->emac_handle = rman_get_bushandle(sc->emac_res);
892 sc->emac_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
893 RF_SHAREABLE | RF_ACTIVE);
894 if (sc->emac_irq == NULL) {
895 device_printf(dev, "cannot allocate IRQ resources.\n");
899 /* Create device sysctl node. */
900 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
901 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
902 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW,
903 &sc->emac_rx_process_limit, 0, sysctl_hw_emac_proc_limit, "I",
904 "max number of Rx events to process");
906 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT;
907 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
908 "process_limit", &sc->emac_rx_process_limit);
910 if (sc->emac_rx_process_limit < EMAC_PROC_MIN ||
911 sc->emac_rx_process_limit > EMAC_PROC_MAX) {
912 device_printf(dev, "process_limit value out of range; "
913 "using default: %d\n", EMAC_PROC_DEFAULT);
914 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT;
918 error = emac_sys_setup(sc);
924 ifp = sc->emac_ifp = if_alloc(IFT_ETHER);
926 device_printf(dev, "unable to allocate ifp\n");
933 error = mii_attach(dev, &sc->emac_miibus, ifp, emac_ifmedia_upd,
934 emac_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
936 device_printf(dev, "PHY probe failed\n");
940 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
941 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
942 ifp->if_start = emac_start;
943 ifp->if_ioctl = emac_ioctl;
944 ifp->if_init = emac_init;
945 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
947 /* Get MAC address */
948 emac_get_hwaddr(sc, eaddr);
949 ether_ifattach(ifp, eaddr);
951 /* VLAN capability setup. */
952 ifp->if_capabilities |= IFCAP_VLAN_MTU;
953 ifp->if_capenable = ifp->if_capabilities;
954 /* Tell the upper layer we support VLAN over-sized frames. */
955 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
957 error = bus_setup_intr(dev, sc->emac_irq, INTR_TYPE_NET | INTR_MPSAFE,
958 NULL, emac_intr, sc, &sc->emac_intrhand);
960 device_printf(dev, "could not set up interrupt handler.\n");
972 emac_miibus_iowait(struct emac_softc *sc)
976 for (timeout = 100; timeout != 0; --timeout) {
978 if ((EMAC_READ_REG(sc, EMAC_MAC_MIND) & 0x1) == 0)
986 * The MII bus interface
989 emac_miibus_readreg(device_t dev, int phy, int reg)
991 struct emac_softc *sc;
994 sc = device_get_softc(dev);
996 /* Issue phy address and reg */
997 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg);
998 /* Pull up the phy io line */
999 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1);
1000 if (!emac_miibus_iowait(sc)) {
1001 device_printf(dev, "timeout waiting for mii read\n");
1004 /* Push down the phy io line */
1005 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0);
1007 rval = EMAC_READ_REG(sc, EMAC_MAC_MRDD);
1013 emac_miibus_writereg(device_t dev, int phy, int reg, int data)
1015 struct emac_softc *sc;
1017 sc = device_get_softc(dev);
1019 /* Issue phy address and reg */
1020 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg);
1022 EMAC_WRITE_REG(sc, EMAC_MAC_MWTD, data);
1023 /* Pull up the phy io line */
1024 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1);
1025 if (!emac_miibus_iowait(sc)) {
1026 device_printf(dev, "timeout waiting for mii write\n");
1029 /* Push down the phy io line */
1030 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0);
1036 emac_miibus_statchg(device_t dev)
1038 struct emac_softc *sc;
1039 struct mii_data *mii;
1043 sc = device_get_softc(dev);
1045 mii = device_get_softc(sc->emac_miibus);
1047 if (mii == NULL || ifp == NULL ||
1048 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1052 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1053 (IFM_ACTIVE | IFM_AVALID)) {
1054 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1063 /* Program MACs with resolved speed/duplex. */
1064 if (sc->emac_link != 0) {
1065 reg_val = EMAC_READ_REG(sc, EMAC_MAC_IPGT);
1066 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1067 reg_val &= ~EMAC_MAC_IPGT_HD;
1068 reg_val |= EMAC_MAC_IPGT_FD;
1070 reg_val &= ~EMAC_MAC_IPGT_FD;
1071 reg_val |= EMAC_MAC_IPGT_HD;
1073 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, reg_val);
1075 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
1076 reg_val |= EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN;
1077 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
1080 reg_val = EMAC_READ_REG(sc, EMAC_CTL);
1081 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN);
1082 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val);
1087 emac_ifmedia_upd(struct ifnet *ifp)
1089 struct emac_softc *sc;
1090 struct mii_data *mii;
1091 struct mii_softc *miisc;
1095 mii = device_get_softc(sc->emac_miibus);
1097 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1099 error = mii_mediachg(mii);
1106 emac_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1108 struct emac_softc *sc;
1109 struct mii_data *mii;
1112 mii = device_get_softc(sc->emac_miibus);
1116 ifmr->ifm_active = mii->mii_media_active;
1117 ifmr->ifm_status = mii->mii_media_status;
1121 static device_method_t emac_methods[] = {
1122 /* Device interface */
1123 DEVMETHOD(device_probe, emac_probe),
1124 DEVMETHOD(device_attach, emac_attach),
1125 DEVMETHOD(device_detach, emac_detach),
1126 DEVMETHOD(device_shutdown, emac_shutdown),
1127 DEVMETHOD(device_suspend, emac_suspend),
1128 DEVMETHOD(device_resume, emac_resume),
1130 /* bus interface, for miibus */
1131 DEVMETHOD(bus_print_child, bus_generic_print_child),
1132 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
1135 DEVMETHOD(miibus_readreg, emac_miibus_readreg),
1136 DEVMETHOD(miibus_writereg, emac_miibus_writereg),
1137 DEVMETHOD(miibus_statchg, emac_miibus_statchg),
1142 static driver_t emac_driver = {
1145 sizeof(struct emac_softc)
1148 static devclass_t emac_devclass;
1150 DRIVER_MODULE(emac, simplebus, emac_driver, emac_devclass, 0, 0);
1151 DRIVER_MODULE(miibus, emac, miibus_driver, miibus_devclass, 0, 0);
1152 MODULE_DEPEND(emac, miibus, 1, 1, 1);
1153 MODULE_DEPEND(emac, ether, 1, 1, 1);
1156 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
1162 value = *(int *)arg1;
1163 error = sysctl_handle_int(oidp, &value, 0, req);
1164 if (error || req->newptr == NULL)
1166 if (value < low || value > high)
1168 *(int *)arg1 = value;
1174 sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS)
1177 return (sysctl_int_range(oidp, arg1, arg2, req,
1178 EMAC_PROC_MIN, EMAC_PROC_MAX));