2 * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <sys/malloc.h>
37 #include <sys/timeet.h>
38 #include <sys/timetc.h>
39 #include <sys/watchdog.h>
40 #include <machine/bus.h>
41 #include <machine/cpu.h>
42 #include <machine/intr.h>
43 #include <machine/machdep.h>
45 #include <dev/fdt/fdt_common.h>
46 #include <dev/ofw/openfirm.h>
47 #include <dev/ofw/ofw_bus.h>
48 #include <dev/ofw/ofw_bus_subr.h>
50 #include <machine/bus.h>
54 #include <arm/allwinner/aw_machdep.h>
57 * Timer registers addr
60 #define SW_TIMER_IRQ_EN_REG 0x00
61 #define SW_TIMER_IRQ_STA_REG 0x04
62 #define SW_TIMER0_CTRL_REG 0x10
63 #define SW_TIMER0_INT_VALUE_REG 0x14
64 #define SW_TIMER0_CUR_VALUE_REG 0x18
66 #define SW_COUNTER64LO_REG 0xa4
67 #define SW_COUNTER64HI_REG 0xa8
68 #define CNT64_CTRL_REG 0xa0
70 #define CNT64_RL_EN 0x02 /* read latch enable */
72 #define TIMER_ENABLE (1<<0)
73 #define TIMER_AUTORELOAD (1<<1)
74 #define TIMER_OSC24M (1<<2) /* oscillator = 24mhz */
75 #define TIMER_PRESCALAR (0<<4) /* prescalar = 1 */
77 #define SYS_TIMER_CLKSRC 24000000 /* clock source */
79 struct a10_timer_softc {
81 struct resource *res[2];
82 bus_space_tag_t sc_bst;
83 bus_space_handle_t sc_bsh;
84 void *sc_ih; /* interrupt handler */
90 int a10_timer_get_timerfreq(struct a10_timer_softc *);
92 #define timer_read_4(sc, reg) \
93 bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg)
94 #define timer_write_4(sc, reg, val) \
95 bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val)
97 static u_int a10_timer_get_timecount(struct timecounter *);
98 static int a10_timer_timer_start(struct eventtimer *,
99 sbintime_t first, sbintime_t period);
100 static int a10_timer_timer_stop(struct eventtimer *);
102 static uint64_t timer_read_counter64(void);
104 static int a10_timer_hardclock(void *);
105 static int a10_timer_probe(device_t);
106 static int a10_timer_attach(device_t);
108 static delay_func a10_timer_delay;
110 static struct timecounter a10_timer_timecounter = {
111 .tc_name = "a10_timer timer0",
112 .tc_get_timecount = a10_timer_get_timecount,
113 .tc_counter_mask = ~0u,
118 struct a10_timer_softc *a10_timer_sc = NULL;
120 static struct resource_spec a10_timer_spec[] = {
121 { SYS_RES_MEMORY, 0, RF_ACTIVE },
122 { SYS_RES_IRQ, 0, RF_ACTIVE },
127 timer_read_counter64(void)
131 /* Latch counter, wait for it to be ready to read. */
132 timer_write_4(a10_timer_sc, CNT64_CTRL_REG, CNT64_RL_EN);
133 while (timer_read_4(a10_timer_sc, CNT64_CTRL_REG) & CNT64_RL_EN)
136 hi = timer_read_4(a10_timer_sc, SW_COUNTER64HI_REG);
137 lo = timer_read_4(a10_timer_sc, SW_COUNTER64LO_REG);
139 return (((uint64_t)hi << 32) | lo);
143 a10_timer_probe(device_t dev)
145 struct a10_timer_softc *sc;
148 sc = device_get_softc(dev);
150 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-timer"))
153 soc_family = allwinner_soc_family();
154 if (soc_family != ALLWINNERSOC_SUN4I &&
155 soc_family != ALLWINNERSOC_SUN5I)
158 device_set_desc(dev, "Allwinner A10/A20 timer");
159 return (BUS_PROBE_DEFAULT);
163 a10_timer_attach(device_t dev)
165 struct a10_timer_softc *sc;
169 sc = device_get_softc(dev);
171 if (bus_alloc_resources(dev, a10_timer_spec, sc->res)) {
172 device_printf(dev, "could not allocate resources\n");
177 sc->sc_bst = rman_get_bustag(sc->res[0]);
178 sc->sc_bsh = rman_get_bushandle(sc->res[0]);
180 /* Setup and enable the timer interrupt */
181 err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, a10_timer_hardclock,
182 NULL, sc, &sc->sc_ih);
184 bus_release_resources(dev, a10_timer_spec, sc->res);
185 device_printf(dev, "Unable to setup the clock irq handler, "
190 /* Set clock source to OSC24M, 16 pre-division */
191 val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
192 val |= TIMER_PRESCALAR | TIMER_OSC24M;
193 timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
196 val = timer_read_4(sc, SW_TIMER_IRQ_EN_REG);
198 timer_write_4(sc, SW_TIMER_IRQ_EN_REG, val);
200 sc->timer0_freq = SYS_TIMER_CLKSRC;
202 /* Set desired frequency in event timer and timecounter */
203 sc->et.et_frequency = sc->timer0_freq;
204 sc->et.et_name = "a10_timer Eventtimer";
205 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC;
206 sc->et.et_quality = 1000;
207 sc->et.et_min_period = (0x00000005LLU << 32) / sc->et.et_frequency;
208 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
209 sc->et.et_start = a10_timer_timer_start;
210 sc->et.et_stop = a10_timer_timer_stop;
212 et_register(&sc->et);
214 if (device_get_unit(dev) == 0) {
215 arm_set_delay(a10_timer_delay, sc);
219 a10_timer_timecounter.tc_frequency = sc->timer0_freq;
220 tc_init(&a10_timer_timecounter);
223 device_printf(sc->sc_dev, "clock: hz=%d stathz = %d\n", hz, stathz);
225 device_printf(sc->sc_dev, "event timer clock frequency %u\n",
227 device_printf(sc->sc_dev, "timecounter clock frequency %lld\n",
228 a10_timer_timecounter.tc_frequency);
235 a10_timer_timer_start(struct eventtimer *et, sbintime_t first,
238 struct a10_timer_softc *sc;
242 sc = (struct a10_timer_softc *)et->et_priv;
245 sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32;
249 count = ((uint32_t)et->et_frequency * first) >> 32;
251 count = sc->sc_period;
253 /* Update timer values */
254 timer_write_4(sc, SW_TIMER0_INT_VALUE_REG, sc->sc_period);
255 timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, count);
257 val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
260 val |= TIMER_AUTORELOAD;
263 val &= ~TIMER_AUTORELOAD;
267 timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
273 a10_timer_timer_stop(struct eventtimer *et)
275 struct a10_timer_softc *sc;
278 sc = (struct a10_timer_softc *)et->et_priv;
281 val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
282 val &= ~TIMER_ENABLE;
283 timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
291 a10_timer_get_timerfreq(struct a10_timer_softc *sc)
293 return (sc->timer0_freq);
297 a10_timer_hardclock(void *arg)
299 struct a10_timer_softc *sc;
302 sc = (struct a10_timer_softc *)arg;
304 /* Clear interrupt pending bit. */
305 timer_write_4(sc, SW_TIMER_IRQ_STA_REG, 0x1);
307 val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
309 * Disabled autoreload and sc_period > 0 means
310 * timer_start was called with non NULL first value.
311 * Now we will set periodic timer with the given period
314 if ((val & (1<<1)) == 0 && sc->sc_period > 0) {
316 timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, sc->sc_period);
318 /* Make periodic and enable */
319 val |= TIMER_AUTORELOAD | TIMER_ENABLE;
320 timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
323 if (sc->et.et_active)
324 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
326 return (FILTER_HANDLED);
330 a10_timer_get_timecount(struct timecounter *tc)
333 if (a10_timer_sc == NULL)
336 return ((u_int)timer_read_counter64());
339 static device_method_t a10_timer_methods[] = {
340 DEVMETHOD(device_probe, a10_timer_probe),
341 DEVMETHOD(device_attach, a10_timer_attach),
346 static driver_t a10_timer_driver = {
349 sizeof(struct a10_timer_softc),
352 static devclass_t a10_timer_devclass;
354 EARLY_DRIVER_MODULE(a10_timer, simplebus, a10_timer_driver, a10_timer_devclass, 0, 0,
355 BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
358 a10_timer_delay(int usec, void *arg)
360 struct a10_timer_softc *sc = arg;
363 now = timer_read_counter64();
364 end = now + (sc->timer0_freq / 1000000) * (usec + 1);
367 now = timer_read_counter64();