sys/arm/allwinner/timer.c

   1 /*-
   2  * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <sys/param.h>
  31 #include <sys/systm.h>
  32 #include <sys/bus.h>
  33 #include <sys/kernel.h>
  34 #include <sys/module.h>
  35 #include <sys/malloc.h>
  36 #include <sys/rman.h>
  37 #include <sys/timeet.h>
  38 #include <sys/timetc.h>
  39 #include <sys/watchdog.h>
  40 #include <machine/bus.h>
  41 #include <machine/cpu.h>
  42 #include <machine/intr.h>
  43
  44 #include <dev/fdt/fdt_common.h>
  45 #include <dev/ofw/openfirm.h>
  46 #include <dev/ofw/ofw_bus.h>
  47 #include <dev/ofw/ofw_bus_subr.h>
  48
  49 #include <machine/bus.h>
  50
  51 #include <sys/kdb.h>
  52
  53 #include "a20/a20_cpu_cfg.h"
  54
  55 /**
  56  * Timer registers addr
  57  *
  58  */
  59 #define SW_TIMER_IRQ_EN_REG     0x00
  60 #define SW_TIMER_IRQ_STA_REG    0x04
  61 #define SW_TIMER0_CTRL_REG      0x10
  62 #define SW_TIMER0_INT_VALUE_REG 0x14
  63 #define SW_TIMER0_CUR_VALUE_REG 0x18
  64
  65 #define SW_COUNTER64LO_REG      0xa4
  66 #define SW_COUNTER64HI_REG      0xa8
  67 #define CNT64_CTRL_REG          0xa0
  68
  69 #define CNT64_RL_EN             0x02 /* read latch enable */
  70
  71 #define TIMER_ENABLE            (1<<0)
  72 #define TIMER_AUTORELOAD        (1<<1)
  73 #define TIMER_OSC24M            (1<<2) /* oscillator = 24mhz */
  74 #define TIMER_PRESCALAR         (0<<4) /* prescalar = 1 */
  75
  76 #define SYS_TIMER_CLKSRC        24000000 /* clock source */
  77
  78 struct a10_timer_softc {
  79         device_t        sc_dev;
  80         struct resource *res[2];
  81         bus_space_tag_t sc_bst;
  82         bus_space_handle_t sc_bsh;
  83         void            *sc_ih;         /* interrupt handler */
  84         uint32_t        sc_period;
  85         uint32_t        timer0_freq;
  86         struct eventtimer et;
  87         uint8_t         sc_timer_type;  /* 0 for A10, 1 for A20 */
  88 };
  89
  90 int a10_timer_get_timerfreq(struct a10_timer_softc *);
  91
  92 #define timer_read_4(sc, reg)   \
  93         bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg)
  94 #define timer_write_4(sc, reg, val)     \
  95         bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val)
  96
  97 static u_int    a10_timer_get_timecount(struct timecounter *);
  98 static int      a10_timer_timer_start(struct eventtimer *,
  99     sbintime_t first, sbintime_t period);
 100 static int      a10_timer_timer_stop(struct eventtimer *);
 101
 102 static uint64_t timer_read_counter64(void);
 103
 104 static int a10_timer_initialized = 0;
 105 static int a10_timer_hardclock(void *);
 106 static int a10_timer_probe(device_t);
 107 static int a10_timer_attach(device_t);
 108
 109 static struct timecounter a10_timer_timecounter = {
 110         .tc_name           = "a10_timer timer0",
 111         .tc_get_timecount  = a10_timer_get_timecount,
 112         .tc_counter_mask   = ~0u,
 113         .tc_frequency      = 0,
 114         .tc_quality        = 1000,
 115 };
 116
 117 struct a10_timer_softc *a10_timer_sc = NULL;
 118
 119 static struct resource_spec a10_timer_spec[] = {
 120         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
 121         { SYS_RES_IRQ,          0,      RF_ACTIVE },
 122         { -1, 0 }
 123 };
 124
 125 static uint64_t
 126 timer_read_counter64(void)
 127 {
 128         uint32_t lo, hi;
 129
 130         /* In case of A20 get appropriate counter info */
 131         if (a10_timer_sc->sc_timer_type)
 132                 return (a20_read_counter64());
 133
 134         /* Latch counter, wait for it to be ready to read. */
 135         timer_write_4(a10_timer_sc, CNT64_CTRL_REG, CNT64_RL_EN);
 136         while (timer_read_4(a10_timer_sc, CNT64_CTRL_REG) & CNT64_RL_EN)
 137                 continue;
 138
 139         hi = timer_read_4(a10_timer_sc, SW_COUNTER64HI_REG);
 140         lo = timer_read_4(a10_timer_sc, SW_COUNTER64LO_REG);
 141
 142         return (((uint64_t)hi << 32) | lo);
 143 }
 144
 145 static int
 146 a10_timer_probe(device_t dev)
 147 {
 148         struct a10_timer_softc *sc;
 149
 150         sc = device_get_softc(dev);
 151
 152         if (ofw_bus_is_compatible(dev, "allwinner,sun4i-timer"))
 153                 sc->sc_timer_type = 0;
 154         else if (ofw_bus_is_compatible(dev, "allwinner,sun7i-timer"))
 155                 sc->sc_timer_type = 1;
 156         else
 157                 return (ENXIO);
 158
 159         device_set_desc(dev, "Allwinner A10/A20 timer");
 160         return (BUS_PROBE_DEFAULT);
 161 }
 162
 163 static int
 164 a10_timer_attach(device_t dev)
 165 {
 166         struct a10_timer_softc *sc;
 167         int err;
 168         uint32_t val;
 169
 170         sc = device_get_softc(dev);
 171
 172         if (bus_alloc_resources(dev, a10_timer_spec, sc->res)) {
 173                 device_printf(dev, "could not allocate resources\n");
 174                 return (ENXIO);
 175         }
 176
 177         sc->sc_dev = dev;
 178         sc->sc_bst = rman_get_bustag(sc->res[0]);
 179         sc->sc_bsh = rman_get_bushandle(sc->res[0]);
 180
 181         /* Setup and enable the timer interrupt */
 182         err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, a10_timer_hardclock,
 183             NULL, sc, &sc->sc_ih);
 184         if (err != 0) {
 185                 bus_release_resources(dev, a10_timer_spec, sc->res);
 186                 device_printf(dev, "Unable to setup the clock irq handler, "
 187                     "err = %d\n", err);
 188                 return (ENXIO);
 189         }
 190
 191         /* Set clock source to OSC24M, 16 pre-division */
 192         val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
 193         val |= TIMER_PRESCALAR | TIMER_OSC24M;
 194         timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
 195
 196         /* Enable timer0 */
 197         val = timer_read_4(sc, SW_TIMER_IRQ_EN_REG);
 198         val |= TIMER_ENABLE;
 199         timer_write_4(sc, SW_TIMER_IRQ_EN_REG, val);
 200
 201         sc->timer0_freq = SYS_TIMER_CLKSRC;
 202
 203         /* Set desired frequency in event timer and timecounter */
 204         sc->et.et_frequency = sc->timer0_freq;
 205         sc->et.et_name = "a10_timer Eventtimer";
 206         sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC;
 207         sc->et.et_quality = 1000;
 208         sc->et.et_min_period = (0x00000005LLU << 32) / sc->et.et_frequency;
 209         sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
 210         sc->et.et_start = a10_timer_timer_start;
 211         sc->et.et_stop = a10_timer_timer_stop;
 212         sc->et.et_priv = sc;
 213         et_register(&sc->et);
 214
 215         if (device_get_unit(dev) == 0)
 216                 a10_timer_sc = sc;
 217
 218         a10_timer_timecounter.tc_frequency = sc->timer0_freq;
 219         tc_init(&a10_timer_timecounter);
 220
 221         if (bootverbose) {
 222                 device_printf(sc->sc_dev, "clock: hz=%d stathz = %d\n", hz, stathz);
 223
 224                 device_printf(sc->sc_dev, "event timer clock frequency %u\n",
 225                     sc->timer0_freq);
 226                 device_printf(sc->sc_dev, "timecounter clock frequency %lld\n",
 227                     a10_timer_timecounter.tc_frequency);
 228         }
 229
 230         a10_timer_initialized = 1;
 231
 232         return (0);
 233 }
 234
 235 static int
 236 a10_timer_timer_start(struct eventtimer *et, sbintime_t first,
 237     sbintime_t period)
 238 {
 239         struct a10_timer_softc *sc;
 240         uint32_t count;
 241         uint32_t val;
 242
 243         sc = (struct a10_timer_softc *)et->et_priv;
 244
 245         if (period != 0)
 246                 sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32;
 247         else
 248                 sc->sc_period = 0;
 249         if (first != 0)
 250                 count = ((uint32_t)et->et_frequency * first) >> 32;
 251         else
 252                 count = sc->sc_period;
 253
 254         /* Update timer values */
 255         timer_write_4(sc, SW_TIMER0_INT_VALUE_REG, sc->sc_period);
 256         timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, count);
 257
 258         val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
 259         if (period != 0) {
 260                 /* periodic */
 261                 val |= TIMER_AUTORELOAD;
 262         } else {
 263                 /* oneshot */
 264                 val &= ~TIMER_AUTORELOAD;
 265         }
 266         /* Enable timer0 */
 267         val |= TIMER_ENABLE;
 268         timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
 269
 270         return (0);
 271 }
 272
 273 static int
 274 a10_timer_timer_stop(struct eventtimer *et)
 275 {
 276         struct a10_timer_softc *sc;
 277         uint32_t val;
 278
 279         sc = (struct a10_timer_softc *)et->et_priv;
 280
 281         /* Disable timer0 */
 282         val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
 283         val &= ~TIMER_ENABLE;
 284         timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
 285
 286         sc->sc_period = 0;
 287
 288         return (0);
 289 }
 290
 291 int
 292 a10_timer_get_timerfreq(struct a10_timer_softc *sc)
 293 {
 294         return (sc->timer0_freq);
 295 }
 296
 297 static int
 298 a10_timer_hardclock(void *arg)
 299 {
 300         struct a10_timer_softc *sc;
 301         uint32_t val;
 302
 303         sc = (struct a10_timer_softc *)arg;
 304
 305         /* Clear interrupt pending bit. */
 306         timer_write_4(sc, SW_TIMER_IRQ_STA_REG, 0x1);
 307
 308         val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
 309         /*
 310          * Disabled autoreload and sc_period > 0 means
 311          * timer_start was called with non NULL first value.
 312          * Now we will set periodic timer with the given period
 313          * value.
 314          */
 315         if ((val & (1<<1)) == 0 && sc->sc_period > 0) {
 316                 /* Update timer */
 317                 timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, sc->sc_period);
 318
 319                 /* Make periodic and enable */
 320                 val |= TIMER_AUTORELOAD | TIMER_ENABLE;
 321                 timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
 322         }
 323
 324         if (sc->et.et_active)
 325                 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
 326
 327         return (FILTER_HANDLED);
 328 }
 329
 330 u_int
 331 a10_timer_get_timecount(struct timecounter *tc)
 332 {
 333
 334         if (a10_timer_sc == NULL)
 335                 return (0);
 336
 337         return ((u_int)timer_read_counter64());
 338 }
 339
 340 static device_method_t a10_timer_methods[] = {
 341         DEVMETHOD(device_probe,         a10_timer_probe),
 342         DEVMETHOD(device_attach,        a10_timer_attach),
 343
 344         DEVMETHOD_END
 345 };
 346
 347 static driver_t a10_timer_driver = {
 348         "a10_timer",
 349         a10_timer_methods,
 350         sizeof(struct a10_timer_softc),
 351 };
 352
 353 static devclass_t a10_timer_devclass;
 354
 355 DRIVER_MODULE(a10_timer, simplebus, a10_timer_driver, a10_timer_devclass, 0, 0);
 356
 357 void
 358 DELAY(int usec)
 359 {
 360         uint32_t counter;
 361         uint64_t end, now;
 362
 363         if (!a10_timer_initialized) {
 364                 for (; usec > 0; usec--)
 365                         for (counter = 50; counter > 0; counter--)
 366                                 cpufunc_nullop();
 367                 return;
 368         }
 369
 370         now = timer_read_counter64();
 371         end = now + (a10_timer_sc->timer0_freq / 1000000) * (usec + 1);
 372
 373         while (now < end)
 374                 now = timer_read_counter64();
 375 }
 376