2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #define L3REGS_REMAP 0x0 /* Remap */
34 #define REMAP_LWHPS2FPGA (1 << 4)
35 #define REMAP_HPS2FPGA (1 << 3)
36 #define REMAP_MPUZERO (1 << 0)
37 #define L3REGS_L4MAIN 0x8 /* L4 main peripherals security */
38 #define L3REGS_L4SP 0xC /* L4 SP Peripherals Security */
39 #define L3REGS_L4MP 0x10 /* L4 MP Peripherals Security */
40 #define L3REGS_L4OSC1 0x14 /* L4 OSC1 Peripherals Security */
41 #define L3REGS_L4SPIM 0x18 /* L4 SPIM Peripherals Security */
42 #define L3REGS_STM 0x1C /* STM Peripheral Security */
43 #define L3REGS_LWHPS2FPGAREGS 0x20 /* LWHPS2FPGA AXI Bridge Security */
44 #define L3REGS_USB1 0x28 /* USB1 Peripheral Security */
45 #define L3REGS_NANDDATA 0x2C /* NAND Flash Controller Data Sec */
46 #define L3REGS_USB0 0x80 /* USB0 Peripheral Security */
47 #define L3REGS_NANDREGS 0x84 /* NAND Flash Controller Security */
48 #define L3REGS_QSPIDATA 0x88 /* QSPI Flash Controller Data Sec */
49 #define L3REGS_FPGAMGRDATA 0x8C /* FPGA Manager Data Peripheral Sec */
50 #define L3REGS_HPS2FPGAREGS 0x90 /* HPS2FPGA AXI Bridge Perip. Sec */
51 #define L3REGS_ACP 0x94 /* MPU ACP Peripheral Security */
52 #define L3REGS_ROM 0x98 /* ROM Peripheral Security */
53 #define L3REGS_OCRAM 0x9C /* On-chip RAM Peripheral Security */
54 #define L3REGS_SDRDATA 0xA0 /* SDRAM Data Peripheral Security */