2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * Altera FPGA Manager.
33 * Chapter 4, Cyclone V Device Handbook (CV-5V2 2014.07.22)
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
39 #include <sys/param.h>
40 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/malloc.h>
46 #include <sys/timeet.h>
47 #include <sys/timetc.h>
51 #include <dev/ofw/openfirm.h>
52 #include <dev/ofw/ofw_bus.h>
53 #include <dev/ofw/ofw_bus_subr.h>
55 #include <machine/bus.h>
56 #include <machine/cpu.h>
57 #include <machine/intr.h>
59 #include <arm/altera/socfpga/socfpga_common.h>
61 /* FPGA Manager Module Registers */
62 #define FPGAMGR_STAT 0x0 /* Status Register */
63 #define STAT_MSEL_MASK 0x1f
64 #define STAT_MSEL_SHIFT 3
65 #define STAT_MODE_SHIFT 0
66 #define STAT_MODE_MASK 0x7
67 #define FPGAMGR_CTRL 0x4 /* Control Register */
68 #define CTRL_AXICFGEN (1 << 8)
69 #define CTRL_CDRATIO_MASK 0x3
70 #define CTRL_CDRATIO_SHIFT 6
71 #define CTRL_CFGWDTH_MASK 1
72 #define CTRL_CFGWDTH_SHIFT 9
73 #define CTRL_NCONFIGPULL (1 << 2)
74 #define CTRL_NCE (1 << 1)
75 #define CTRL_EN (1 << 0)
76 #define FPGAMGR_DCLKCNT 0x8 /* DCLK Count Register */
77 #define FPGAMGR_DCLKSTAT 0xC /* DCLK Status Register */
78 #define FPGAMGR_GPO 0x10 /* General-Purpose Output Register */
79 #define FPGAMGR_GPI 0x14 /* General-Purpose Input Register */
80 #define FPGAMGR_MISCI 0x18 /* Miscellaneous Input Register */
82 /* Configuration Monitor (MON) Registers */
83 #define GPIO_INTEN 0x830 /* Interrupt Enable Register */
84 #define GPIO_INTMASK 0x834 /* Interrupt Mask Register */
85 #define GPIO_INTTYPE_LEVEL 0x838 /* Interrupt Level Register */
86 #define GPIO_INT_POLARITY 0x83C /* Interrupt Polarity Register */
87 #define GPIO_INTSTATUS 0x840 /* Interrupt Status Register */
88 #define GPIO_RAW_INTSTATUS 0x844 /* Raw Interrupt Status Register */
89 #define GPIO_PORTA_EOI 0x84C /* Clear Interrupt Register */
90 #define PORTA_EOI_NS (1 << 0)
91 #define GPIO_EXT_PORTA 0x850 /* External Port A Register */
92 #define EXT_PORTA_CDP (1 << 10) /* Configuration done */
93 #define GPIO_LS_SYNC 0x860 /* Synchronization Level Register */
94 #define GPIO_VER_ID_CODE 0x86C /* GPIO Version Register */
95 #define GPIO_CONFIG_REG2 0x870 /* Configuration Register 2 */
96 #define GPIO_CONFIG_REG1 0x874 /* Configuration Register 1 */
98 #define MSEL_PP16_FAST_NOAES_NODC 0x0
99 #define MSEL_PP16_FAST_AES_NODC 0x1
100 #define MSEL_PP16_FAST_AESOPT_DC 0x2
101 #define MSEL_PP16_SLOW_NOAES_NODC 0x4
102 #define MSEL_PP16_SLOW_AES_NODC 0x5
103 #define MSEL_PP16_SLOW_AESOPT_DC 0x6
104 #define MSEL_PP32_FAST_NOAES_NODC 0x8
105 #define MSEL_PP32_FAST_AES_NODC 0x9
106 #define MSEL_PP32_FAST_AESOPT_DC 0xa
107 #define MSEL_PP32_SLOW_NOAES_NODC 0xc
108 #define MSEL_PP32_SLOW_AES_NODC 0xd
109 #define MSEL_PP32_SLOW_AESOPT_DC 0xe
119 #define FPGAMGR_MODE_POWEROFF 0x0
120 #define FPGAMGR_MODE_RESET 0x1
121 #define FPGAMGR_MODE_CONFIG 0x2
122 #define FPGAMGR_MODE_INIT 0x3
123 #define FPGAMGR_MODE_USER 0x4
131 static struct cfgmgr_mode cfgmgr_modes[] = {
132 { MSEL_PP16_FAST_NOAES_NODC, CFGWDTH_16, CDRATIO_1 },
133 { MSEL_PP16_FAST_AES_NODC, CFGWDTH_16, CDRATIO_2 },
134 { MSEL_PP16_FAST_AESOPT_DC, CFGWDTH_16, CDRATIO_4 },
135 { MSEL_PP16_SLOW_NOAES_NODC, CFGWDTH_16, CDRATIO_1 },
136 { MSEL_PP16_SLOW_AES_NODC, CFGWDTH_16, CDRATIO_2 },
137 { MSEL_PP16_SLOW_AESOPT_DC, CFGWDTH_16, CDRATIO_4 },
138 { MSEL_PP32_FAST_NOAES_NODC, CFGWDTH_32, CDRATIO_1 },
139 { MSEL_PP32_FAST_AES_NODC, CFGWDTH_32, CDRATIO_4 },
140 { MSEL_PP32_FAST_AESOPT_DC, CFGWDTH_32, CDRATIO_8 },
141 { MSEL_PP32_SLOW_NOAES_NODC, CFGWDTH_32, CDRATIO_1 },
142 { MSEL_PP32_SLOW_AES_NODC, CFGWDTH_32, CDRATIO_4 },
143 { MSEL_PP32_SLOW_AESOPT_DC, CFGWDTH_32, CDRATIO_8 },
147 struct fpgamgr_softc {
148 struct resource *res[3];
149 bus_space_tag_t bst_data;
150 bus_space_handle_t bsh_data;
151 struct cdev *mgr_cdev;
155 static struct resource_spec fpgamgr_spec[] = {
156 { SYS_RES_MEMORY, 0, RF_ACTIVE },
157 { SYS_RES_MEMORY, 1, RF_ACTIVE },
158 { SYS_RES_IRQ, 0, RF_ACTIVE },
163 fpgamgr_state_get(struct fpgamgr_softc *sc)
167 reg = READ4(sc, FPGAMGR_STAT);
168 reg >>= STAT_MODE_SHIFT;
169 reg &= STAT_MODE_MASK;
175 fpgamgr_state_wait(struct fpgamgr_softc *sc, int state)
181 if (fpgamgr_state_get(sc) == state)
194 fpga_open(struct cdev *dev, int flags __unused,
195 int fmt __unused, struct thread *td __unused)
197 struct fpgamgr_softc *sc;
198 struct cfgmgr_mode *mode;
205 msel = READ4(sc, FPGAMGR_STAT);
206 msel >>= STAT_MSEL_SHIFT;
207 msel &= STAT_MSEL_MASK;
210 for (i = 0; cfgmgr_modes[i].msel != -1; i++) {
211 if (msel == cfgmgr_modes[i].msel) {
212 mode = &cfgmgr_modes[i];
217 device_printf(sc->dev, "Can't configure: unknown mode\n");
221 reg = READ4(sc, FPGAMGR_CTRL);
222 reg &= ~(CTRL_CDRATIO_MASK << CTRL_CDRATIO_SHIFT);
223 reg |= (mode->cdratio << CTRL_CDRATIO_SHIFT);
224 reg &= ~(CTRL_CFGWDTH_MASK << CTRL_CFGWDTH_SHIFT);
225 reg |= (mode->cfgwdth << CTRL_CFGWDTH_SHIFT);
227 WRITE4(sc, FPGAMGR_CTRL, reg);
229 /* Enable configuration */
230 reg = READ4(sc, FPGAMGR_CTRL);
232 WRITE4(sc, FPGAMGR_CTRL, reg);
235 reg = READ4(sc, FPGAMGR_CTRL);
236 reg |= (CTRL_NCONFIGPULL);
237 WRITE4(sc, FPGAMGR_CTRL, reg);
239 /* Wait reset state */
240 if (fpgamgr_state_wait(sc, FPGAMGR_MODE_RESET)) {
241 device_printf(sc->dev, "Can't get RESET state\n");
245 /* Release from reset */
246 reg = READ4(sc, FPGAMGR_CTRL);
247 reg &= ~(CTRL_NCONFIGPULL);
248 WRITE4(sc, FPGAMGR_CTRL, reg);
250 if (fpgamgr_state_wait(sc, FPGAMGR_MODE_CONFIG)) {
251 device_printf(sc->dev, "Can't get CONFIG state\n");
255 /* Clear nSTATUS edge interrupt */
256 WRITE4(sc, GPIO_PORTA_EOI, PORTA_EOI_NS);
258 /* Enter configuration state */
259 reg = READ4(sc, FPGAMGR_CTRL);
260 reg |= (CTRL_AXICFGEN);
261 WRITE4(sc, FPGAMGR_CTRL, reg);
267 fpga_wait_dclk_pulses(struct fpgamgr_softc *sc, int npulses)
271 /* Clear done bit, if any */
272 if (READ4(sc, FPGAMGR_DCLKSTAT) != 0)
273 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1);
275 /* Request DCLK pulses */
276 WRITE4(sc, FPGAMGR_DCLKCNT, npulses);
281 if (READ4(sc, FPGAMGR_DCLKSTAT) == 1) {
282 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1);
296 fpga_close(struct cdev *dev, int flags __unused,
297 int fmt __unused, struct thread *td __unused)
299 struct fpgamgr_softc *sc;
304 reg = READ4(sc, GPIO_EXT_PORTA);
305 if ((reg & EXT_PORTA_CDP) == 0) {
306 device_printf(sc->dev, "Err: configuration failed\n");
310 /* Exit configuration state */
311 reg = READ4(sc, FPGAMGR_CTRL);
312 reg &= ~(CTRL_AXICFGEN);
313 WRITE4(sc, FPGAMGR_CTRL, reg);
315 /* Wait dclk pulses */
316 if (fpga_wait_dclk_pulses(sc, 4)) {
317 device_printf(sc->dev, "Can't proceed 4 dclk pulses\n");
321 if (fpgamgr_state_wait(sc, FPGAMGR_MODE_USER)) {
322 device_printf(sc->dev, "Can't get USER mode\n");
326 /* Disable configuration */
327 reg = READ4(sc, FPGAMGR_CTRL);
329 WRITE4(sc, FPGAMGR_CTRL, reg);
335 fpga_write(struct cdev *dev, struct uio *uio, int ioflag)
337 struct fpgamgr_softc *sc;
343 * Device supports 4-byte copy only.
344 * TODO: add padding for <4 bytes.
347 while (uio->uio_resid > 0) {
348 uiomove(&buffer, 4, uio);
349 bus_space_write_4(sc->bst_data, sc->bsh_data,
357 fpga_ioctl(struct cdev *dev, u_long cmd, caddr_t addr, int flags,
364 static struct cdevsw fpga_cdevsw = {
365 .d_version = D_VERSION,
367 .d_close = fpga_close,
368 .d_write = fpga_write,
369 .d_ioctl = fpga_ioctl,
370 .d_name = "FPGA Manager",
374 fpgamgr_probe(device_t dev)
377 if (!ofw_bus_status_okay(dev))
380 if (!ofw_bus_is_compatible(dev, "altr,socfpga-fpga-mgr"))
383 device_set_desc(dev, "FPGA Manager");
384 return (BUS_PROBE_DEFAULT);
388 fpgamgr_attach(device_t dev)
390 struct fpgamgr_softc *sc;
392 sc = device_get_softc(dev);
395 if (bus_alloc_resources(dev, fpgamgr_spec, sc->res)) {
396 device_printf(dev, "could not allocate resources\n");
400 /* Memory interface */
401 sc->bst_data = rman_get_bustag(sc->res[1]);
402 sc->bsh_data = rman_get_bushandle(sc->res[1]);
404 sc->mgr_cdev = make_dev(&fpga_cdevsw, 0, UID_ROOT, GID_WHEEL,
405 0600, "fpga%d", device_get_unit(sc->dev));
407 if (sc->mgr_cdev == NULL) {
408 device_printf(dev, "Failed to create character device.\n");
412 sc->mgr_cdev->si_drv1 = sc;
417 static device_method_t fpgamgr_methods[] = {
418 DEVMETHOD(device_probe, fpgamgr_probe),
419 DEVMETHOD(device_attach, fpgamgr_attach),
423 static driver_t fpgamgr_driver = {
426 sizeof(struct fpgamgr_softc),
429 static devclass_t fpgamgr_devclass;
431 DRIVER_MODULE(fpgamgr, simplebus, fpgamgr_driver, fpgamgr_devclass, 0, 0);