2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * Altera FPGA Manager.
33 * Chapter 4, Cyclone V Device Handbook (CV-5V2 2014.07.22)
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
39 #include <sys/param.h>
40 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/malloc.h>
46 #include <sys/timeet.h>
47 #include <sys/timetc.h>
51 #include <dev/fdt/fdt_common.h>
52 #include <dev/ofw/openfirm.h>
53 #include <dev/ofw/ofw_bus.h>
54 #include <dev/ofw/ofw_bus_subr.h>
56 #include <machine/bus.h>
57 #include <machine/cpu.h>
58 #include <machine/intr.h>
60 #include <arm/altera/socfpga/socfpga_common.h>
62 /* FPGA Manager Module Registers */
63 #define FPGAMGR_STAT 0x0 /* Status Register */
64 #define STAT_MSEL_MASK 0x1f
65 #define STAT_MSEL_SHIFT 3
66 #define STAT_MODE_SHIFT 0
67 #define STAT_MODE_MASK 0x7
68 #define FPGAMGR_CTRL 0x4 /* Control Register */
69 #define CTRL_AXICFGEN (1 << 8)
70 #define CTRL_CDRATIO_MASK 0x3
71 #define CTRL_CDRATIO_SHIFT 6
72 #define CTRL_CFGWDTH_MASK 1
73 #define CTRL_CFGWDTH_SHIFT 9
74 #define CTRL_NCONFIGPULL (1 << 2)
75 #define CTRL_NCE (1 << 1)
76 #define CTRL_EN (1 << 0)
77 #define FPGAMGR_DCLKCNT 0x8 /* DCLK Count Register */
78 #define FPGAMGR_DCLKSTAT 0xC /* DCLK Status Register */
79 #define FPGAMGR_GPO 0x10 /* General-Purpose Output Register */
80 #define FPGAMGR_GPI 0x14 /* General-Purpose Input Register */
81 #define FPGAMGR_MISCI 0x18 /* Miscellaneous Input Register */
83 /* Configuration Monitor (MON) Registers */
84 #define GPIO_INTEN 0x830 /* Interrupt Enable Register */
85 #define GPIO_INTMASK 0x834 /* Interrupt Mask Register */
86 #define GPIO_INTTYPE_LEVEL 0x838 /* Interrupt Level Register */
87 #define GPIO_INT_POLARITY 0x83C /* Interrupt Polarity Register */
88 #define GPIO_INTSTATUS 0x840 /* Interrupt Status Register */
89 #define GPIO_RAW_INTSTATUS 0x844 /* Raw Interrupt Status Register */
90 #define GPIO_PORTA_EOI 0x84C /* Clear Interrupt Register */
91 #define PORTA_EOI_NS (1 << 0)
92 #define GPIO_EXT_PORTA 0x850 /* External Port A Register */
93 #define EXT_PORTA_CDP (1 << 10) /* Configuration done */
94 #define GPIO_LS_SYNC 0x860 /* Synchronization Level Register */
95 #define GPIO_VER_ID_CODE 0x86C /* GPIO Version Register */
96 #define GPIO_CONFIG_REG2 0x870 /* Configuration Register 2 */
97 #define GPIO_CONFIG_REG1 0x874 /* Configuration Register 1 */
99 #define MSEL_PP16_FAST_NOAES_NODC 0x0
100 #define MSEL_PP16_FAST_AES_NODC 0x1
101 #define MSEL_PP16_FAST_AESOPT_DC 0x2
102 #define MSEL_PP16_SLOW_NOAES_NODC 0x4
103 #define MSEL_PP16_SLOW_AES_NODC 0x5
104 #define MSEL_PP16_SLOW_AESOPT_DC 0x6
105 #define MSEL_PP32_FAST_NOAES_NODC 0x8
106 #define MSEL_PP32_FAST_AES_NODC 0x9
107 #define MSEL_PP32_FAST_AESOPT_DC 0xa
108 #define MSEL_PP32_SLOW_NOAES_NODC 0xc
109 #define MSEL_PP32_SLOW_AES_NODC 0xd
110 #define MSEL_PP32_SLOW_AESOPT_DC 0xe
120 #define FPGAMGR_MODE_POWEROFF 0x0
121 #define FPGAMGR_MODE_RESET 0x1
122 #define FPGAMGR_MODE_CONFIG 0x2
123 #define FPGAMGR_MODE_INIT 0x3
124 #define FPGAMGR_MODE_USER 0x4
132 static struct cfgmgr_mode cfgmgr_modes[] = {
133 { MSEL_PP16_FAST_NOAES_NODC, CFGWDTH_16, CDRATIO_1 },
134 { MSEL_PP16_FAST_AES_NODC, CFGWDTH_16, CDRATIO_2 },
135 { MSEL_PP16_FAST_AESOPT_DC, CFGWDTH_16, CDRATIO_4 },
136 { MSEL_PP16_SLOW_NOAES_NODC, CFGWDTH_16, CDRATIO_1 },
137 { MSEL_PP16_SLOW_AES_NODC, CFGWDTH_16, CDRATIO_2 },
138 { MSEL_PP16_SLOW_AESOPT_DC, CFGWDTH_16, CDRATIO_4 },
139 { MSEL_PP32_FAST_NOAES_NODC, CFGWDTH_32, CDRATIO_1 },
140 { MSEL_PP32_FAST_AES_NODC, CFGWDTH_32, CDRATIO_4 },
141 { MSEL_PP32_FAST_AESOPT_DC, CFGWDTH_32, CDRATIO_8 },
142 { MSEL_PP32_SLOW_NOAES_NODC, CFGWDTH_32, CDRATIO_1 },
143 { MSEL_PP32_SLOW_AES_NODC, CFGWDTH_32, CDRATIO_4 },
144 { MSEL_PP32_SLOW_AESOPT_DC, CFGWDTH_32, CDRATIO_8 },
148 struct fpgamgr_softc {
149 struct resource *res[3];
150 bus_space_tag_t bst_data;
151 bus_space_handle_t bsh_data;
152 struct cdev *mgr_cdev;
156 static struct resource_spec fpgamgr_spec[] = {
157 { SYS_RES_MEMORY, 0, RF_ACTIVE },
158 { SYS_RES_MEMORY, 1, RF_ACTIVE },
159 { SYS_RES_IRQ, 0, RF_ACTIVE },
164 fpgamgr_state_get(struct fpgamgr_softc *sc)
168 reg = READ4(sc, FPGAMGR_STAT);
169 reg >>= STAT_MODE_SHIFT;
170 reg &= STAT_MODE_MASK;
176 fpgamgr_state_wait(struct fpgamgr_softc *sc, int state)
182 if (fpgamgr_state_get(sc) == state)
195 fpga_open(struct cdev *dev, int flags __unused,
196 int fmt __unused, struct thread *td __unused)
198 struct fpgamgr_softc *sc;
199 struct cfgmgr_mode *mode;
206 msel = READ4(sc, FPGAMGR_STAT);
207 msel >>= STAT_MSEL_SHIFT;
208 msel &= STAT_MSEL_MASK;
211 for (i = 0; cfgmgr_modes[i].msel != -1; i++) {
212 if (msel == cfgmgr_modes[i].msel) {
213 mode = &cfgmgr_modes[i];
218 device_printf(sc->dev, "Can't configure: unknown mode\n");
222 reg = READ4(sc, FPGAMGR_CTRL);
223 reg &= ~(CTRL_CDRATIO_MASK << CTRL_CDRATIO_SHIFT);
224 reg |= (mode->cdratio << CTRL_CDRATIO_SHIFT);
225 reg &= ~(CTRL_CFGWDTH_MASK << CTRL_CFGWDTH_SHIFT);
226 reg |= (mode->cfgwdth << CTRL_CFGWDTH_SHIFT);
228 WRITE4(sc, FPGAMGR_CTRL, reg);
230 /* Enable configuration */
231 reg = READ4(sc, FPGAMGR_CTRL);
233 WRITE4(sc, FPGAMGR_CTRL, reg);
236 reg = READ4(sc, FPGAMGR_CTRL);
237 reg |= (CTRL_NCONFIGPULL);
238 WRITE4(sc, FPGAMGR_CTRL, reg);
240 /* Wait reset state */
241 if (fpgamgr_state_wait(sc, FPGAMGR_MODE_RESET)) {
242 device_printf(sc->dev, "Can't get RESET state\n");
246 /* Release from reset */
247 reg = READ4(sc, FPGAMGR_CTRL);
248 reg &= ~(CTRL_NCONFIGPULL);
249 WRITE4(sc, FPGAMGR_CTRL, reg);
251 if (fpgamgr_state_wait(sc, FPGAMGR_MODE_CONFIG)) {
252 device_printf(sc->dev, "Can't get CONFIG state\n");
256 /* Clear nSTATUS edge interrupt */
257 WRITE4(sc, GPIO_PORTA_EOI, PORTA_EOI_NS);
259 /* Enter configuration state */
260 reg = READ4(sc, FPGAMGR_CTRL);
261 reg |= (CTRL_AXICFGEN);
262 WRITE4(sc, FPGAMGR_CTRL, reg);
268 fpga_wait_dclk_pulses(struct fpgamgr_softc *sc, int npulses)
272 /* Clear done bit, if any */
273 if (READ4(sc, FPGAMGR_DCLKSTAT) != 0)
274 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1);
276 /* Request DCLK pulses */
277 WRITE4(sc, FPGAMGR_DCLKCNT, npulses);
282 if (READ4(sc, FPGAMGR_DCLKSTAT) == 1) {
283 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1);
297 fpga_close(struct cdev *dev, int flags __unused,
298 int fmt __unused, struct thread *td __unused)
300 struct fpgamgr_softc *sc;
305 reg = READ4(sc, GPIO_EXT_PORTA);
306 if ((reg & EXT_PORTA_CDP) == 0) {
307 device_printf(sc->dev, "Err: configuration failed\n");
311 /* Exit configuration state */
312 reg = READ4(sc, FPGAMGR_CTRL);
313 reg &= ~(CTRL_AXICFGEN);
314 WRITE4(sc, FPGAMGR_CTRL, reg);
316 /* Wait dclk pulses */
317 if (fpga_wait_dclk_pulses(sc, 4)) {
318 device_printf(sc->dev, "Can't proceed 4 dclk pulses\n");
322 if (fpgamgr_state_wait(sc, FPGAMGR_MODE_USER)) {
323 device_printf(sc->dev, "Can't get USER mode\n");
327 /* Disable configuration */
328 reg = READ4(sc, FPGAMGR_CTRL);
330 WRITE4(sc, FPGAMGR_CTRL, reg);
336 fpga_write(struct cdev *dev, struct uio *uio, int ioflag)
338 struct fpgamgr_softc *sc;
344 * Device supports 4-byte copy only.
345 * TODO: add padding for <4 bytes.
348 while (uio->uio_resid > 0) {
349 uiomove(&buffer, 4, uio);
350 bus_space_write_4(sc->bst_data, sc->bsh_data,
358 fpga_ioctl(struct cdev *dev, u_long cmd, caddr_t addr, int flags,
365 static struct cdevsw fpga_cdevsw = {
366 .d_version = D_VERSION,
368 .d_close = fpga_close,
369 .d_write = fpga_write,
370 .d_ioctl = fpga_ioctl,
371 .d_name = "FPGA Manager",
375 fpgamgr_probe(device_t dev)
378 if (!ofw_bus_status_okay(dev))
381 if (!ofw_bus_is_compatible(dev, "altr,fpga-mgr"))
384 device_set_desc(dev, "FPGA Manager");
385 return (BUS_PROBE_DEFAULT);
389 fpgamgr_attach(device_t dev)
391 struct fpgamgr_softc *sc;
393 sc = device_get_softc(dev);
396 if (bus_alloc_resources(dev, fpgamgr_spec, sc->res)) {
397 device_printf(dev, "could not allocate resources\n");
401 /* Memory interface */
402 sc->bst_data = rman_get_bustag(sc->res[1]);
403 sc->bsh_data = rman_get_bushandle(sc->res[1]);
405 sc->mgr_cdev = make_dev(&fpga_cdevsw, 0, UID_ROOT, GID_WHEEL,
406 0600, "fpga%d", device_get_unit(sc->dev));
408 if (sc->mgr_cdev == NULL) {
409 device_printf(dev, "Failed to create character device.\n");
413 sc->mgr_cdev->si_drv1 = sc;
418 static device_method_t fpgamgr_methods[] = {
419 DEVMETHOD(device_probe, fpgamgr_probe),
420 DEVMETHOD(device_attach, fpgamgr_attach),
424 static driver_t fpgamgr_driver = {
427 sizeof(struct fpgamgr_softc),
430 static devclass_t fpgamgr_devclass;
432 DRIVER_MODULE(fpgamgr, simplebus, fpgamgr_driver, fpgamgr_devclass, 0, 0);