2 * Copyright (c) 2014-2017 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include "opt_platform.h"
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/kernel.h>
40 #include <sys/mutex.h>
46 #include <machine/cpu.h>
47 #include <machine/smp.h>
48 #include <machine/fdt.h>
49 #include <machine/intr.h>
50 #include <machine/platformvar.h>
52 #include <arm/altera/socfpga/socfpga_mp.h>
53 #include <arm/altera/socfpga/socfpga_rstmgr.h>
55 #define SCU_PHYSBASE 0xFFFEC000
56 #define SCU_PHYSBASE_A10 0xFFFFC000
57 #define SCU_SIZE 0x100
59 #define SCU_CONTROL_REG 0x00
60 #define SCU_CONTROL_ENABLE (1 << 0)
61 #define SCU_CONFIG_REG 0x04
62 #define SCU_CONFIG_REG_NCPU_MASK 0x03
63 #define SCU_CPUPOWER_REG 0x08
64 #define SCU_INV_TAGS_REG 0x0c
65 #define SCU_DIAG_CONTROL 0x30
66 #define SCU_DIAG_DISABLE_MIGBIT (1 << 0)
67 #define SCU_FILTER_START_REG 0x40
68 #define SCU_FILTER_END_REG 0x44
69 #define SCU_SECURE_ACCESS_REG 0x50
70 #define SCU_NONSECURE_ACCESS_REG 0x54
72 #define RSTMGR_PHYSBASE 0xFFD05000
73 #define RSTMGR_SIZE 0x100
75 #define RAM_PHYSBASE 0x0
76 #define RAM_SIZE 0x1000
78 #define SOCFPGA_ARRIA10 1
79 #define SOCFPGA_CYCLONE5 2
81 extern char *mpentry_addr;
82 static void socfpga_trampoline(void);
85 socfpga_trampoline(void)
90 ".globl mpentry_addr\n"
96 socfpga_mp_setmaxid(platform_t plat)
100 /* If we've already set this don't bother to do it again. */
107 TUNABLE_INT_FETCH("hw.ncpu", &ncpu);
108 if (ncpu < 1 || ncpu > hwcpu)
116 _socfpga_mp_start_ap(uint32_t platid)
118 bus_space_handle_t scu, rst, ram;
122 #if defined(SOC_ALTERA_ARRIA10)
123 case SOCFPGA_ARRIA10:
124 if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE_A10,
125 SCU_SIZE, 0, &scu) != 0)
126 panic("Couldn't map the SCU\n");
129 #if defined(SOC_ALTERA_CYCLONE5)
130 case SOCFPGA_CYCLONE5:
131 if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE,
132 SCU_SIZE, 0, &scu) != 0)
133 panic("Couldn't map the SCU\n");
137 panic("Unknown platform id %d\n", platid);
140 if (bus_space_map(fdtbus_bs_tag, RSTMGR_PHYSBASE,
141 RSTMGR_SIZE, 0, &rst) != 0)
142 panic("Couldn't map the reset manager (RSTMGR)\n");
143 if (bus_space_map(fdtbus_bs_tag, RAM_PHYSBASE,
144 RAM_SIZE, 0, &ram) != 0)
145 panic("Couldn't map the first physram page\n");
147 /* Invalidate SCU cache tags */
148 bus_space_write_4(fdtbus_bs_tag, scu,
149 SCU_INV_TAGS_REG, 0x0000ffff);
152 * Erratum ARM/MP: 764369 (problems with cache maintenance).
153 * Setting the "disable-migratory bit" in the undocumented SCU
154 * Diagnostic Control Register helps work around the problem.
156 reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL);
157 reg |= (SCU_DIAG_DISABLE_MIGBIT);
158 bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, reg);
160 /* Put CPU1 to reset state */
162 #if defined(SOC_ALTERA_ARRIA10)
163 case SOCFPGA_ARRIA10:
164 bus_space_write_4(fdtbus_bs_tag, rst,
165 RSTMGR_A10_MPUMODRST, MPUMODRST_CPU1);
168 #if defined(SOC_ALTERA_CYCLONE5)
169 case SOCFPGA_CYCLONE5:
170 bus_space_write_4(fdtbus_bs_tag, rst,
171 RSTMGR_MPUMODRST, MPUMODRST_CPU1);
175 panic("Unknown platform id %d\n", platid);
178 /* Enable the SCU, then clean the cache on this core */
179 reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
180 reg |= (SCU_CONTROL_ENABLE);
181 bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG, reg);
183 /* Set up trampoline code */
184 mpentry_addr = (char *)pmap_kextract((vm_offset_t)mpentry);
185 bus_space_write_region_4(fdtbus_bs_tag, ram, 0,
186 (uint32_t *)&socfpga_trampoline, 8);
188 dcache_wbinv_poc_all();
190 /* Put CPU1 out from reset */
192 #if defined(SOC_ALTERA_ARRIA10)
193 case SOCFPGA_ARRIA10:
194 bus_space_write_4(fdtbus_bs_tag, rst,
195 RSTMGR_A10_MPUMODRST, 0);
198 #if defined(SOC_ALTERA_CYCLONE5)
199 case SOCFPGA_CYCLONE5:
200 bus_space_write_4(fdtbus_bs_tag, rst,
201 RSTMGR_MPUMODRST, 0);
205 panic("Unknown platform id %d\n", platid);
211 bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
212 bus_space_unmap(fdtbus_bs_tag, rst, RSTMGR_SIZE);
213 bus_space_unmap(fdtbus_bs_tag, ram, RAM_SIZE);
216 #if defined(SOC_ALTERA_ARRIA10)
218 socfpga_a10_mp_start_ap(platform_t plat)
221 _socfpga_mp_start_ap(SOCFPGA_ARRIA10);
225 #if defined(SOC_ALTERA_CYCLONE5)
227 socfpga_mp_start_ap(platform_t plat)
230 _socfpga_mp_start_ap(SOCFPGA_CYCLONE5);