2 * Copyright (c) 2014-2017 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SOCFPGA Reset Manager.
33 * Chapter 3, Cyclone V Device Handbook (CV-5V2 2014.07.22)
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
39 #include <sys/param.h>
40 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/malloc.h>
46 #include <sys/timeet.h>
47 #include <sys/timetc.h>
48 #include <sys/sysctl.h>
50 #include <dev/ofw/openfirm.h>
51 #include <dev/ofw/ofw_bus.h>
52 #include <dev/ofw/ofw_bus_subr.h>
54 #include <machine/bus.h>
55 #include <machine/fdt.h>
56 #include <machine/cpu.h>
57 #include <machine/intr.h>
59 #include <arm/altera/socfpga/socfpga_common.h>
60 #include <arm/altera/socfpga/socfpga_rstmgr.h>
61 #include <arm/altera/socfpga/socfpga_l3regs.h>
64 struct resource *res[1];
66 bus_space_handle_t bsh;
70 struct rstmgr_softc *rstmgr_sc;
72 static struct resource_spec rstmgr_spec[] = {
73 { SYS_RES_MEMORY, 0, RF_ACTIVE },
78 RSTMGR_SYSCTL_FPGA2HPS,
79 RSTMGR_SYSCTL_LWHPS2FPGA,
80 RSTMGR_SYSCTL_HPS2FPGA
84 l3remap(struct rstmgr_softc *sc, int remap, int enable)
92 * Control whether bridge is visible to L3 masters or not.
93 * Register is write-only.
102 node = OF_finddevice("l3regs");
104 device_printf(sc->dev, "Can't find l3regs node\n");
108 if ((OF_getencprop(node, "reg", &paddr, sizeof(paddr))) > 0) {
109 if (bus_space_map(fdtbus_bs_tag, paddr, 0x4, 0, &vaddr) == 0) {
110 bus_space_write_4(fdtbus_bs_tag, vaddr,
120 rstmgr_sysctl(SYSCTL_HANDLER_ARGS)
122 struct rstmgr_softc *sc;
132 case RSTMGR_SYSCTL_FPGA2HPS:
133 bit = BRGMODRST_FPGA2HPS;
136 case RSTMGR_SYSCTL_LWHPS2FPGA:
137 bit = BRGMODRST_LWHPS2FPGA;
138 remap = REMAP_LWHPS2FPGA;
140 case RSTMGR_SYSCTL_HPS2FPGA:
141 bit = BRGMODRST_HPS2FPGA;
142 remap = REMAP_HPS2FPGA;
148 reg = READ4(sc, RSTMGR_BRGMODRST);
149 enable = reg & bit ? 0 : 1;
151 err = sysctl_handle_int(oidp, &enable, 0, req);
152 if (err || !req->newptr)
157 else if (enable == 0)
162 WRITE4(sc, RSTMGR_BRGMODRST, reg);
163 l3remap(sc, remap, enable);
169 rstmgr_warmreset(uint32_t reg)
171 struct rstmgr_softc *sc;
177 /* Request warm reset */
178 WRITE4(sc, reg, CTRL_SWWARMRSTREQ);
184 rstmgr_add_sysctl(struct rstmgr_softc *sc)
186 struct sysctl_oid_list *children;
187 struct sysctl_ctx_list *ctx;
189 ctx = device_get_sysctl_ctx(sc->dev);
190 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
192 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fpga2hps",
193 CTLTYPE_UINT | CTLFLAG_RW, sc, RSTMGR_SYSCTL_FPGA2HPS,
194 rstmgr_sysctl, "I", "Enable fpga2hps bridge");
195 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lwhps2fpga",
196 CTLTYPE_UINT | CTLFLAG_RW, sc, RSTMGR_SYSCTL_LWHPS2FPGA,
197 rstmgr_sysctl, "I", "Enable lwhps2fpga bridge");
198 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hps2fpga",
199 CTLTYPE_UINT | CTLFLAG_RW, sc, RSTMGR_SYSCTL_HPS2FPGA,
200 rstmgr_sysctl, "I", "Enable hps2fpga bridge");
206 rstmgr_probe(device_t dev)
209 if (!ofw_bus_status_okay(dev))
212 if (!ofw_bus_is_compatible(dev, "altr,rst-mgr"))
215 device_set_desc(dev, "Reset Manager");
217 return (BUS_PROBE_DEFAULT);
221 rstmgr_attach(device_t dev)
223 struct rstmgr_softc *sc;
225 sc = device_get_softc(dev);
228 if (bus_alloc_resources(dev, rstmgr_spec, sc->res)) {
229 device_printf(dev, "could not allocate resources\n");
233 /* Memory interface */
234 sc->bst = rman_get_bustag(sc->res[0]);
235 sc->bsh = rman_get_bushandle(sc->res[0]);
238 rstmgr_add_sysctl(sc);
243 static device_method_t rstmgr_methods[] = {
244 DEVMETHOD(device_probe, rstmgr_probe),
245 DEVMETHOD(device_attach, rstmgr_attach),
249 static driver_t rstmgr_driver = {
252 sizeof(struct rstmgr_softc),
255 static devclass_t rstmgr_devclass;
257 DRIVER_MODULE(rstmgr, simplebus, rstmgr_driver, rstmgr_devclass, 0, 0);