2 * Copyright 2013-2015 John Wehle <john@feith.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef _ARM_AMLOGIC_AML8726_FB_H
30 #define _ARM_AMLOGIC_AML8726_FB_H
33 #define AML_CAV_OSD1_INDEX 0x40
35 #define AML_CAV_LUT_DATAL_REG 0
36 #define AML_CAV_LUT_DATAL_WIDTH_MASK (7 << 29)
37 #define AML_CAV_LUT_DATAL_WIDTH_SHIFT 29
38 #define AML_CAV_LUT_DATAL_WIDTH_WIDTH 3
39 #define AML_CAV_LUT_DATAL_ADDR_MASK 0x1fffffff
40 #define AML_CAV_LUT_DATAL_ADDR_SHIFT 0
42 #define AML_CAV_LUT_DATAH_REG 4
43 #define AML_CAV_LUT_DATAH_BLKMODE_MASK (3 << 24)
44 #define AML_CAV_LUT_DATAH_BLKMODE_SHIFT 24
45 #define AML_CAV_LUT_DATAH_BLKMODE_LINEAR (0 << 24)
46 #define AML_CAV_LUT_DATAH_BLKMODE_32x32 (1 << 24)
47 #define AML_CAV_LUT_DATAH_BLKMODE_64x32 (2 << 24)
48 #define AML_CAV_LUT_DATAH_WRAP_X (1 << 23)
49 #define AML_CAV_LUT_DATAH_WRAP_Y (1 << 22)
50 #define AML_CAV_LUT_DATAH_HEIGHT_MASK (0x1fff << 9)
51 #define AML_CAV_LUT_DATAH_HEIGHT_SHIFT 9
52 #define AML_CAV_LUT_DATAH_WIDTH_MASK 0x1ff
53 #define AML_CAV_LUT_DATAH_WIDTH_SHIFT 0
55 #define AML_CAV_LUT_ADDR_REG 8
56 #define AML_CAV_LUT_ADDR_WR_EN (1 << 9)
57 #define AML_CAV_LUT_ADDR_RD_EN (1 << 8)
58 #define AML_CAV_LUT_ADDR_INDEX_MASK 0xff
59 #define AML_CAV_LUT_ADDR_INDEX_SHIFT 0
61 #define AML_VIU_OSD1_CTRL_REG 64
62 #define AML_VIU_OSD_CTRL_OSD_EN (1 << 21)
63 #define AML_VIU_OSD_CTRL_GLOBAL_ALPHA_MASK (0x1ff << 12)
64 #define AML_VIU_OSD_CTRL_GLOBAL_ALPHA_SHIFT 12
65 #define AML_VIU_OSD_CTRL_OSD_BLK_EN_MASK (0xf << 0)
66 #define AML_VIU_OSD_CTRL_OSD_BLK_EN_SHIFT 0
68 #define AML_VIU_OSD1_BLK0_CFG_W0_REG 108
69 #define AML_VIU_OSD1_BLK1_CFG_W0_REG 124
70 #define AML_VIU_OSD1_BLK2_CFG_W0_REG 140
71 #define AML_VIU_OSD1_BLK3_CFG_W0_REG 156
72 #define AML_VIU_OSD_BLK_CFG_W0_INDEX_MASK (0xff << 16)
73 #define AML_VIU_OSD_BLK_CFG_W0_INDEX_SHIFT 16
74 #define AML_VIU_OSD_BLK_CFG_W0_LITTLE_ENDIAN (1 << 15)
75 #define AML_VIU_OSD_BLK_CFG_W0_BLKMODE_24 (7 << 8)
76 #define AML_VIU_OSD_BLK_CFG_W0_RGB_EN (1 << 7)
77 #define AML_VIU_OSD_BLK_CFG_W0_CMATRIX_RGB (0 << 2)
79 #define AML_VIU_OSD1_BLK0_CFG_W1_REG 112
80 #define AML_VIU_OSD1_BLK1_CFG_W1_REG 128
81 #define AML_VIU_OSD1_BLK2_CFG_W1_REG 144
82 #define AML_VIU_OSD1_BLK3_CFG_W1_REG 160
83 #define AML_VIU_OSD_BLK_CFG_W1_X_END_MASK (0x1fff << 16)
84 #define AML_VIU_OSD_BLK_CFG_W1_X_END_SHIFT 16
85 #define AML_VIU_OSD_BLK_CFG_W1_X_START_MASK 0x1fff
86 #define AML_VIU_OSD_BLK_CFG_W1_X_START_SHIFT 0
88 #define AML_VIU_OSD1_BLK0_CFG_W2_REG 116
89 #define AML_VIU_OSD1_BLK1_CFG_W2_REG 132
90 #define AML_VIU_OSD1_BLK2_CFG_W2_REG 148
91 #define AML_VIU_OSD1_BLK3_CFG_W2_REG 164
92 #define AML_VIU_OSD_BLK_CFG_W2_Y_END_MASK (0x1fff << 16)
93 #define AML_VIU_OSD_BLK_CFG_W2_Y_END_SHIFT 16
94 #define AML_VIU_OSD_BLK_CFG_W2_Y_START_MASK 0x1fff
95 #define AML_VIU_OSD_BLK_CFG_W2_Y_START_SHIFT 0
97 #define AML_VIU_OSD1_BLK0_CFG_W3_REG 120
98 #define AML_VIU_OSD1_BLK1_CFG_W3_REG 136
99 #define AML_VIU_OSD1_BLK2_CFG_W3_REG 152
100 #define AML_VIU_OSD1_BLK3_CFG_W3_REG 168
101 #define AML_VIU_OSD_BLK_CFG_W3_H_END_MASK (0xfff << 16)
102 #define AML_VIU_OSD_BLK_CFG_W3_H_END_SHIFT 16
103 #define AML_VIU_OSD_BLK_CFG_W3_H_START_MASK 0xfff
104 #define AML_VIU_OSD_BLK_CFG_W3_H_START_SHIFT 0
106 #define AML_VIU_OSD1_BLK0_CFG_W4_REG 76
107 #define AML_VIU_OSD1_BLK1_CFG_W4_REG 80
108 #define AML_VIU_OSD1_BLK2_CFG_W4_REG 84
109 #define AML_VIU_OSD1_BLK3_CFG_W4_REG 88
110 #define AML_VIU_OSD_BLK_CFG_W4_V_END_MASK (0xfff << 16)
111 #define AML_VIU_OSD_BLK_CFG_W4_V_END_SHIFT 16
112 #define AML_VIU_OSD_BLK_CFG_W4_V_START_MASK 0xfff
113 #define AML_VIU_OSD_BLK_CFG_W4_V_START_SHIFT 0
115 #define AML_VIU_OSD1_FIFO_CTRL_REG 172
116 #define AML_VIU_OSD_FIFO_CTRL_DEPTH_MASK (0x3f << 12)
117 #define AML_VIU_OSD_FIFO_CTRL_DEPTH_SHIFT 12
118 #define AML_VIU_OSD_FIFO_CTRL_BURST_LEN_MASK (3 << 10)
119 #define AML_VIU_OSD_FIFO_CTRL_BURST_LEN_24 (0 << 10)
120 #define AML_VIU_OSD_FIFO_CTRL_BURST_LEN_32 (1 << 10)
121 #define AML_VIU_OSD_FIFO_CTRL_BURST_LEN_48 (2 << 10)
122 #define AML_VIU_OSD_FIFO_CTRL_BURST_LEN_64 (3 << 10)
123 #define AML_VIU_OSD_FIFO_CTRL_HOLD_LINES_MASK (0x1f << 5)
124 #define AML_VIU_OSD_FIFO_CTRL_HOLD_LINES_SHIFT 5
125 #define AML_VIU_OSD_FIFO_CTRL_URGENT (1 << 0)
127 /* OSD2 field meanings are the same as OSD1 */
128 #define AML_VIU_OSD2_CTRL_REG 192
129 #define AML_VIU_OSD2_BLK0_CFG_W0_REG 236
130 #define AML_VIU_OSD2_BLK1_CFG_W0_REG 252
131 #define AML_VIU_OSD2_BLK2_CFG_W0_REG 268
132 #define AML_VIU_OSD2_BLK3_CFG_W0_REG 284
133 #define AML_VIU_OSD2_BLK0_CFG_W1_REG 240
134 #define AML_VIU_OSD2_BLK1_CFG_W1_REG 256
135 #define AML_VIU_OSD2_BLK2_CFG_W1_REG 272
136 #define AML_VIU_OSD2_BLK3_CFG_W1_REG 288
137 #define AML_VIU_OSD2_BLK0_CFG_W2_REG 244
138 #define AML_VIU_OSD2_BLK1_CFG_W2_REG 260
139 #define AML_VIU_OSD2_BLK2_CFG_W2_REG 276
140 #define AML_VIU_OSD2_BLK3_CFG_W2_REG 292
141 #define AML_VIU_OSD2_BLK0_CFG_W3_REG 248
142 #define AML_VIU_OSD2_BLK1_CFG_W3_REG 264
143 #define AML_VIU_OSD2_BLK2_CFG_W3_REG 280
144 #define AML_VIU_OSD2_BLK3_CFG_W3_REG 296
145 #define AML_VIU_OSD2_BLK0_CFG_W4_REG 400
146 #define AML_VIU_OSD2_BLK1_CFG_W4_REG 404
147 #define AML_VIU_OSD2_BLK2_CFG_W4_REG 408
148 #define AML_VIU_OSD2_BLK3_CFG_W4_REG 412
149 #define AML_VIU_OSD2_FIFO_CTRL_REG 300
151 #define AML_VPP_MISC_REG 152
152 #define AML_VPP_MISC_OSD2_PREBLEND (1 << 17)
153 #define AML_VPP_MISC_OSD1_PREBLEND (1 << 16)
154 #define AML_VPP_MISC_VD2_PREBLEND (1 << 15)
155 #define AML_VPP_MISC_VD1_PREBLEND (1 << 14)
156 #define AML_VPP_MISC_OSD2_POSTBLEND (1 << 13)
157 #define AML_VPP_MISC_OSD1_POSTBLEND (1 << 12)
158 #define AML_VPP_MISC_VD2_POSTBLEND (1 << 11)
159 #define AML_VPP_MISC_VD1_POSTBLEND (1 << 10)
160 #define AML_VPP_MISC_POSTBLEND_EN (1 << 7)
161 #define AML_VPP_MISC_PREBLEND_EN (1 << 6)
163 #endif /* _ARM_AMLOGIC_AML8726_FB_H */