2 * Copyright 2013-2015 John Wehle <john@feith.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Amlogic aml8726 MMC host controller driver.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
41 #include <sys/mutex.h>
42 #include <sys/resource.h>
47 #include <machine/bus.h>
48 #include <machine/cpu.h>
50 #include <dev/fdt/fdt_common.h>
51 #include <dev/ofw/ofw_bus.h>
52 #include <dev/ofw/ofw_bus_subr.h>
54 #include <dev/mmc/bridge.h>
55 #include <dev/mmc/mmcreg.h>
56 #include <dev/mmc/mmcbrvar.h>
58 #include <arm/amlogic/aml8726/aml8726_mmc.h>
63 struct aml8726_mmc_gpio {
69 struct aml8726_mmc_softc {
71 struct resource *res[2];
74 unsigned int ref_freq;
75 struct aml8726_mmc_gpio pwr_en;
77 struct aml8726_mmc_gpio vselect;
83 struct mmc_command *cmd;
84 unsigned int timeout_remaining;
87 static struct resource_spec aml8726_mmc_spec[] = {
88 { SYS_RES_MEMORY, 0, RF_ACTIVE },
89 { SYS_RES_IRQ, 0, RF_ACTIVE },
93 #define AML_MMC_LOCK(sc) mtx_lock(&(sc)->mtx)
94 #define AML_MMC_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
95 #define AML_MMC_LOCK_INIT(sc) \
96 mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \
98 #define AML_MMC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx);
100 #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val))
101 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg)
102 #define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \
103 (BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE))
105 #define PWR_ON_FLAG(pol) ((pol) == 0 ? GPIO_PIN_LOW : \
107 #define PWR_OFF_FLAG(pol) ((pol) == 0 ? GPIO_PIN_HIGH : \
111 aml8726_mmc_mapmem(void *arg, bus_dma_segment_t *segs, int nseg, int error)
113 bus_addr_t *busaddrp;
116 * There should only be one bus space address since
117 * bus_dma_tag_create was called with nsegments = 1.
120 busaddrp = (bus_addr_t *)arg;
121 *busaddrp = segs->ds_addr;
125 aml8726_mmc_power_off(struct aml8726_mmc_softc *sc)
128 if (sc->pwr_en.dev == NULL)
131 return (GPIO_PIN_SET(sc->pwr_en.dev, sc->pwr_en.pin,
132 PWR_OFF_FLAG(sc->pwr_en.pol)));
136 aml8726_mmc_power_on(struct aml8726_mmc_softc *sc)
139 if (sc->pwr_en.dev == NULL)
142 return (GPIO_PIN_SET(sc->pwr_en.dev, sc->pwr_en.pin,
143 PWR_ON_FLAG(sc->pwr_en.pol)));
147 aml8726_mmc_restart_timer(struct aml8726_mmc_softc *sc)
152 if (sc->cmd == NULL || sc->timeout_remaining == 0)
155 count = (sc->timeout_remaining > 0x1fff) ? 0x1fff :
156 sc->timeout_remaining;
157 sc->timeout_remaining -= count;
159 isr = (count << AML_MMC_IRQ_STATUS_TIMER_CNT_SHIFT) |
160 AML_MMC_IRQ_STATUS_TIMER_EN | AML_MMC_IRQ_STATUS_TIMEOUT_IRQ;
162 CSR_WRITE_4(sc, AML_MMC_IRQ_STATUS_REG, isr);
168 aml8726_mmc_start_command(struct aml8726_mmc_softc *sc, struct mmc_command *cmd)
170 struct mmc_ios *ios = &sc->host.ios;
175 uint32_t cycles_per_msec;
178 uint32_t nbits_per_pkg;
181 struct mmc_data *data;
183 if (cmd->opcode > 0x3f)
184 return (MMC_ERR_INVALID);
187 * Ensure the hardware state machine is in a known state,
188 * the command done interrupt is enabled, and previous
189 * IRQ status bits have been cleared.
191 CSR_WRITE_4(sc, AML_MMC_IRQ_CONFIG_REG,
192 (AML_MMC_IRQ_CONFIG_SOFT_RESET | AML_MMC_IRQ_CONFIG_CMD_DONE_EN));
193 CSR_BARRIER(sc, AML_MMC_IRQ_CONFIG_REG);
194 CSR_WRITE_4(sc, AML_MMC_IRQ_STATUS_REG, AML_MMC_IRQ_STATUS_CLEAR_IRQ);
197 * Start and transmission bits are per section 4.7.2 of the:
199 * SD Specifications Part 1
200 * Physicaly Layer Simplified Specification
203 cmdr = AML_MMC_CMD_START_BIT | AML_MMC_CMD_TRANS_BIT_HOST | cmd->opcode;
207 timeout = AML_MMC_CMD_TIMEOUT;
209 if ((cmd->flags & MMC_RSP_136) != 0) {
210 cmdr |= AML_MMC_CMD_RESP_CRC7_FROM_8;
211 cmdr |= (133 << AML_MMC_CMD_RESP_BITS_SHIFT);
212 } else if ((cmd->flags & MMC_RSP_PRESENT) != 0)
213 cmdr |= (45 << AML_MMC_CMD_RESP_BITS_SHIFT);
215 if ((cmd->flags & MMC_RSP_CRC) == 0)
216 cmdr |= AML_MMC_CMD_RESP_NO_CRC7;
218 if ((cmd->flags & MMC_RSP_BUSY) != 0)
219 cmdr |= AML_MMC_CMD_CHECK_DAT0_BUSY;
223 if (data && data->len &&
224 (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) != 0) {
225 block_size = data->len;
227 if ((data->flags & MMC_DATA_MULTI) != 0) {
228 block_size = MMC_SECTOR_SIZE;
229 if ((data->len % block_size) != 0)
230 return (MMC_ERR_INVALID);
233 cmdr |= (((data->len / block_size) - 1) <<
234 AML_MMC_CMD_REP_PKG_CNT_SHIFT);
236 mcfgr |= (data->flags & MMC_DATA_STREAM) ?
237 AML_MMC_MULT_CONFIG_STREAM_EN : 0;
240 * The number of bits per package equals the number
241 * of data bits + the number of CRC bits. There are
242 * 16 bits of CRC calculate per bus line.
244 * A completed package appears to be detected by when
245 * a counter decremented by the width underflows, thus
246 * a value of zero always transfers 1 (or 4 bits depending
247 * on the mode) which is why bus_width is subtracted.
249 bus_width = (ios->bus_width == bus_width_4) ? 4 : 1;
250 nbits_per_pkg = block_size * 8 + 16 * bus_width - bus_width;
251 if (nbits_per_pkg > 0x3fff)
252 return (MMC_ERR_INVALID);
254 extr |= (nbits_per_pkg << AML_MMC_EXTENSION_PKT_SIZE_SHIFT);
256 error = bus_dmamap_load(sc->dmatag, sc->dmamap,
257 data->data, data->len, aml8726_mmc_mapmem, &baddr,
260 return (MMC_ERR_NO_MEMORY);
262 if ((data->flags & MMC_DATA_READ) != 0) {
263 cmdr |= AML_MMC_CMD_RESP_HAS_DATA;
264 bus_dmamap_sync(sc->dmatag, sc->dmamap,
265 BUS_DMASYNC_PREREAD);
266 timeout = AML_MMC_READ_TIMEOUT *
267 (data->len / block_size);
269 cmdr |= AML_MMC_CMD_CMD_HAS_DATA;
270 bus_dmamap_sync(sc->dmatag, sc->dmamap,
271 BUS_DMASYNC_PREWRITE);
272 timeout = AML_MMC_WRITE_TIMEOUT *
273 (data->len / block_size);
279 cmd->error = MMC_ERR_NONE;
282 * Round up while calculating the number of cycles which
283 * correspond to a millisecond. Use that to determine
284 * the count from the desired timeout in milliseconds.
286 * The counter has a limited range which is not sufficient
287 * for directly implementing worst case timeouts at high clock
288 * rates so a 32 bit counter is implemented in software.
290 * The documentation isn't clear on when the timer starts
291 * so add 48 cycles for the command and 136 cycles for the
292 * response (the values are from the previously mentioned
295 if (timeout > AML_MMC_MAX_TIMEOUT)
296 timeout = AML_MMC_MAX_TIMEOUT;
297 cycles_per_msec = (ios->clock + 1000 - 1) / 1000;
298 sc->timeout_remaining = 48 + 136 + timeout * cycles_per_msec;
300 aml8726_mmc_restart_timer(sc);
302 CSR_WRITE_4(sc, AML_MMC_CMD_ARGUMENT_REG, cmd->arg);
303 CSR_WRITE_4(sc, AML_MMC_MULT_CONFIG_REG, mcfgr);
304 CSR_WRITE_4(sc, AML_MMC_EXTENSION_REG, extr);
305 CSR_WRITE_4(sc, AML_MMC_DMA_ADDR_REG, (uint32_t)baddr);
307 CSR_WRITE_4(sc, AML_MMC_CMD_SEND_REG, cmdr);
308 CSR_BARRIER(sc, AML_MMC_CMD_SEND_REG);
310 return (MMC_ERR_NONE);
314 aml8726_mmc_intr(void *arg)
316 struct aml8726_mmc_softc *sc = (struct aml8726_mmc_softc *)arg;
317 struct mmc_command *cmd;
318 struct mmc_command *stop_cmd;
319 struct mmc_data *data;
324 uint32_t previous_byte;
332 isr = CSR_READ_4(sc, AML_MMC_IRQ_STATUS_REG);
333 cmdr = CSR_READ_4(sc, AML_MMC_CMD_SEND_REG);
338 mmc_error = MMC_ERR_NONE;
340 if ((isr & AML_MMC_IRQ_STATUS_CMD_DONE_IRQ) != 0) {
341 /* Check for CRC errors if the command has completed. */
342 if ((cmdr & AML_MMC_CMD_RESP_NO_CRC7) == 0 &&
343 (isr & AML_MMC_IRQ_STATUS_RESP_CRC7_OK) == 0)
344 mmc_error = MMC_ERR_BADCRC;
345 if ((cmdr & AML_MMC_CMD_RESP_HAS_DATA) != 0 &&
346 (isr & AML_MMC_IRQ_STATUS_RD_CRC16_OK) == 0)
347 mmc_error = MMC_ERR_BADCRC;
348 if ((cmdr & AML_MMC_CMD_CMD_HAS_DATA) != 0 &&
349 (isr & AML_MMC_IRQ_STATUS_WR_CRC16_OK) == 0)
350 mmc_error = MMC_ERR_BADCRC;
351 } else if ((isr & AML_MMC_IRQ_STATUS_TIMEOUT_IRQ) != 0) {
352 if (aml8726_mmc_restart_timer(sc) != 0) {
356 mmc_error = MMC_ERR_TIMEOUT;
361 * Clear spurious interrupts while leaving intacted any
362 * interrupts that may have occurred after we read the
363 * interrupt status register.
366 CSR_WRITE_4(sc, AML_MMC_IRQ_STATUS_REG,
367 (AML_MMC_IRQ_STATUS_CLEAR_IRQ & isr));
368 CSR_BARRIER(sc, AML_MMC_IRQ_STATUS_REG);
373 if ((isr & AML_MMC_IRQ_STATUS_CMD_BUSY) != 0 &&
375 * A multiblock operation may keep the hardware
376 * busy until stop transmission is executed.
378 (isr & AML_MMC_IRQ_STATUS_CMD_DONE_IRQ) == 0) {
379 if (mmc_error == MMC_ERR_NONE)
380 mmc_error = MMC_ERR_FAILED;
383 * Issue a soft reset (while leaving the command complete
384 * interrupt enabled) to terminate the command.
386 * Ensure the command has terminated before continuing on
387 * to things such as bus_dmamap_sync / bus_dmamap_unload.
390 icr = AML_MMC_IRQ_CONFIG_SOFT_RESET |
391 AML_MMC_IRQ_CONFIG_CMD_DONE_EN;
393 CSR_WRITE_4(sc, AML_MMC_IRQ_CONFIG_REG, icr);
395 while ((CSR_READ_4(sc, AML_MMC_IRQ_STATUS_REG) &
396 AML_MMC_IRQ_STATUS_CMD_BUSY) != 0)
400 /* Clear all interrupts since the request is no longer in flight. */
401 CSR_WRITE_4(sc, AML_MMC_IRQ_STATUS_REG, AML_MMC_IRQ_STATUS_CLEAR_IRQ);
402 CSR_BARRIER(sc, AML_MMC_IRQ_STATUS_REG);
407 cmd->error = mmc_error;
409 if ((cmd->flags & MMC_RSP_PRESENT) != 0 &&
410 mmc_error == MMC_ERR_NONE) {
412 mcfgr |= AML_MMC_MULT_CONFIG_RESP_READOUT_EN;
413 CSR_WRITE_4(sc, AML_MMC_MULT_CONFIG_REG, mcfgr);
415 if ((cmd->flags & MMC_RSP_136) != 0) {
418 * Controller supplies 135:8 instead of
419 * 127:0 so discard the leading 8 bits
420 * and provide a trailing 8 zero bits
421 * where the CRC belongs.
426 for (i = 0; i < 4; i++) {
427 resp = CSR_READ_4(sc, AML_MMC_CMD_ARGUMENT_REG);
428 cmd->resp[3 - i] = (resp << 8) | previous_byte;
429 previous_byte = (resp >> 24) & 0xff;
432 cmd->resp[0] = CSR_READ_4(sc, AML_MMC_CMD_ARGUMENT_REG);
437 if (data && data->len &&
438 (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) != 0) {
439 if ((data->flags & MMC_DATA_READ) != 0)
440 bus_dmamap_sync(sc->dmatag, sc->dmamap,
441 BUS_DMASYNC_POSTREAD);
443 bus_dmamap_sync(sc->dmatag, sc->dmamap,
444 BUS_DMASYNC_POSTWRITE);
445 bus_dmamap_unload(sc->dmatag, sc->dmamap);
449 * If there's a linked stop command, then start the stop command.
450 * In order to establish a known state attempt the stop command
451 * even if the original request encountered an error.
454 stop_cmd = (cmd->mrq->stop != cmd) ? cmd->mrq->stop : NULL;
456 if (stop_cmd != NULL) {
457 mmc_stop_error = aml8726_mmc_start_command(sc, stop_cmd);
458 if (mmc_stop_error == MMC_ERR_NONE) {
462 stop_cmd->error = mmc_stop_error;
467 /* Execute the callback after dropping the lock. */
469 cmd->mrq->done(cmd->mrq);
473 aml8726_mmc_probe(device_t dev)
476 if (!ofw_bus_status_okay(dev))
479 if (!ofw_bus_is_compatible(dev, "amlogic,aml8726-mmc"))
482 device_set_desc(dev, "Amlogic aml8726 MMC");
484 return (BUS_PROBE_DEFAULT);
488 aml8726_mmc_attach(device_t dev)
490 struct aml8726_mmc_softc *sc = device_get_softc(dev);
503 node = ofw_bus_get_node(dev);
505 len = OF_getencprop(OF_parent(node), "bus-frequency",
507 if ((len / sizeof(prop[0])) != 1 || prop[0] == 0) {
508 device_printf(dev, "missing bus-frequency attribute in FDT\n");
512 sc->ref_freq = prop[0];
515 * The pins must be specified as part of the device in order
516 * to know which port to used.
519 len = OF_getencprop(node, "pinctrl-0", prop, sizeof(prop));
521 if ((len / sizeof(prop[0])) != 1 || prop[0] == 0) {
522 device_printf(dev, "missing pinctrl-0 attribute in FDT\n");
526 len = OF_getprop_alloc(OF_node_from_xref(prop[0]), "amlogic,function",
527 sizeof(char), (void **)&function_name);
531 "missing amlogic,function attribute in FDT\n");
535 if (strncmp("sdio-a", function_name, len) == 0)
536 sc->port = AML_MMC_MULT_CONFIG_PORT_A;
537 else if (strncmp("sdio-b", function_name, len) == 0)
538 sc->port = AML_MMC_MULT_CONFIG_PORT_B;
539 else if (strncmp("sdio-c", function_name, len) == 0)
540 sc->port = AML_MMC_MULT_CONFIG_PORT_C;
542 device_printf(dev, "unknown function attribute %.*s in FDT\n",
544 free(function_name, M_OFWPROP);
548 free(function_name, M_OFWPROP);
550 sc->pwr_en.dev = NULL;
552 len = OF_getencprop(node, "mmc-pwr-en", prop, sizeof(prop));
554 if ((len / sizeof(prop[0])) == 3) {
555 sc->pwr_en.dev = OF_device_from_xref(prop[0]);
556 sc->pwr_en.pin = prop[1];
557 sc->pwr_en.pol = prop[2];
560 if (sc->pwr_en.dev == NULL) {
562 "unable to process mmc-pwr-en attribute in FDT\n");
566 /* Turn off power and then configure the output driver. */
567 if (aml8726_mmc_power_off(sc) != 0 ||
568 GPIO_PIN_SETFLAGS(sc->pwr_en.dev, sc->pwr_en.pin,
569 GPIO_PIN_OUTPUT) != 0) {
571 "could not use gpio to control power\n");
576 len = OF_getprop_alloc(node, "mmc-voltages",
577 sizeof(char), (void **)&voltages);
580 device_printf(dev, "missing mmc-voltages attribute in FDT\n");
590 while (len && nvoltages < 2) {
591 if (strncmp("1.8", voltage, len) == 0)
592 sc->voltages[nvoltages] = MMC_OCR_LOW_VOLTAGE;
593 else if (strncmp("3.3", voltage, len) == 0)
594 sc->voltages[nvoltages] = MMC_OCR_320_330 |
598 "unknown voltage attribute %.*s in FDT\n",
600 free(voltages, M_OFWPROP);
606 /* queue up next string */
607 while (*voltage && len) {
617 free(voltages, M_OFWPROP);
619 sc->vselect.dev = NULL;
621 len = OF_getencprop(node, "mmc-vselect", prop, sizeof(prop));
623 if ((len / sizeof(prop[0])) == 2) {
624 sc->vselect.dev = OF_device_from_xref(prop[0]);
625 sc->vselect.pin = prop[1];
629 if (sc->vselect.dev == NULL) {
631 "unable to process mmc-vselect attribute in FDT\n");
636 * With the power off select voltage 0 and then
637 * configure the output driver.
639 if (GPIO_PIN_SET(sc->vselect.dev, sc->vselect.pin, 0) != 0 ||
640 GPIO_PIN_SETFLAGS(sc->vselect.dev, sc->vselect.pin,
641 GPIO_PIN_OUTPUT) != 0) {
643 "could not use gpio to set voltage\n");
648 if (nvoltages == 0) {
649 device_printf(dev, "no voltages in FDT\n");
651 } else if (nvoltages == 1 && sc->vselect.dev != NULL) {
652 device_printf(dev, "only one voltage in FDT\n");
654 } else if (nvoltages == 2 && sc->vselect.dev == NULL) {
655 device_printf(dev, "too many voltages in FDT\n");
659 if (bus_alloc_resources(dev, aml8726_mmc_spec, sc->res)) {
660 device_printf(dev, "could not allocate resources for device\n");
664 AML_MMC_LOCK_INIT(sc);
666 error = bus_dma_tag_create(bus_get_dma_tag(dev), AML_MMC_ALIGN_DMA, 0,
667 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
668 AML_MMC_MAX_DMA, 1, AML_MMC_MAX_DMA, 0, NULL, NULL, &sc->dmatag);
672 error = bus_dmamap_create(sc->dmatag, 0, &sc->dmamap);
677 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE,
678 NULL, aml8726_mmc_intr, sc, &sc->ih_cookie);
680 device_printf(dev, "could not setup interrupt handler\n");
684 sc->host.f_min = 200000;
685 sc->host.f_max = 50000000;
686 sc->host.host_ocr = sc->voltages[0] | sc->voltages[1];
687 sc->host.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_HSPEED;
689 child = device_add_child(dev, "mmc", -1);
692 device_printf(dev, "could not add mmc\n");
697 error = device_probe_and_attach(child);
700 device_printf(dev, "could not attach mmc\n");
708 bus_teardown_intr(dev, sc->res[1], sc->ih_cookie);
711 bus_dmamap_destroy(sc->dmatag, sc->dmamap);
714 bus_dma_tag_destroy(sc->dmatag);
716 AML_MMC_LOCK_DESTROY(sc);
718 aml8726_mmc_power_off(sc);
720 bus_release_resources(dev, aml8726_mmc_spec, sc->res);
726 aml8726_mmc_detach(device_t dev)
728 struct aml8726_mmc_softc *sc = device_get_softc(dev);
732 if (sc->cmd != NULL) {
738 * Turn off the power, reset the hardware state machine,
739 * disable the interrupts, and clear the interrupts.
741 (void)aml8726_mmc_power_off(sc);
742 CSR_WRITE_4(sc, AML_MMC_IRQ_CONFIG_REG, AML_MMC_IRQ_CONFIG_SOFT_RESET);
743 CSR_BARRIER(sc, AML_MMC_IRQ_CONFIG_REG);
744 CSR_WRITE_4(sc, AML_MMC_IRQ_STATUS_REG, AML_MMC_IRQ_STATUS_CLEAR_IRQ);
748 bus_generic_detach(dev);
750 bus_teardown_intr(dev, sc->res[1], sc->ih_cookie);
752 bus_dmamap_destroy(sc->dmatag, sc->dmamap);
754 bus_dma_tag_destroy(sc->dmatag);
756 AML_MMC_LOCK_DESTROY(sc);
758 bus_release_resources(dev, aml8726_mmc_spec, sc->res);
764 aml8726_mmc_shutdown(device_t dev)
766 struct aml8726_mmc_softc *sc = device_get_softc(dev);
769 * Turn off the power, reset the hardware state machine,
770 * disable the interrupts, and clear the interrupts.
772 (void)aml8726_mmc_power_off(sc);
773 CSR_WRITE_4(sc, AML_MMC_IRQ_CONFIG_REG, AML_MMC_IRQ_CONFIG_SOFT_RESET);
774 CSR_BARRIER(sc, AML_MMC_IRQ_CONFIG_REG);
775 CSR_WRITE_4(sc, AML_MMC_IRQ_STATUS_REG, AML_MMC_IRQ_STATUS_CLEAR_IRQ);
781 aml8726_mmc_update_ios(device_t bus, device_t child)
783 struct aml8726_mmc_softc *sc = device_get_softc(bus);
784 struct mmc_ios *ios = &sc->host.ios;
785 unsigned int divisor;
790 cfgr = (2 << AML_MMC_CONFIG_WR_CRC_STAT_SHIFT) |
791 (2 << AML_MMC_CONFIG_WR_DELAY_SHIFT) |
792 AML_MMC_CONFIG_DMA_ENDIAN_SBW |
793 (39 << AML_MMC_CONFIG_CMD_ARG_BITS_SHIFT);
795 switch (ios->bus_width) {
797 cfgr |= AML_MMC_CONFIG_BUS_WIDTH_4;
800 cfgr |= AML_MMC_CONFIG_BUS_WIDTH_1;
806 divisor = sc->ref_freq / (ios->clock * 2) - 1;
807 if (divisor == 0 || divisor == -1)
809 if ((sc->ref_freq / ((divisor + 1) * 2)) > ios->clock)
816 CSR_WRITE_4(sc, AML_MMC_CONFIG_REG, cfgr);
820 switch (ios->power_mode) {
823 * Configure and power on the regulator so that the
824 * voltage stabilizes prior to powering on the card.
826 if (sc->vselect.dev != NULL) {
827 for (i = 0; i < 2; i++)
828 if ((sc->voltages[i] & (1 << ios->vdd)) != 0)
832 error = GPIO_PIN_SET(sc->vselect.dev,
837 error = aml8726_mmc_power_on(sc);
840 error = aml8726_mmc_power_off(sc);
850 aml8726_mmc_request(device_t bus, device_t child, struct mmc_request *req)
852 struct aml8726_mmc_softc *sc = device_get_softc(bus);
857 if (sc->cmd != NULL) {
862 mmc_error = aml8726_mmc_start_command(sc, req->cmd);
866 /* Execute the callback after dropping the lock. */
867 if (mmc_error != MMC_ERR_NONE) {
868 req->cmd->error = mmc_error;
876 aml8726_mmc_read_ivar(device_t bus, device_t child,
877 int which, uintptr_t *result)
879 struct aml8726_mmc_softc *sc = device_get_softc(bus);
882 case MMCBR_IVAR_BUS_MODE:
883 *(int *)result = sc->host.ios.bus_mode;
885 case MMCBR_IVAR_BUS_WIDTH:
886 *(int *)result = sc->host.ios.bus_width;
888 case MMCBR_IVAR_CHIP_SELECT:
889 *(int *)result = sc->host.ios.chip_select;
891 case MMCBR_IVAR_CLOCK:
892 *(int *)result = sc->host.ios.clock;
894 case MMCBR_IVAR_F_MIN:
895 *(int *)result = sc->host.f_min;
897 case MMCBR_IVAR_F_MAX:
898 *(int *)result = sc->host.f_max;
900 case MMCBR_IVAR_HOST_OCR:
901 *(int *)result = sc->host.host_ocr;
903 case MMCBR_IVAR_MODE:
904 *(int *)result = sc->host.mode;
907 *(int *)result = sc->host.ocr;
909 case MMCBR_IVAR_POWER_MODE:
910 *(int *)result = sc->host.ios.power_mode;
913 *(int *)result = sc->host.ios.vdd;
915 case MMCBR_IVAR_CAPS:
916 *(int *)result = sc->host.caps;
918 case MMCBR_IVAR_MAX_DATA:
919 *(int *)result = AML_MMC_MAX_DMA / MMC_SECTOR_SIZE;
929 aml8726_mmc_write_ivar(device_t bus, device_t child,
930 int which, uintptr_t value)
932 struct aml8726_mmc_softc *sc = device_get_softc(bus);
935 case MMCBR_IVAR_BUS_MODE:
936 sc->host.ios.bus_mode = value;
938 case MMCBR_IVAR_BUS_WIDTH:
939 sc->host.ios.bus_width = value;
941 case MMCBR_IVAR_CHIP_SELECT:
942 sc->host.ios.chip_select = value;
944 case MMCBR_IVAR_CLOCK:
945 sc->host.ios.clock = value;
947 case MMCBR_IVAR_MODE:
948 sc->host.mode = value;
951 sc->host.ocr = value;
953 case MMCBR_IVAR_POWER_MODE:
954 sc->host.ios.power_mode = value;
957 sc->host.ios.vdd = value;
959 /* These are read-only */
960 case MMCBR_IVAR_CAPS:
961 case MMCBR_IVAR_HOST_OCR:
962 case MMCBR_IVAR_F_MIN:
963 case MMCBR_IVAR_F_MAX:
964 case MMCBR_IVAR_MAX_DATA:
973 aml8726_mmc_get_ro(device_t bus, device_t child)
980 aml8726_mmc_acquire_host(device_t bus, device_t child)
982 struct aml8726_mmc_softc *sc = device_get_softc(bus);
987 mtx_sleep(sc, &sc->mtx, PZERO, "mmc", hz / 5);
996 aml8726_mmc_release_host(device_t bus, device_t child)
998 struct aml8726_mmc_softc *sc = device_get_softc(bus);
1010 static device_method_t aml8726_mmc_methods[] = {
1011 /* Device interface */
1012 DEVMETHOD(device_probe, aml8726_mmc_probe),
1013 DEVMETHOD(device_attach, aml8726_mmc_attach),
1014 DEVMETHOD(device_detach, aml8726_mmc_detach),
1015 DEVMETHOD(device_shutdown, aml8726_mmc_shutdown),
1018 DEVMETHOD(bus_read_ivar, aml8726_mmc_read_ivar),
1019 DEVMETHOD(bus_write_ivar, aml8726_mmc_write_ivar),
1021 /* MMC bridge interface */
1022 DEVMETHOD(mmcbr_update_ios, aml8726_mmc_update_ios),
1023 DEVMETHOD(mmcbr_request, aml8726_mmc_request),
1024 DEVMETHOD(mmcbr_get_ro, aml8726_mmc_get_ro),
1025 DEVMETHOD(mmcbr_acquire_host, aml8726_mmc_acquire_host),
1026 DEVMETHOD(mmcbr_release_host, aml8726_mmc_release_host),
1031 static driver_t aml8726_mmc_driver = {
1033 aml8726_mmc_methods,
1034 sizeof(struct aml8726_mmc_softc),
1037 static devclass_t aml8726_mmc_devclass;
1039 DRIVER_MODULE(aml8726_mmc, simplebus, aml8726_mmc_driver,
1040 aml8726_mmc_devclass, 0, 0);
1041 MODULE_DEPEND(aml8726_mmc, aml8726_gpio, 1, 1, 1);