2 * Copyright 2013-2015 John Wehle <john@feith.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Amlogic aml8726 MMC host controller driver.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
40 #include <sys/mutex.h>
41 #include <sys/resource.h>
46 #include <machine/bus.h>
47 #include <machine/cpu.h>
49 #include <dev/ofw/ofw_bus.h>
50 #include <dev/ofw/ofw_bus_subr.h>
52 #include <dev/mmc/bridge.h>
53 #include <dev/mmc/mmcbrvar.h>
55 #include <arm/amlogic/aml8726/aml8726_mmc.h>
60 struct aml8726_mmc_gpio {
66 struct aml8726_mmc_softc {
68 struct resource *res[2];
72 unsigned int ref_freq;
73 struct aml8726_mmc_gpio pwr_en;
75 struct aml8726_mmc_gpio vselect;
81 struct mmc_command *cmd;
82 uint32_t stop_timeout;
85 static struct resource_spec aml8726_mmc_spec[] = {
86 { SYS_RES_MEMORY, 0, RF_ACTIVE },
87 { SYS_RES_IRQ, 0, RF_ACTIVE },
91 #define AML_MMC_LOCK(sc) mtx_lock(&(sc)->mtx)
92 #define AML_MMC_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
93 #define AML_MMC_LOCK_ASSERT(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
94 #define AML_MMC_LOCK_INIT(sc) \
95 mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \
97 #define AML_MMC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx);
99 #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val))
100 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg)
101 #define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \
102 (BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE))
104 #define PWR_ON_FLAG(pol) ((pol) == 0 ? GPIO_PIN_LOW : \
106 #define PWR_OFF_FLAG(pol) ((pol) == 0 ? GPIO_PIN_HIGH : \
109 #define MSECS_TO_TICKS(ms) (((ms)*hz)/1000 + 1)
111 static void aml8726_mmc_timeout(void *arg);
114 aml8726_mmc_clk(phandle_t node)
120 len = OF_getencprop(node, "clocks", &prop, sizeof(prop));
121 if ((len / sizeof(prop)) != 1 || prop == 0 ||
122 (clk_node = OF_node_from_xref(prop)) == 0)
125 len = OF_getencprop(clk_node, "clock-frequency", &prop, sizeof(prop));
126 if ((len / sizeof(prop)) != 1 || prop == 0)
129 return ((unsigned int)prop);
133 aml8726_mmc_freq(struct aml8726_mmc_softc *sc, uint32_t divisor)
136 return (sc->ref_freq / ((divisor + 1) * 2));
140 aml8726_mmc_div(struct aml8726_mmc_softc *sc, uint32_t desired_freq)
144 divisor = sc->ref_freq / (desired_freq * 2);
151 if (aml8726_mmc_freq(sc, divisor) > desired_freq)
154 if (divisor > (AML_MMC_CONFIG_CMD_CLK_DIV_MASK >>
155 AML_MMC_CONFIG_CMD_CLK_DIV_SHIFT)) {
156 divisor = AML_MMC_CONFIG_CMD_CLK_DIV_MASK >>
157 AML_MMC_CONFIG_CMD_CLK_DIV_SHIFT;
164 aml8726_mmc_mapmem(void *arg, bus_dma_segment_t *segs, int nseg, int error)
166 bus_addr_t *busaddrp;
169 * There should only be one bus space address since
170 * bus_dma_tag_create was called with nsegments = 1.
173 busaddrp = (bus_addr_t *)arg;
174 *busaddrp = segs->ds_addr;
178 aml8726_mmc_power_off(struct aml8726_mmc_softc *sc)
181 if (sc->pwr_en.dev == NULL)
184 return (GPIO_PIN_SET(sc->pwr_en.dev, sc->pwr_en.pin,
185 PWR_OFF_FLAG(sc->pwr_en.pol)));
189 aml8726_mmc_power_on(struct aml8726_mmc_softc *sc)
192 if (sc->pwr_en.dev == NULL)
195 return (GPIO_PIN_SET(sc->pwr_en.dev, sc->pwr_en.pin,
196 PWR_ON_FLAG(sc->pwr_en.pol)));
200 aml8726_mmc_soft_reset(struct aml8726_mmc_softc *sc, boolean_t enable_irq)
204 icr = AML_MMC_IRQ_CONFIG_SOFT_RESET;
206 if (enable_irq == true)
207 icr |= AML_MMC_IRQ_CONFIG_CMD_DONE_EN;
209 CSR_WRITE_4(sc, AML_MMC_IRQ_CONFIG_REG, icr);
210 CSR_BARRIER(sc, AML_MMC_IRQ_CONFIG_REG);
214 aml8726_mmc_start_command(struct aml8726_mmc_softc *sc, struct mmc_command *cmd)
216 struct mmc_ios *ios = &sc->host.ios;
223 uint32_t nbits_per_pkg;
226 struct mmc_data *data;
228 if (cmd->opcode > 0x3f)
229 return (MMC_ERR_INVALID);
232 * Ensure the hardware state machine is in a known state.
234 aml8726_mmc_soft_reset(sc, true);
237 * Start and transmission bits are per section 4.7.2 of the:
239 * SD Specifications Part 1
240 * Physical Layer Simplified Specification
243 cmdr = AML_MMC_CMD_START_BIT | AML_MMC_CMD_TRANS_BIT_HOST | cmd->opcode;
247 timeout = AML_MMC_CMD_TIMEOUT;
250 * If this is a linked command, then use the previous timeout.
252 if (cmd == cmd->mrq->stop && sc->stop_timeout)
253 timeout = sc->stop_timeout;
254 sc->stop_timeout = 0;
256 if ((cmd->flags & MMC_RSP_136) != 0) {
257 cmdr |= AML_MMC_CMD_RESP_CRC7_FROM_8;
258 cmdr |= (133 << AML_MMC_CMD_RESP_BITS_SHIFT);
259 } else if ((cmd->flags & MMC_RSP_PRESENT) != 0)
260 cmdr |= (45 << AML_MMC_CMD_RESP_BITS_SHIFT);
262 if ((cmd->flags & MMC_RSP_CRC) == 0)
263 cmdr |= AML_MMC_CMD_RESP_NO_CRC7;
265 if ((cmd->flags & MMC_RSP_BUSY) != 0)
266 cmdr |= AML_MMC_CMD_CHECK_DAT0_BUSY;
270 if (data && data->len &&
271 (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) != 0) {
272 block_size = data->len;
274 if ((data->flags & MMC_DATA_MULTI) != 0) {
275 block_size = MMC_SECTOR_SIZE;
276 if ((data->len % block_size) != 0)
277 return (MMC_ERR_INVALID);
280 cmdr |= (((data->len / block_size) - 1) <<
281 AML_MMC_CMD_REP_PKG_CNT_SHIFT);
283 mcfgr |= (data->flags & MMC_DATA_STREAM) ?
284 AML_MMC_MULT_CONFIG_STREAM_EN : 0;
287 * The number of bits per package equals the number
288 * of data bits + the number of CRC bits. There are
289 * 16 bits of CRC calculate per bus line.
291 * A completed package appears to be detected by when
292 * a counter decremented by the width underflows, thus
293 * a value of zero always transfers 1 (or 4 bits depending
294 * on the mode) which is why bus_width is subtracted.
296 bus_width = (ios->bus_width == bus_width_4) ? 4 : 1;
297 nbits_per_pkg = block_size * 8 + 16 * bus_width - bus_width;
298 if (nbits_per_pkg > 0x3fff)
299 return (MMC_ERR_INVALID);
301 extr |= (nbits_per_pkg << AML_MMC_EXTENSION_PKT_SIZE_SHIFT);
303 error = bus_dmamap_load(sc->dmatag, sc->dmamap,
304 data->data, data->len, aml8726_mmc_mapmem, &baddr,
307 return (MMC_ERR_NO_MEMORY);
309 if ((data->flags & MMC_DATA_READ) != 0) {
310 cmdr |= AML_MMC_CMD_RESP_HAS_DATA;
311 bus_dmamap_sync(sc->dmatag, sc->dmamap,
312 BUS_DMASYNC_PREREAD);
313 timeout = AML_MMC_READ_TIMEOUT *
314 (data->len / block_size);
316 cmdr |= AML_MMC_CMD_CMD_HAS_DATA;
317 bus_dmamap_sync(sc->dmatag, sc->dmamap,
318 BUS_DMASYNC_PREWRITE);
319 timeout = AML_MMC_WRITE_TIMEOUT *
320 (data->len / block_size);
324 * Stop terminates a multiblock read / write and thus
325 * can take as long to execute as an actual read / write.
327 if (cmd->mrq->stop != NULL)
328 sc->stop_timeout = timeout;
333 cmd->error = MMC_ERR_NONE;
335 if (timeout > AML_MMC_MAX_TIMEOUT)
336 timeout = AML_MMC_MAX_TIMEOUT;
338 callout_reset(&sc->ch, MSECS_TO_TICKS(timeout),
339 aml8726_mmc_timeout, sc);
341 CSR_WRITE_4(sc, AML_MMC_CMD_ARGUMENT_REG, cmd->arg);
342 CSR_WRITE_4(sc, AML_MMC_MULT_CONFIG_REG, mcfgr);
343 CSR_WRITE_4(sc, AML_MMC_EXTENSION_REG, extr);
344 CSR_WRITE_4(sc, AML_MMC_DMA_ADDR_REG, (uint32_t)baddr);
346 CSR_WRITE_4(sc, AML_MMC_CMD_SEND_REG, cmdr);
347 CSR_BARRIER(sc, AML_MMC_CMD_SEND_REG);
349 return (MMC_ERR_NONE);
353 aml8726_mmc_finish_command(struct aml8726_mmc_softc *sc, int mmc_error)
356 struct mmc_command *cmd;
357 struct mmc_command *stop_cmd;
358 struct mmc_data *data;
360 AML_MMC_LOCK_ASSERT(sc);
362 /* Clear all interrupts since the request is no longer in flight. */
363 CSR_WRITE_4(sc, AML_MMC_IRQ_STATUS_REG, AML_MMC_IRQ_STATUS_CLEAR_IRQ);
364 CSR_BARRIER(sc, AML_MMC_IRQ_STATUS_REG);
366 /* In some cases (e.g. finish called via timeout) this is a NOP. */
367 callout_stop(&sc->ch);
372 cmd->error = mmc_error;
376 if (data && data->len &&
377 (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) != 0) {
378 if ((data->flags & MMC_DATA_READ) != 0)
379 bus_dmamap_sync(sc->dmatag, sc->dmamap,
380 BUS_DMASYNC_POSTREAD);
382 bus_dmamap_sync(sc->dmatag, sc->dmamap,
383 BUS_DMASYNC_POSTWRITE);
384 bus_dmamap_unload(sc->dmatag, sc->dmamap);
388 * If there's a linked stop command, then start the stop command.
389 * In order to establish a known state attempt the stop command
390 * even if the original request encountered an error.
393 stop_cmd = (cmd->mrq->stop != cmd) ? cmd->mrq->stop : NULL;
395 if (stop_cmd != NULL) {
396 mmc_stop_error = aml8726_mmc_start_command(sc, stop_cmd);
397 if (mmc_stop_error == MMC_ERR_NONE) {
401 stop_cmd->error = mmc_stop_error;
406 /* Execute the callback after dropping the lock. */
408 cmd->mrq->done(cmd->mrq);
412 aml8726_mmc_timeout(void *arg)
414 struct aml8726_mmc_softc *sc = (struct aml8726_mmc_softc *)arg;
417 * The command failed to complete in time so forcefully
420 aml8726_mmc_soft_reset(sc, false);
423 * Ensure the command has terminated before continuing on
424 * to things such as bus_dmamap_sync / bus_dmamap_unload.
426 while ((CSR_READ_4(sc, AML_MMC_IRQ_STATUS_REG) &
427 AML_MMC_IRQ_STATUS_CMD_BUSY) != 0)
430 aml8726_mmc_finish_command(sc, MMC_ERR_TIMEOUT);
434 aml8726_mmc_intr(void *arg)
436 struct aml8726_mmc_softc *sc = (struct aml8726_mmc_softc *)arg;
440 uint32_t previous_byte;
447 isr = CSR_READ_4(sc, AML_MMC_IRQ_STATUS_REG);
448 cmdr = CSR_READ_4(sc, AML_MMC_CMD_SEND_REG);
453 mmc_error = MMC_ERR_NONE;
455 if ((isr & AML_MMC_IRQ_STATUS_CMD_DONE_IRQ) != 0) {
456 /* Check for CRC errors if the command has completed. */
457 if ((cmdr & AML_MMC_CMD_RESP_NO_CRC7) == 0 &&
458 (isr & AML_MMC_IRQ_STATUS_RESP_CRC7_OK) == 0)
459 mmc_error = MMC_ERR_BADCRC;
460 if ((cmdr & AML_MMC_CMD_RESP_HAS_DATA) != 0 &&
461 (isr & AML_MMC_IRQ_STATUS_RD_CRC16_OK) == 0)
462 mmc_error = MMC_ERR_BADCRC;
463 if ((cmdr & AML_MMC_CMD_CMD_HAS_DATA) != 0 &&
464 (isr & AML_MMC_IRQ_STATUS_WR_CRC16_OK) == 0)
465 mmc_error = MMC_ERR_BADCRC;
470 * Clear spurious interrupts while leaving intacted any
471 * interrupts that may have occurred after we read the
472 * interrupt status register.
475 CSR_WRITE_4(sc, AML_MMC_IRQ_STATUS_REG,
476 (AML_MMC_IRQ_STATUS_CLEAR_IRQ & isr));
477 CSR_BARRIER(sc, AML_MMC_IRQ_STATUS_REG);
482 if ((cmdr & AML_MMC_CMD_RESP_BITS_MASK) != 0) {
484 mcfgr |= AML_MMC_MULT_CONFIG_RESP_READOUT_EN;
485 CSR_WRITE_4(sc, AML_MMC_MULT_CONFIG_REG, mcfgr);
487 if ((cmdr & AML_MMC_CMD_RESP_CRC7_FROM_8) != 0) {
490 * Controller supplies 135:8 instead of
491 * 127:0 so discard the leading 8 bits
492 * and provide a trailing 8 zero bits
493 * where the CRC belongs.
498 for (i = 0; i < 4; i++) {
499 resp = CSR_READ_4(sc, AML_MMC_CMD_ARGUMENT_REG);
500 sc->cmd->resp[3 - i] = (resp << 8) |
502 previous_byte = (resp >> 24) & 0xff;
505 sc->cmd->resp[0] = CSR_READ_4(sc,
506 AML_MMC_CMD_ARGUMENT_REG);
509 if ((isr & AML_MMC_IRQ_STATUS_CMD_BUSY) != 0 &&
511 * A multiblock operation may keep the hardware
512 * busy until stop transmission is executed.
514 (isr & AML_MMC_IRQ_STATUS_CMD_DONE_IRQ) == 0) {
515 if (mmc_error == MMC_ERR_NONE)
516 mmc_error = MMC_ERR_FAILED;
519 * Issue a soft reset to terminate the command.
521 * Ensure the command has terminated before continuing on
522 * to things such as bus_dmamap_sync / bus_dmamap_unload.
525 aml8726_mmc_soft_reset(sc, false);
527 while ((CSR_READ_4(sc, AML_MMC_IRQ_STATUS_REG) &
528 AML_MMC_IRQ_STATUS_CMD_BUSY) != 0)
532 aml8726_mmc_finish_command(sc, mmc_error);
536 aml8726_mmc_probe(device_t dev)
539 if (!ofw_bus_status_okay(dev))
542 if (!ofw_bus_is_compatible(dev, "amlogic,aml8726-mmc"))
545 device_set_desc(dev, "Amlogic aml8726 MMC");
547 return (BUS_PROBE_DEFAULT);
551 aml8726_mmc_attach(device_t dev)
553 struct aml8726_mmc_softc *sc = device_get_softc(dev);
566 node = ofw_bus_get_node(dev);
568 sc->ref_freq = aml8726_mmc_clk(node);
570 if (sc->ref_freq == 0) {
571 device_printf(dev, "missing clocks attribute in FDT\n");
576 * The pins must be specified as part of the device in order
577 * to know which port to used.
580 len = OF_getencprop(node, "pinctrl-0", prop, sizeof(prop));
582 if ((len / sizeof(prop[0])) != 1 || prop[0] == 0) {
583 device_printf(dev, "missing pinctrl-0 attribute in FDT\n");
587 len = OF_getprop_alloc(OF_node_from_xref(prop[0]), "amlogic,function",
588 sizeof(char), (void **)&function_name);
592 "missing amlogic,function attribute in FDT\n");
596 if (strncmp("sdio-a", function_name, len) == 0)
597 sc->port = AML_MMC_MULT_CONFIG_PORT_A;
598 else if (strncmp("sdio-b", function_name, len) == 0)
599 sc->port = AML_MMC_MULT_CONFIG_PORT_B;
600 else if (strncmp("sdio-c", function_name, len) == 0)
601 sc->port = AML_MMC_MULT_CONFIG_PORT_C;
603 device_printf(dev, "unknown function attribute %.*s in FDT\n",
605 OF_prop_free(function_name);
609 OF_prop_free(function_name);
611 sc->pwr_en.dev = NULL;
613 len = OF_getencprop(node, "mmc-pwr-en", prop, sizeof(prop));
615 if ((len / sizeof(prop[0])) == 3) {
616 sc->pwr_en.dev = OF_device_from_xref(prop[0]);
617 sc->pwr_en.pin = prop[1];
618 sc->pwr_en.pol = prop[2];
621 if (sc->pwr_en.dev == NULL) {
623 "unable to process mmc-pwr-en attribute in FDT\n");
627 /* Turn off power and then configure the output driver. */
628 if (aml8726_mmc_power_off(sc) != 0 ||
629 GPIO_PIN_SETFLAGS(sc->pwr_en.dev, sc->pwr_en.pin,
630 GPIO_PIN_OUTPUT) != 0) {
632 "could not use gpio to control power\n");
637 len = OF_getprop_alloc(node, "mmc-voltages",
638 sizeof(char), (void **)&voltages);
641 device_printf(dev, "missing mmc-voltages attribute in FDT\n");
651 while (len && nvoltages < 2) {
652 if (strncmp("1.8", voltage, len) == 0)
653 sc->voltages[nvoltages] = MMC_OCR_LOW_VOLTAGE;
654 else if (strncmp("3.3", voltage, len) == 0)
655 sc->voltages[nvoltages] = MMC_OCR_320_330 |
659 "unknown voltage attribute %.*s in FDT\n",
661 OF_prop_free(voltages);
667 /* queue up next string */
668 while (*voltage && len) {
678 OF_prop_free(voltages);
680 sc->vselect.dev = NULL;
682 len = OF_getencprop(node, "mmc-vselect", prop, sizeof(prop));
684 if ((len / sizeof(prop[0])) == 2) {
685 sc->vselect.dev = OF_device_from_xref(prop[0]);
686 sc->vselect.pin = prop[1];
690 if (sc->vselect.dev == NULL) {
692 "unable to process mmc-vselect attribute in FDT\n");
697 * With the power off select voltage 0 and then
698 * configure the output driver.
700 if (GPIO_PIN_SET(sc->vselect.dev, sc->vselect.pin, 0) != 0 ||
701 GPIO_PIN_SETFLAGS(sc->vselect.dev, sc->vselect.pin,
702 GPIO_PIN_OUTPUT) != 0) {
704 "could not use gpio to set voltage\n");
709 if (nvoltages == 0) {
710 device_printf(dev, "no voltages in FDT\n");
712 } else if (nvoltages == 1 && sc->vselect.dev != NULL) {
713 device_printf(dev, "only one voltage in FDT\n");
715 } else if (nvoltages == 2 && sc->vselect.dev == NULL) {
716 device_printf(dev, "too many voltages in FDT\n");
720 if (bus_alloc_resources(dev, aml8726_mmc_spec, sc->res)) {
721 device_printf(dev, "could not allocate resources for device\n");
725 AML_MMC_LOCK_INIT(sc);
727 error = bus_dma_tag_create(bus_get_dma_tag(dev), AML_MMC_ALIGN_DMA, 0,
728 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
729 AML_MMC_MAX_DMA, 1, AML_MMC_MAX_DMA, 0, NULL, NULL, &sc->dmatag);
733 error = bus_dmamap_create(sc->dmatag, 0, &sc->dmamap);
738 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE,
739 NULL, aml8726_mmc_intr, sc, &sc->ih_cookie);
741 device_printf(dev, "could not setup interrupt handler\n");
745 callout_init_mtx(&sc->ch, &sc->mtx, CALLOUT_RETURNUNLOCKED);
747 sc->host.f_min = aml8726_mmc_freq(sc, aml8726_mmc_div(sc, 200000));
748 sc->host.f_max = aml8726_mmc_freq(sc, aml8726_mmc_div(sc, 50000000));
749 sc->host.host_ocr = sc->voltages[0] | sc->voltages[1];
750 sc->host.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_HSPEED;
752 child = device_add_child(dev, "mmc", -1);
755 device_printf(dev, "could not add mmc\n");
760 error = device_probe_and_attach(child);
763 device_printf(dev, "could not attach mmc\n");
771 bus_teardown_intr(dev, sc->res[1], sc->ih_cookie);
774 bus_dmamap_destroy(sc->dmatag, sc->dmamap);
777 bus_dma_tag_destroy(sc->dmatag);
779 AML_MMC_LOCK_DESTROY(sc);
781 aml8726_mmc_power_off(sc);
783 bus_release_resources(dev, aml8726_mmc_spec, sc->res);
789 aml8726_mmc_detach(device_t dev)
791 struct aml8726_mmc_softc *sc = device_get_softc(dev);
795 if (sc->cmd != NULL) {
801 * Turn off the power, reset the hardware state machine,
802 * disable the interrupts, and clear the interrupts.
804 (void)aml8726_mmc_power_off(sc);
805 aml8726_mmc_soft_reset(sc, false);
806 CSR_WRITE_4(sc, AML_MMC_IRQ_STATUS_REG, AML_MMC_IRQ_STATUS_CLEAR_IRQ);
808 /* This should be a NOP since no command was in flight. */
809 callout_stop(&sc->ch);
813 bus_generic_detach(dev);
815 bus_teardown_intr(dev, sc->res[1], sc->ih_cookie);
817 bus_dmamap_destroy(sc->dmatag, sc->dmamap);
819 bus_dma_tag_destroy(sc->dmatag);
821 AML_MMC_LOCK_DESTROY(sc);
823 bus_release_resources(dev, aml8726_mmc_spec, sc->res);
829 aml8726_mmc_shutdown(device_t dev)
831 struct aml8726_mmc_softc *sc = device_get_softc(dev);
834 * Turn off the power, reset the hardware state machine,
835 * disable the interrupts, and clear the interrupts.
837 (void)aml8726_mmc_power_off(sc);
838 aml8726_mmc_soft_reset(sc, false);
839 CSR_WRITE_4(sc, AML_MMC_IRQ_STATUS_REG, AML_MMC_IRQ_STATUS_CLEAR_IRQ);
845 aml8726_mmc_update_ios(device_t bus, device_t child)
847 struct aml8726_mmc_softc *sc = device_get_softc(bus);
848 struct mmc_ios *ios = &sc->host.ios;
853 cfgr = (2 << AML_MMC_CONFIG_WR_CRC_STAT_SHIFT) |
854 (2 << AML_MMC_CONFIG_WR_DELAY_SHIFT) |
855 AML_MMC_CONFIG_DMA_ENDIAN_SBW |
856 (39 << AML_MMC_CONFIG_CMD_ARG_BITS_SHIFT);
858 switch (ios->bus_width) {
860 cfgr |= AML_MMC_CONFIG_BUS_WIDTH_4;
863 cfgr |= AML_MMC_CONFIG_BUS_WIDTH_1;
869 cfgr |= aml8726_mmc_div(sc, ios->clock) <<
870 AML_MMC_CONFIG_CMD_CLK_DIV_SHIFT;
872 CSR_WRITE_4(sc, AML_MMC_CONFIG_REG, cfgr);
876 switch (ios->power_mode) {
879 * Configure and power on the regulator so that the
880 * voltage stabilizes prior to powering on the card.
882 if (sc->vselect.dev != NULL) {
883 for (i = 0; i < 2; i++)
884 if ((sc->voltages[i] & (1 << ios->vdd)) != 0)
888 error = GPIO_PIN_SET(sc->vselect.dev,
893 error = aml8726_mmc_power_on(sc);
896 error = aml8726_mmc_power_off(sc);
906 aml8726_mmc_request(device_t bus, device_t child, struct mmc_request *req)
908 struct aml8726_mmc_softc *sc = device_get_softc(bus);
913 if (sc->cmd != NULL) {
918 mmc_error = aml8726_mmc_start_command(sc, req->cmd);
922 /* Execute the callback after dropping the lock. */
923 if (mmc_error != MMC_ERR_NONE) {
924 req->cmd->error = mmc_error;
932 aml8726_mmc_read_ivar(device_t bus, device_t child,
933 int which, uintptr_t *result)
935 struct aml8726_mmc_softc *sc = device_get_softc(bus);
938 case MMCBR_IVAR_BUS_MODE:
939 *(int *)result = sc->host.ios.bus_mode;
941 case MMCBR_IVAR_BUS_WIDTH:
942 *(int *)result = sc->host.ios.bus_width;
944 case MMCBR_IVAR_CHIP_SELECT:
945 *(int *)result = sc->host.ios.chip_select;
947 case MMCBR_IVAR_CLOCK:
948 *(int *)result = sc->host.ios.clock;
950 case MMCBR_IVAR_F_MIN:
951 *(int *)result = sc->host.f_min;
953 case MMCBR_IVAR_F_MAX:
954 *(int *)result = sc->host.f_max;
956 case MMCBR_IVAR_HOST_OCR:
957 *(int *)result = sc->host.host_ocr;
959 case MMCBR_IVAR_MODE:
960 *(int *)result = sc->host.mode;
963 *(int *)result = sc->host.ocr;
965 case MMCBR_IVAR_POWER_MODE:
966 *(int *)result = sc->host.ios.power_mode;
969 *(int *)result = sc->host.ios.vdd;
971 case MMCBR_IVAR_CAPS:
972 *(int *)result = sc->host.caps;
974 case MMCBR_IVAR_MAX_DATA:
975 *(int *)result = AML_MMC_MAX_DMA / MMC_SECTOR_SIZE;
985 aml8726_mmc_write_ivar(device_t bus, device_t child,
986 int which, uintptr_t value)
988 struct aml8726_mmc_softc *sc = device_get_softc(bus);
991 case MMCBR_IVAR_BUS_MODE:
992 sc->host.ios.bus_mode = value;
994 case MMCBR_IVAR_BUS_WIDTH:
995 sc->host.ios.bus_width = value;
997 case MMCBR_IVAR_CHIP_SELECT:
998 sc->host.ios.chip_select = value;
1000 case MMCBR_IVAR_CLOCK:
1001 sc->host.ios.clock = value;
1003 case MMCBR_IVAR_MODE:
1004 sc->host.mode = value;
1006 case MMCBR_IVAR_OCR:
1007 sc->host.ocr = value;
1009 case MMCBR_IVAR_POWER_MODE:
1010 sc->host.ios.power_mode = value;
1012 case MMCBR_IVAR_VDD:
1013 sc->host.ios.vdd = value;
1015 /* These are read-only */
1016 case MMCBR_IVAR_CAPS:
1017 case MMCBR_IVAR_HOST_OCR:
1018 case MMCBR_IVAR_F_MIN:
1019 case MMCBR_IVAR_F_MAX:
1020 case MMCBR_IVAR_MAX_DATA:
1029 aml8726_mmc_get_ro(device_t bus, device_t child)
1036 aml8726_mmc_acquire_host(device_t bus, device_t child)
1038 struct aml8726_mmc_softc *sc = device_get_softc(bus);
1042 while (sc->bus_busy)
1043 mtx_sleep(sc, &sc->mtx, PZERO, "mmc", hz / 5);
1052 aml8726_mmc_release_host(device_t bus, device_t child)
1054 struct aml8726_mmc_softc *sc = device_get_softc(bus);
1066 static device_method_t aml8726_mmc_methods[] = {
1067 /* Device interface */
1068 DEVMETHOD(device_probe, aml8726_mmc_probe),
1069 DEVMETHOD(device_attach, aml8726_mmc_attach),
1070 DEVMETHOD(device_detach, aml8726_mmc_detach),
1071 DEVMETHOD(device_shutdown, aml8726_mmc_shutdown),
1074 DEVMETHOD(bus_read_ivar, aml8726_mmc_read_ivar),
1075 DEVMETHOD(bus_write_ivar, aml8726_mmc_write_ivar),
1077 /* MMC bridge interface */
1078 DEVMETHOD(mmcbr_update_ios, aml8726_mmc_update_ios),
1079 DEVMETHOD(mmcbr_request, aml8726_mmc_request),
1080 DEVMETHOD(mmcbr_get_ro, aml8726_mmc_get_ro),
1081 DEVMETHOD(mmcbr_acquire_host, aml8726_mmc_acquire_host),
1082 DEVMETHOD(mmcbr_release_host, aml8726_mmc_release_host),
1087 static driver_t aml8726_mmc_driver = {
1089 aml8726_mmc_methods,
1090 sizeof(struct aml8726_mmc_softc),
1093 static devclass_t aml8726_mmc_devclass;
1095 DRIVER_MODULE(aml8726_mmc, simplebus, aml8726_mmc_driver,
1096 aml8726_mmc_devclass, NULL, NULL);
1097 MODULE_DEPEND(aml8726_mmc, aml8726_gpio, 1, 1, 1);
1098 MMC_DECLARE_BRIDGE(aml8726_mmc);