2 * Copyright 2013-2015 John Wehle <john@feith.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
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12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Amlogic aml8726 PIC driver.
30 * The current implementation doesn't include support for FIQ.
32 * There is a set of four interrupt controllers per cpu located in adjacent
33 * memory addresses (the set for cpu 1 starts right after the set for cpu 0)
34 * ... this allows for interrupt handling to be spread across the cpus.
36 * The multicore chips also have a GIC ... typically they run SMP kernels
37 * which include the GIC driver in which case this driver is simply used
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
44 #include <sys/param.h>
45 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/module.h>
50 #include <sys/resource.h>
53 #include <machine/bus.h>
54 #include <machine/intr.h>
56 #include <dev/fdt/fdt_common.h>
57 #include <dev/ofw/ofw_bus.h>
58 #include <dev/ofw/ofw_bus_subr.h>
60 struct aml8726_pic_softc {
62 struct resource * res[1];
65 static struct resource_spec aml8726_pic_spec[] = {
66 { SYS_RES_MEMORY, 0, RF_ACTIVE },
71 * devclass_get_device / device_get_softc could be used
72 * to dynamically locate this, however the pic is a
73 * required device which can't be unloaded so there's
74 * no need for the overhead.
76 static struct aml8726_pic_softc *aml8726_pic_sc = NULL;
78 #define AML_PIC_NCNTRLS 4
79 #define AML_PIC_IRQS_PER_CNTRL 32
81 #define AML_PIC_NIRQS (AML_PIC_NCNTRLS * AML_PIC_IRQS_PER_CNTRL)
83 #define AML_PIC_0_STAT_REG 0
84 #define AML_PIC_0_STAT_CLR_REG 4
85 #define AML_PIC_0_MASK_REG 8
86 #define AML_PIC_0_FIRQ_SEL 12
88 #define AML_PIC_1_STAT_REG 16
89 #define AML_PIC_1_STAT_CLR_REG 20
90 #define AML_PIC_1_MASK_REG 24
91 #define AML_PIC_1_FIRQ_SEL 28
93 #define AML_PIC_2_STAT_REG 32
94 #define AML_PIC_2_STAT_CLR_REG 36
95 #define AML_PIC_2_MASK_REG 40
96 #define AML_PIC_2_FIRQ_SEL 44
98 #define AML_PIC_3_STAT_REG 48
99 #define AML_PIC_3_STAT_CLR_REG 52
100 #define AML_PIC_3_MASK_REG 56
101 #define AML_PIC_3_FIRQ_SEL 60
103 #define AML_PIC_CTRL(x) ((x) >> 5)
104 #define AML_PIC_BIT(x) (1 << ((x) & 0x1f))
106 #define AML_PIC_STAT_REG(x) (AML_PIC_0_STAT_REG + AML_PIC_CTRL(x) * 16)
107 #define AML_PIC_STAT_CLR_REG(x) (AML_PIC_0_STAT_CLR_REG + AML_PIC_CTRL(x) * 16)
108 #define AML_PIC_MASK_REG(x) (AML_PIC_0_MASK_REG + AML_PIC_CTRL(x) * 16)
109 #define AML_PIC_FIRQ_SEL(x) (AML_PIC_0_FIRQ_REG + AML_PIC_CTRL(x) * 16)
111 #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val))
112 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg)
113 #define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \
114 (BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE))
117 aml8726_pic_eoi(void *arg)
119 uintptr_t nb = (uintptr_t) arg;
121 if (nb >= AML_PIC_NIRQS)
124 arm_irq_memory_barrier(nb);
126 CSR_WRITE_4(aml8726_pic_sc, AML_PIC_STAT_CLR_REG(nb), AML_PIC_BIT(nb));
128 CSR_BARRIER(aml8726_pic_sc, AML_PIC_STAT_CLR_REG(nb));
132 aml8726_pic_probe(device_t dev)
135 if (!ofw_bus_status_okay(dev))
138 if (!ofw_bus_is_compatible(dev, "amlogic,aml8726-pic"))
141 device_set_desc(dev, "Amlogic aml8726 PIC");
143 return (BUS_PROBE_DEFAULT);
147 aml8726_pic_attach(device_t dev)
149 struct aml8726_pic_softc *sc = device_get_softc(dev);
152 /* There should be exactly one instance. */
153 if (aml8726_pic_sc != NULL)
158 if (bus_alloc_resources(dev, aml8726_pic_spec, sc->res)) {
159 device_printf(dev, "could not allocate resources for device\n");
164 * Disable, clear, and set the interrupts to normal mode.
166 for (i = 0; i < AML_PIC_NCNTRLS; i++) {
167 CSR_WRITE_4(sc, AML_PIC_0_MASK_REG + i * 16, 0);
168 CSR_WRITE_4(sc, AML_PIC_0_STAT_CLR_REG + i * 16, ~0u);
169 CSR_WRITE_4(sc, AML_PIC_0_FIRQ_SEL + i * 16, 0);
173 arm_post_filter = aml8726_pic_eoi;
175 device_printf(dev, "disabled in favor of gic\n");
184 aml8726_pic_detach(device_t dev)
190 static device_method_t aml8726_pic_methods[] = {
191 /* Device interface */
192 DEVMETHOD(device_probe, aml8726_pic_probe),
193 DEVMETHOD(device_attach, aml8726_pic_attach),
194 DEVMETHOD(device_detach, aml8726_pic_detach),
199 static driver_t aml8726_pic_driver = {
202 sizeof(struct aml8726_pic_softc),
205 static devclass_t aml8726_pic_devclass;
207 EARLY_DRIVER_MODULE(pic, simplebus, aml8726_pic_driver, aml8726_pic_devclass,
208 0, 0, BUS_PASS_INTERRUPT);
212 arm_get_next_irq(int last)
219 * The extra complexity is simply so that all IRQs are checked
220 * round robin so a particularly busy interrupt can't prevent
221 * other interrupts from being serviced.
224 start = (last + 1) % AML_PIC_NIRQS;
228 value = CSR_READ_4(aml8726_pic_sc, AML_PIC_STAT_REG(irq));
231 if ((value & AML_PIC_BIT(irq)) != 0)
234 irq = (irq + 1) % AML_PIC_NIRQS;
239 if ((irq % AML_PIC_IRQS_PER_CNTRL) == 0)
246 arm_mask_irq(uintptr_t nb)
250 if (nb >= AML_PIC_NIRQS)
253 mask = CSR_READ_4(aml8726_pic_sc, AML_PIC_MASK_REG(nb));
254 mask &= ~AML_PIC_BIT(nb);
255 CSR_WRITE_4(aml8726_pic_sc, AML_PIC_MASK_REG(nb), mask);
257 CSR_BARRIER(aml8726_pic_sc, AML_PIC_MASK_REG(nb));
259 aml8726_pic_eoi((void *)nb);
263 arm_unmask_irq(uintptr_t nb)
267 if (nb >= AML_PIC_NIRQS)
270 arm_irq_memory_barrier(nb);
272 mask = CSR_READ_4(aml8726_pic_sc, AML_PIC_MASK_REG(nb));
273 mask |= AML_PIC_BIT(nb);
274 CSR_WRITE_4(aml8726_pic_sc, AML_PIC_MASK_REG(nb), mask);
276 CSR_BARRIER(aml8726_pic_sc, AML_PIC_MASK_REG(nb));