sys/arm/amlogic/aml8726/aml8726_sdxc-m8.c

   1 /*-
   2  * Copyright 2015 John Wehle <john@feith.com>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 /*
  28  * Amlogic aml8726-m8 (and later) SDXC host controller driver.
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include <sys/param.h>
  35 #include <sys/systm.h>
  36 #include <sys/conf.h>
  37 #include <sys/bus.h>
  38 #include <sys/kernel.h>
  39 #include <sys/module.h>
  40 #include <sys/lock.h>
  41 #include <sys/mutex.h>
  42 #include <sys/resource.h>
  43 #include <sys/rman.h>
  44
  45 #include <sys/gpio.h>
  46
  47 #include <machine/bus.h>
  48 #include <machine/cpu.h>
  49
  50 #include <dev/fdt/fdt_common.h>
  51 #include <dev/ofw/ofw_bus.h>
  52 #include <dev/ofw/ofw_bus_subr.h>
  53
  54 #include <dev/mmc/bridge.h>
  55 #include <dev/mmc/mmcreg.h>
  56 #include <dev/mmc/mmcbrvar.h>
  57
  58 #include <arm/amlogic/aml8726/aml8726_soc.h>
  59 #include <arm/amlogic/aml8726/aml8726_sdxc-m8.h>
  60
  61 #include "gpio_if.h"
  62 #include "mmcbr_if.h"
  63
  64 /*
  65  * The table is sorted from highest to lowest and
  66  * last entry in the table is mark by freq == 0.
  67  */
  68 struct {
  69         uint32_t        voltage;
  70         uint32_t        freq;
  71         uint32_t        rx_phase;
  72 } aml8726_sdxc_clk_phases[] = {
  73         {
  74                 MMC_OCR_LOW_VOLTAGE | MMC_OCR_320_330 | MMC_OCR_330_340,
  75                 100000000,
  76                 1
  77         },
  78         {
  79                 MMC_OCR_320_330 | MMC_OCR_330_340,
  80                 45000000,
  81                 15
  82         },
  83         {
  84                 MMC_OCR_LOW_VOLTAGE,
  85                 45000000,
  86                 11
  87         },
  88         {
  89                 MMC_OCR_LOW_VOLTAGE | MMC_OCR_320_330 | MMC_OCR_330_340,
  90                 24999999,
  91                 15
  92         },
  93         {
  94                 MMC_OCR_LOW_VOLTAGE | MMC_OCR_320_330 | MMC_OCR_330_340,
  95                 5000000,
  96                 23
  97         },
  98         {
  99                 MMC_OCR_LOW_VOLTAGE | MMC_OCR_320_330 | MMC_OCR_330_340,
 100                 1000000,
 101                 55
 102         },
 103         {
 104                 MMC_OCR_LOW_VOLTAGE | MMC_OCR_320_330 | MMC_OCR_330_340,
 105                 0,
 106                 1061
 107         },
 108 };
 109
 110 struct aml8726_sdxc_gpio {
 111         device_t        dev;
 112         uint32_t        pin;
 113         uint32_t        pol;
 114 };
 115
 116 struct aml8726_sdxc_softc {
 117         device_t                dev;
 118         boolean_t               auto_fill_flush;
 119         struct resource         *res[2];
 120         struct mtx              mtx;
 121         struct callout          ch;
 122         unsigned int            ref_freq;
 123         struct aml8726_sdxc_gpio pwr_en;
 124         int                     voltages[2];
 125         struct aml8726_sdxc_gpio vselect;
 126         struct aml8726_sdxc_gpio card_rst;
 127         bus_dma_tag_t           dmatag;
 128         bus_dmamap_t            dmamap;
 129         void                    *ih_cookie;
 130         struct mmc_host         host;
 131         int                     bus_busy;
 132         struct {
 133                 uint32_t        time;
 134                 uint32_t        error;
 135         } busy;
 136         struct mmc_command      *cmd;
 137 };
 138
 139 static struct resource_spec aml8726_sdxc_spec[] = {
 140         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
 141         { SYS_RES_IRQ,          0,      RF_ACTIVE },
 142         { -1, 0 }
 143 };
 144
 145 #define AML_SDXC_LOCK(sc)               mtx_lock(&(sc)->mtx)
 146 #define AML_SDXC_UNLOCK(sc)             mtx_unlock(&(sc)->mtx)
 147 #define AML_SDXC_LOCK_ASSERT(sc)        mtx_assert(&(sc)->mtx, MA_OWNED)
 148 #define AML_SDXC_LOCK_INIT(sc)          \
 149     mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev),        \
 150     "sdxc", MTX_DEF)
 151 #define AML_SDXC_LOCK_DESTROY(sc)       mtx_destroy(&(sc)->mtx);
 152
 153 #define CSR_WRITE_4(sc, reg, val)       bus_write_4((sc)->res[0], reg, (val))
 154 #define CSR_READ_4(sc, reg)             bus_read_4((sc)->res[0], reg)
 155 #define CSR_BARRIER(sc, reg)            bus_barrier((sc)->res[0], reg, 4, \
 156     (BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE))
 157
 158 #define PIN_ON_FLAG(pol)                ((pol) == 0 ? \
 159     GPIO_PIN_LOW : GPIO_PIN_HIGH)
 160 #define PIN_OFF_FLAG(pol)               ((pol) == 0 ? \
 161     GPIO_PIN_HIGH : GPIO_PIN_LOW)
 162
 163 #define msecs_to_ticks(ms)              (((ms)*hz)/1000 + 1)
 164
 165 static void aml8726_sdxc_timeout(void *arg);
 166
 167 static void
 168 aml8726_sdxc_mapmem(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 169 {
 170         bus_addr_t *busaddrp;
 171
 172         /*
 173          * There should only be one bus space address since
 174          * bus_dma_tag_create was called with nsegments = 1.
 175          */
 176
 177          busaddrp = (bus_addr_t *)arg;
 178          *busaddrp = segs->ds_addr;
 179 }
 180
 181 static int
 182 aml8726_sdxc_power_off(struct aml8726_sdxc_softc *sc)
 183 {
 184
 185         if (sc->pwr_en.dev == NULL)
 186                 return (0);
 187
 188         return (GPIO_PIN_SET(sc->pwr_en.dev, sc->pwr_en.pin,
 189             PIN_OFF_FLAG(sc->pwr_en.pol)));
 190 }
 191
 192 static int
 193 aml8726_sdxc_power_on(struct aml8726_sdxc_softc *sc)
 194 {
 195
 196         if (sc->pwr_en.dev == NULL)
 197                 return (0);
 198
 199         return (GPIO_PIN_SET(sc->pwr_en.dev, sc->pwr_en.pin,
 200             PIN_ON_FLAG(sc->pwr_en.pol)));
 201 }
 202
 203 static void
 204 aml8726_sdxc_soft_reset(struct aml8726_sdxc_softc *sc)
 205 {
 206
 207         CSR_WRITE_4(sc, AML_SDXC_SOFT_RESET_REG, AML_SDXC_SOFT_RESET);
 208         CSR_BARRIER(sc, AML_SDXC_SOFT_RESET_REG);
 209         DELAY(5);
 210 }
 211
 212 static void
 213 aml8726_sdxc_engage_dma(struct aml8726_sdxc_softc *sc)
 214 {
 215         int i;
 216         uint32_t pdmar;
 217         uint32_t sr;
 218         struct mmc_data *data;
 219
 220         data = sc->cmd->data;
 221
 222         if (data == NULL || data->len == 0)
 223                 return;
 224
 225         /*
 226          * Engaging the DMA hardware is recommended before writing
 227          * to AML_SDXC_SEND_REG so that the FIFOs are ready to go.
 228          *
 229          * Presumably AML_SDXC_CNTRL_REG and AML_SDXC_DMA_ADDR_REG
 230          * must be set up prior to this happening.
 231          */
 232
 233         pdmar = CSR_READ_4(sc, AML_SDXC_PDMA_REG);
 234
 235         pdmar &= ~AML_SDXC_PDMA_RX_FLUSH_MODE_SW;
 236         pdmar |= AML_SDXC_PDMA_DMA_EN;
 237
 238         if (sc->auto_fill_flush == true) {
 239                 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
 240                 CSR_BARRIER(sc, AML_SDXC_PDMA_REG);
 241                 return;
 242         }
 243
 244         if ((data->flags & MMC_DATA_READ) != 0) {
 245                 pdmar |= AML_SDXC_PDMA_RX_FLUSH_MODE_SW;
 246                 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
 247                 CSR_BARRIER(sc, AML_SDXC_PDMA_REG);
 248         } else {
 249                 pdmar |= AML_SDXC_PDMA_TX_FILL;
 250                 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
 251                 CSR_BARRIER(sc, AML_SDXC_PDMA_REG);
 252
 253                 /*
 254                  * Wait up to 100us for data to show up.
 255                  */
 256                 for (i = 0; i < 100; i++) {
 257                         sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG);
 258                         if ((sr & AML_SDXC_STATUS_TX_CNT_MASK) != 0)
 259                                 break;
 260                         DELAY(1);
 261                 }
 262                 if (i >= 100)
 263                         device_printf(sc->dev, "TX FIFO fill timeout\n");
 264         }
 265 }
 266
 267 static void
 268 aml8726_sdxc_disengage_dma(struct aml8726_sdxc_softc *sc)
 269 {
 270         int i;
 271         uint32_t pdmar;
 272         uint32_t sr;
 273         struct mmc_data *data;
 274
 275         data = sc->cmd->data;
 276
 277         if (data == NULL || data->len == 0)
 278                 return;
 279
 280         pdmar = CSR_READ_4(sc, AML_SDXC_PDMA_REG);
 281
 282         if (sc->auto_fill_flush == true) {
 283                 pdmar &= ~AML_SDXC_PDMA_DMA_EN;
 284                 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
 285                 CSR_BARRIER(sc, AML_SDXC_PDMA_REG);
 286                 return;
 287         }
 288
 289         if ((data->flags & MMC_DATA_READ) != 0) {
 290                 pdmar |= AML_SDXC_PDMA_RX_FLUSH_NOW;
 291                 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
 292                 CSR_BARRIER(sc, AML_SDXC_PDMA_REG);
 293
 294                 /*
 295                  * Wait up to 100us for data to drain.
 296                  */
 297                 for (i = 0; i < 100; i++) {
 298                         sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG);
 299                         if ((sr & AML_SDXC_STATUS_RX_CNT_MASK) == 0)
 300                                 break;
 301                         DELAY(1);
 302                 }
 303                 if (i >= 100)
 304                         device_printf(sc->dev, "RX FIFO drain timeout\n");
 305         }
 306
 307         pdmar &= ~(AML_SDXC_PDMA_DMA_EN | AML_SDXC_PDMA_RX_FLUSH_MODE_SW);
 308
 309         CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
 310         CSR_BARRIER(sc, AML_SDXC_PDMA_REG);
 311 }
 312
 313 static int
 314 aml8726_sdxc_start_command(struct aml8726_sdxc_softc *sc,
 315     struct mmc_command *cmd)
 316 {
 317         bus_addr_t baddr;
 318         uint32_t block_size;
 319         uint32_t ctlr;
 320         uint32_t ier;
 321         uint32_t sndr;
 322         uint32_t timeout;
 323         int error;
 324         struct mmc_data *data;
 325
 326         AML_SDXC_LOCK_ASSERT(sc);
 327
 328         if (cmd->opcode > 0x3f)
 329                 return (MMC_ERR_INVALID);
 330
 331         /*
 332          * Ensure the hardware state machine is in a known state.
 333          */
 334         aml8726_sdxc_soft_reset(sc);
 335
 336         sndr = cmd->opcode;
 337
 338         if ((cmd->flags & MMC_RSP_136) != 0) {
 339                 sndr |= AML_SDXC_SEND_CMD_HAS_RESP;
 340                 sndr |= AML_SDXC_SEND_RESP_136;
 341                 /*
 342                  * According to the SD spec the 136 bit response is
 343                  * used for getting the CID or CSD in which case the
 344                  * CRC7 is embedded in the contents rather than being
 345                  * calculated over the entire response (the controller
 346                  * always checks the CRC7 over the entire response).
 347                  */
 348                 sndr |= AML_SDXC_SEND_RESP_NO_CRC7_CHECK;
 349         } else if ((cmd->flags & MMC_RSP_PRESENT) != 0)
 350                 sndr |= AML_SDXC_SEND_CMD_HAS_RESP;
 351
 352         if ((cmd->flags & MMC_RSP_CRC) == 0)
 353                 sndr |= AML_SDXC_SEND_RESP_NO_CRC7_CHECK;
 354
 355         if (cmd->opcode == MMC_STOP_TRANSMISSION)
 356                 sndr |= AML_SDXC_SEND_DATA_STOP;
 357
 358         data = cmd->data;
 359
 360         baddr = 0;
 361         ctlr = CSR_READ_4(sc, AML_SDXC_CNTRL_REG);
 362         ier = AML_SDXC_IRQ_ENABLE_STANDARD;
 363         timeout = AML_SDXC_CMD_TIMEOUT;
 364
 365         ctlr &= ~AML_SDXC_CNTRL_PKG_LEN_MASK;
 366
 367         if (data && data->len &&
 368             (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) != 0) {
 369                 block_size = data->len;
 370
 371                 if ((data->flags & MMC_DATA_MULTI) != 0) {
 372                         block_size = MMC_SECTOR_SIZE;
 373                         if ((data->len % block_size) != 0)
 374                                 return (MMC_ERR_INVALID);
 375                 }
 376
 377                 if (block_size > 512)
 378                         return (MMC_ERR_INVALID);
 379
 380                 sndr |= AML_SDXC_SEND_CMD_HAS_DATA;
 381                 sndr |= ((data->flags & MMC_DATA_WRITE) != 0) ?
 382                     AML_SDXC_SEND_DATA_WRITE : 0;
 383                 sndr |= (((data->len / block_size) - 1) <<
 384                     AML_SDXC_SEND_REP_PKG_CNT_SHIFT);
 385
 386                 ctlr |= ((block_size < 512) ? block_size : 0) <<
 387                     AML_SDXC_CNTRL_PKG_LEN_SHIFT;
 388
 389                 ier &= ~AML_SDXC_IRQ_ENABLE_RESP_OK;
 390                 ier |= (sc->auto_fill_flush == true ||
 391                     (data->flags & MMC_DATA_WRITE) != 0) ?
 392                     AML_SDXC_IRQ_ENABLE_DMA_DONE :
 393                     AML_SDXC_IRQ_ENABLE_TRANSFER_DONE_OK;
 394
 395                 error = bus_dmamap_load(sc->dmatag, sc->dmamap,
 396                     data->data, data->len, aml8726_sdxc_mapmem, &baddr,
 397                     BUS_DMA_NOWAIT);
 398                 if (error)
 399                         return (MMC_ERR_NO_MEMORY);
 400
 401                 if ((data->flags & MMC_DATA_READ) != 0) {
 402                         bus_dmamap_sync(sc->dmatag, sc->dmamap,
 403                             BUS_DMASYNC_PREREAD);
 404                         timeout = AML_SDXC_READ_TIMEOUT *
 405                             (data->len / block_size);
 406                 } else {
 407                         bus_dmamap_sync(sc->dmatag, sc->dmamap,
 408                             BUS_DMASYNC_PREWRITE);
 409                         timeout = AML_SDXC_WRITE_TIMEOUT *
 410                             (data->len / block_size);
 411                 }
 412         }
 413
 414         sc->cmd = cmd;
 415
 416         cmd->error = MMC_ERR_NONE;
 417
 418         sc->busy.time = 0;
 419         sc->busy.error = MMC_ERR_NONE;
 420
 421         if (timeout > AML_SDXC_MAX_TIMEOUT)
 422                 timeout = AML_SDXC_MAX_TIMEOUT;
 423
 424         callout_reset(&sc->ch, msecs_to_ticks(timeout),
 425             aml8726_sdxc_timeout, sc);
 426
 427         CSR_WRITE_4(sc, AML_SDXC_IRQ_ENABLE_REG, ier);
 428
 429         CSR_WRITE_4(sc, AML_SDXC_CNTRL_REG, ctlr);
 430         CSR_WRITE_4(sc, AML_SDXC_DMA_ADDR_REG, (uint32_t)baddr);
 431         CSR_WRITE_4(sc, AML_SDXC_CMD_ARGUMENT_REG, cmd->arg);
 432
 433         aml8726_sdxc_engage_dma(sc);
 434
 435         CSR_WRITE_4(sc, AML_SDXC_SEND_REG, sndr);
 436         CSR_BARRIER(sc, AML_SDXC_SEND_REG);
 437
 438         return (MMC_ERR_NONE);
 439 }
 440
 441 static void
 442 aml8726_sdxc_finish_command(struct aml8726_sdxc_softc *sc, int mmc_error)
 443 {
 444         int mmc_stop_error;
 445         struct mmc_command *cmd;
 446         struct mmc_command *stop_cmd;
 447         struct mmc_data *data;
 448
 449         AML_SDXC_LOCK_ASSERT(sc);
 450
 451         /* Clear all interrupts since the request is no longer in flight. */
 452         CSR_WRITE_4(sc, AML_SDXC_IRQ_STATUS_REG, AML_SDXC_IRQ_STATUS_CLEAR);
 453         CSR_BARRIER(sc, AML_SDXC_IRQ_STATUS_REG);
 454
 455         /* In some cases (e.g. finish called via timeout) this is a NOP. */
 456         callout_stop(&sc->ch);
 457
 458         cmd = sc->cmd;
 459         sc->cmd = NULL;
 460
 461         cmd->error = mmc_error;
 462
 463         data = cmd->data;
 464
 465         if (data && data->len
 466             && (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) != 0) {
 467                 if ((data->flags & MMC_DATA_READ) != 0)
 468                         bus_dmamap_sync(sc->dmatag, sc->dmamap,
 469                             BUS_DMASYNC_POSTREAD);
 470                 else
 471                         bus_dmamap_sync(sc->dmatag, sc->dmamap,
 472                             BUS_DMASYNC_POSTWRITE);
 473                 bus_dmamap_unload(sc->dmatag, sc->dmamap);
 474         }
 475
 476         /*
 477          * If there's a linked stop command, then start the stop command.
 478          * In order to establish a known state attempt the stop command
 479          * even if the original request encountered an error.
 480          */
 481
 482         stop_cmd = (cmd->mrq->stop != cmd) ? cmd->mrq->stop : NULL;
 483
 484         if (stop_cmd != NULL) {
 485
 486                 /*
 487                  * If the original command executed successfuly, then
 488                  * the hardware will also have automatically executed
 489                  * a stop command so don't bother with the one supplied
 490                  * with the original request.
 491                  */
 492
 493                 if (mmc_error == MMC_ERR_NONE) {
 494                         stop_cmd->error = MMC_ERR_NONE;
 495                         stop_cmd->resp[0] = cmd->resp[0];
 496                         stop_cmd->resp[1] = cmd->resp[1];
 497                         stop_cmd->resp[2] = cmd->resp[2];
 498                         stop_cmd->resp[3] = cmd->resp[3];
 499                 } else {
 500                         mmc_stop_error = aml8726_sdxc_start_command(sc,
 501                             stop_cmd);
 502                         if (mmc_stop_error == MMC_ERR_NONE) {
 503                                 AML_SDXC_UNLOCK(sc);
 504                                 return;
 505                         }
 506                         stop_cmd->error = mmc_stop_error;
 507                 }
 508         }
 509
 510         AML_SDXC_UNLOCK(sc);
 511
 512         /* Execute the callback after dropping the lock. */
 513         if (cmd->mrq != NULL)
 514                 cmd->mrq->done(cmd->mrq);
 515 }
 516
 517 static void
 518 aml8726_sdxc_timeout(void *arg)
 519 {
 520         struct aml8726_sdxc_softc *sc = (struct aml8726_sdxc_softc *)arg;
 521
 522         /*
 523          * The command failed to complete in time so forcefully
 524          * terminate it.
 525          */
 526         aml8726_sdxc_soft_reset(sc);
 527
 528         /*
 529          * Ensure the command has terminated before continuing on
 530          * to things such as bus_dmamap_sync / bus_dmamap_unload.
 531          */
 532         while ((CSR_READ_4(sc, AML_SDXC_STATUS_REG) &
 533             AML_SDXC_STATUS_BUSY) != 0)
 534                 cpu_spinwait();
 535
 536         aml8726_sdxc_finish_command(sc, MMC_ERR_TIMEOUT);
 537 }
 538
 539 static void
 540 aml8726_sdxc_busy_check(void *arg)
 541 {
 542         struct aml8726_sdxc_softc *sc = (struct aml8726_sdxc_softc *)arg;
 543         uint32_t sr;
 544
 545         sc->busy.time += AML_SDXC_BUSY_POLL_INTVL;
 546
 547         sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG);
 548
 549         if ((sr & AML_SDXC_STATUS_DAT0) == 0) {
 550                 if (sc->busy.time < AML_SDXC_BUSY_TIMEOUT) {
 551                         callout_reset(&sc->ch,
 552                             msecs_to_ticks(AML_SDXC_BUSY_POLL_INTVL),
 553                             aml8726_sdxc_busy_check, sc);
 554                         AML_SDXC_UNLOCK(sc);
 555                         return;
 556                 }
 557                 if (sc->busy.error == MMC_ERR_NONE)
 558                         sc->busy.error = MMC_ERR_TIMEOUT;
 559         }
 560
 561         aml8726_sdxc_finish_command(sc, sc->busy.error);
 562 }
 563
 564 static void
 565 aml8726_sdxc_intr(void *arg)
 566 {
 567         struct aml8726_sdxc_softc *sc = (struct aml8726_sdxc_softc *)arg;
 568         uint32_t isr;
 569         uint32_t pdmar;
 570         uint32_t sndr;
 571         uint32_t sr;
 572         int i;
 573         int mmc_error;
 574         int start;
 575         int stop;
 576
 577         AML_SDXC_LOCK(sc);
 578
 579         isr = CSR_READ_4(sc, AML_SDXC_IRQ_STATUS_REG);
 580         sndr = CSR_READ_4(sc, AML_SDXC_SEND_REG);
 581         sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG);
 582
 583         if (sc->cmd == NULL)
 584                 goto spurious;
 585
 586         mmc_error = MMC_ERR_NONE;
 587
 588         if ((isr & (AML_SDXC_IRQ_STATUS_TX_FIFO_EMPTY |
 589             AML_SDXC_IRQ_STATUS_RX_FIFO_FULL)) != 0)
 590                 mmc_error = MMC_ERR_FIFO;
 591         else if ((isr & (AML_SDXC_IRQ_ENABLE_A_PKG_CRC_ERR |
 592             AML_SDXC_IRQ_ENABLE_RESP_CRC_ERR)) != 0)
 593                 mmc_error = MMC_ERR_BADCRC;
 594         else if ((isr & (AML_SDXC_IRQ_ENABLE_A_PKG_TIMEOUT_ERR |
 595             AML_SDXC_IRQ_ENABLE_RESP_TIMEOUT_ERR)) != 0)
 596                 mmc_error = MMC_ERR_TIMEOUT;
 597         else if ((isr & (AML_SDXC_IRQ_STATUS_RESP_OK |
 598             AML_SDXC_IRQ_STATUS_DMA_DONE |
 599             AML_SDXC_IRQ_STATUS_TRANSFER_DONE_OK)) != 0) {
 600                 ;
 601         }
 602         else {
 603 spurious:
 604                 /*
 605                  * Clear spurious interrupts while leaving intacted any
 606                  * interrupts that may have occurred after we read the
 607                  * interrupt status register.
 608                  */
 609
 610                 CSR_WRITE_4(sc, AML_SDXC_IRQ_STATUS_REG,
 611                     (AML_SDXC_IRQ_STATUS_CLEAR & isr));
 612                 CSR_BARRIER(sc, AML_SDXC_IRQ_STATUS_REG);
 613                 AML_SDXC_UNLOCK(sc);
 614                 return;
 615         }
 616
 617         aml8726_sdxc_disengage_dma(sc);
 618
 619         if ((sndr & AML_SDXC_SEND_CMD_HAS_RESP) != 0) {
 620                 start = 0;
 621                 stop = 1;
 622                 if ((sndr & AML_SDXC_SEND_RESP_136) != 0) {
 623                         start = 1;
 624                         stop = start + 4;;
 625                 }
 626                 for (i = start; i < stop; i++) {
 627                         pdmar = CSR_READ_4(sc, AML_SDXC_PDMA_REG);
 628                         pdmar &= ~(AML_SDXC_PDMA_DMA_EN |
 629                             AML_SDXC_PDMA_RESP_INDEX_MASK);
 630                         pdmar |= i << AML_SDXC_PDMA_RESP_INDEX_SHIFT;
 631                         CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
 632                         sc->cmd->resp[(stop - 1) - i] = CSR_READ_4(sc,
 633                             AML_SDXC_CMD_ARGUMENT_REG);
 634                 }
 635         }
 636
 637         if ((sr & AML_SDXC_STATUS_BUSY) != 0 &&
 638             /*
 639              * A multiblock operation may keep the hardware
 640              * busy until stop transmission is executed.
 641              */
 642             (isr & (AML_SDXC_IRQ_STATUS_DMA_DONE |
 643             AML_SDXC_IRQ_STATUS_TRANSFER_DONE_OK)) == 0) {
 644                 if (mmc_error == MMC_ERR_NONE)
 645                         mmc_error = MMC_ERR_FAILED;
 646
 647                 /*
 648                  * Issue a soft reset to terminate the command.
 649                  *
 650                  * Ensure the command has terminated before continuing on
 651                  * to things such as bus_dmamap_sync / bus_dmamap_unload.
 652                  */
 653
 654                 aml8726_sdxc_soft_reset(sc);
 655
 656                 while ((CSR_READ_4(sc, AML_SDXC_STATUS_REG) &
 657                     AML_SDXC_STATUS_BUSY) != 0)
 658                         cpu_spinwait();
 659         }
 660
 661         /*
 662          * The stop command can be generated either manually or
 663          * automatically by the hardware if MISC_MANUAL_STOP_MODE
 664          * has not been set.  In either case check for busy.
 665          */
 666
 667         if (((sc->cmd->flags & MMC_RSP_BUSY) != 0 ||
 668             (sndr & AML_SDXC_SEND_INDEX_MASK) == MMC_STOP_TRANSMISSION) &&
 669             (sr & AML_SDXC_STATUS_DAT0) == 0) {
 670                 sc->busy.error = mmc_error;
 671                 callout_reset(&sc->ch,
 672                     msecs_to_ticks(AML_SDXC_BUSY_POLL_INTVL),
 673                     aml8726_sdxc_busy_check, sc);
 674                 CSR_WRITE_4(sc, AML_SDXC_IRQ_STATUS_REG,
 675                     (AML_SDXC_IRQ_STATUS_CLEAR & isr));
 676                 CSR_BARRIER(sc, AML_SDXC_IRQ_STATUS_REG);
 677                 AML_SDXC_UNLOCK(sc);
 678                 return;
 679         }
 680
 681         aml8726_sdxc_finish_command(sc, mmc_error);
 682 }
 683
 684 static int
 685 aml8726_sdxc_probe(device_t dev)
 686 {
 687
 688         if (!ofw_bus_status_okay(dev))
 689                 return (ENXIO);
 690
 691         if (!ofw_bus_is_compatible(dev, "amlogic,aml8726-sdxc-m8"))
 692                 return (ENXIO);
 693
 694         device_set_desc(dev, "Amlogic aml8726-m8 SDXC");
 695
 696         return (BUS_PROBE_DEFAULT);
 697 }
 698
 699 static int
 700 aml8726_sdxc_attach(device_t dev)
 701 {
 702         struct aml8726_sdxc_softc *sc = device_get_softc(dev);
 703         char *voltages;
 704         char *voltage;
 705         int error;
 706         int nvoltages;
 707         pcell_t prop[3];
 708         phandle_t node;
 709         ssize_t len;
 710         device_t child;
 711         uint32_t ectlr;
 712         uint32_t miscr;
 713         uint32_t pdmar;
 714
 715         sc->dev = dev;
 716
 717         sc->auto_fill_flush = false;
 718
 719         pdmar = AML_SDXC_PDMA_DMA_URGENT |
 720             (49 << AML_SDXC_PDMA_TX_THOLD_SHIFT) |
 721             (7 << AML_SDXC_PDMA_RX_THOLD_SHIFT) |
 722             (15 << AML_SDXC_PDMA_RD_BURST_SHIFT) |
 723             (7 << AML_SDXC_PDMA_WR_BURST_SHIFT);
 724
 725         miscr = (2 << AML_SDXC_MISC_WCRC_OK_PAT_SHIFT) |
 726             (5 << AML_SDXC_MISC_WCRC_ERR_PAT_SHIFT);
 727
 728         ectlr = (12 << AML_SDXC_ENH_CNTRL_SDIO_IRQ_PERIOD_SHIFT);
 729
 730         /*
 731          * Certain bitfields are dependent on the hardware revision.
 732          */
 733         switch (aml8726_soc_hw_rev) {
 734         case AML_SOC_HW_REV_M8:
 735                 switch (aml8726_soc_metal_rev) {
 736                 case AML_SOC_M8_METAL_REV_M2_A:
 737                         sc->auto_fill_flush = true;
 738                         miscr |= (6 << AML_SDXC_MISC_TXSTART_THOLD_SHIFT);
 739                         ectlr |= (64 << AML_SDXC_ENH_CNTRL_RX_FULL_THOLD_SHIFT) |
 740                             AML_SDXC_ENH_CNTRL_WR_RESP_MODE_SKIP_M8M2;
 741                         break;
 742                 default:
 743                         miscr |= (7 << AML_SDXC_MISC_TXSTART_THOLD_SHIFT);
 744                         ectlr |= (63 << AML_SDXC_ENH_CNTRL_RX_FULL_THOLD_SHIFT) |
 745                             AML_SDXC_ENH_CNTRL_DMA_NO_WR_RESP_CHECK_M8 |
 746                             (255 << AML_SDXC_ENH_CNTRL_RX_TIMEOUT_SHIFT_M8);
 747
 748                         break;
 749                 }
 750                 break;
 751         case AML_SOC_HW_REV_M8B:
 752                 miscr |= (7 << AML_SDXC_MISC_TXSTART_THOLD_SHIFT);
 753                 ectlr |= (63 << AML_SDXC_ENH_CNTRL_RX_FULL_THOLD_SHIFT) |
 754                     AML_SDXC_ENH_CNTRL_DMA_NO_WR_RESP_CHECK_M8 |
 755                     (255 << AML_SDXC_ENH_CNTRL_RX_TIMEOUT_SHIFT_M8);
 756                 break;
 757         default:
 758                 device_printf(dev, "unsupported SoC\n");
 759                 return (ENXIO);
 760                 /* NOTREACHED */
 761                 break;
 762         }
 763
 764         node = ofw_bus_get_node(dev);
 765
 766         len = OF_getencprop(node, "clock-frequency", prop, sizeof(prop));
 767         if ((len / sizeof(prop[0])) != 1 || prop[0] == 0) {
 768                 device_printf(dev,
 769                     "missing clock-frequency attribute in FDT\n");
 770                 return (ENXIO);
 771         }
 772
 773         sc->ref_freq = prop[0];
 774
 775         sc->pwr_en.dev = NULL;
 776
 777         len = OF_getencprop(node, "mmc-pwr-en", prop, sizeof(prop));
 778         if (len > 0) {
 779                 if ((len / sizeof(prop[0])) == 3) {
 780                         sc->pwr_en.dev = OF_device_from_xref(prop[0]);
 781                         sc->pwr_en.pin = prop[1];
 782                         sc->pwr_en.pol = prop[2];
 783                 }
 784
 785                 if (sc->pwr_en.dev == NULL) {
 786                         device_printf(dev,
 787                             "unable to process mmc-pwr-en attribute in FDT\n");
 788                         return (ENXIO);
 789                 }
 790
 791                 /* Turn off power and then configure the output driver. */
 792                 if (aml8726_sdxc_power_off(sc) != 0 ||
 793                     GPIO_PIN_SETFLAGS(sc->pwr_en.dev, sc->pwr_en.pin,
 794                     GPIO_PIN_OUTPUT) != 0) {
 795                         device_printf(dev,
 796                             "could not use gpio to control power\n");
 797                         return (ENXIO);
 798                 }
 799         }
 800
 801         len = OF_getprop_alloc(node, "mmc-voltages",
 802             sizeof(char), (void **)&voltages);
 803
 804         if (len < 0) {
 805                 device_printf(dev, "missing mmc-voltages attribute in FDT\n");
 806                 return (ENXIO);
 807         }
 808
 809         sc->voltages[0] = 0;
 810         sc->voltages[1] = 0;
 811
 812         voltage = voltages;
 813         nvoltages = 0;
 814
 815         while (len && nvoltages < 2) {
 816                 if (strncmp("1.8", voltage, len) == 0)
 817                         sc->voltages[nvoltages] = MMC_OCR_LOW_VOLTAGE;
 818                 else if (strncmp("3.3", voltage, len) == 0)
 819                         sc->voltages[nvoltages] = MMC_OCR_320_330 |
 820                             MMC_OCR_330_340;
 821                 else {
 822                         device_printf(dev,
 823                             "unknown voltage attribute %.*s in FDT\n",
 824                             len, voltage);
 825                         free(voltages, M_OFWPROP);
 826                         return (ENXIO);
 827                 }
 828
 829                 nvoltages++;
 830
 831                 /* queue up next string */
 832                 while (*voltage && len) {
 833                         voltage++;
 834                         len--;
 835                 }
 836                 if (len) {
 837                         voltage++;
 838                         len--;
 839                 }
 840         }
 841
 842         free(voltages, M_OFWPROP);
 843
 844         sc->vselect.dev = NULL;
 845
 846         len = OF_getencprop(node, "mmc-vselect", prop, sizeof(prop));
 847         if (len > 0) {
 848                 if ((len / sizeof(prop[0])) == 2) {
 849                         sc->vselect.dev = OF_device_from_xref(prop[0]);
 850                         sc->vselect.pin = prop[1];
 851                         sc->vselect.pol = 1;
 852                 }
 853
 854                 if (sc->vselect.dev == NULL) {
 855                         device_printf(dev,
 856                             "unable to process mmc-vselect attribute in FDT\n");
 857                         return (ENXIO);
 858                 }
 859
 860                 /*
 861                  * With the power off select voltage 0 and then
 862                  * configure the output driver.
 863                  */
 864                 if (GPIO_PIN_SET(sc->vselect.dev, sc->vselect.pin, 0) != 0 ||
 865                     GPIO_PIN_SETFLAGS(sc->vselect.dev, sc->vselect.pin,
 866                     GPIO_PIN_OUTPUT) != 0) {
 867                         device_printf(dev,
 868                             "could not use gpio to set voltage\n");
 869                         return (ENXIO);
 870                 }
 871         }
 872
 873         if (nvoltages == 0) {
 874                 device_printf(dev, "no voltages in FDT\n");
 875                 return (ENXIO);
 876         } else if (nvoltages == 1 && sc->vselect.dev != NULL) {
 877                 device_printf(dev, "only one voltage in FDT\n");
 878                 return (ENXIO);
 879         } else if (nvoltages == 2 && sc->vselect.dev == NULL) {
 880                 device_printf(dev, "too many voltages in FDT\n");
 881                 return (ENXIO);
 882         }
 883
 884         sc->card_rst.dev = NULL;
 885
 886         len = OF_getencprop(node, "mmc-rst", prop, sizeof(prop));
 887         if (len > 0) {
 888                 if ((len / sizeof(prop[0])) == 3) {
 889                         sc->card_rst.dev = OF_device_from_xref(prop[0]);
 890                         sc->card_rst.pin = prop[1];
 891                         sc->card_rst.pol = prop[2];
 892                 }
 893
 894                 if (sc->card_rst.dev == NULL) {
 895                         device_printf(dev,
 896                             "unable to process mmc-rst attribute in FDT\n");
 897                         return (ENXIO);
 898                 }
 899         }
 900
 901         if (bus_alloc_resources(dev, aml8726_sdxc_spec, sc->res)) {
 902                 device_printf(dev, "could not allocate resources for device\n");
 903                 return (ENXIO);
 904         }
 905
 906         AML_SDXC_LOCK_INIT(sc);
 907
 908         error = bus_dma_tag_create(bus_get_dma_tag(dev), AML_SDXC_ALIGN_DMA, 0,
 909             BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
 910             AML_SDXC_MAX_DMA, 1, AML_SDXC_MAX_DMA, 0, NULL, NULL, &sc->dmatag);
 911         if (error)
 912                 goto fail;
 913
 914         error = bus_dmamap_create(sc->dmatag, 0, &sc->dmamap);
 915
 916         if (error)
 917                 goto fail;
 918
 919         error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE,
 920             NULL, aml8726_sdxc_intr, sc, &sc->ih_cookie);
 921         if (error) {
 922                 device_printf(dev, "could not setup interrupt handler\n");
 923                 goto fail;
 924         }
 925
 926         callout_init_mtx(&sc->ch, &sc->mtx, CALLOUT_RETURNUNLOCKED);
 927
 928         sc->host.f_min = 200000;
 929         sc->host.f_max = 100000000;
 930         sc->host.host_ocr = sc->voltages[0] | sc->voltages[1];
 931         sc->host.caps = MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
 932             MMC_CAP_HSPEED;
 933
 934         aml8726_sdxc_soft_reset(sc);
 935
 936         CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
 937
 938         CSR_WRITE_4(sc, AML_SDXC_MISC_REG, miscr);
 939
 940         CSR_WRITE_4(sc, AML_SDXC_ENH_CNTRL_REG, ectlr);
 941
 942         child = device_add_child(dev, "mmc", -1);
 943
 944         if (!child) {
 945                 device_printf(dev, "could not add mmc\n");
 946                 error = ENXIO;
 947                 goto fail;
 948         }
 949
 950         error = device_probe_and_attach(child);
 951
 952         if (error) {
 953                 device_printf(dev, "could not attach mmc\n");
 954                 goto fail;
 955         }
 956
 957         return (0);
 958
 959 fail:
 960         if (sc->ih_cookie)
 961                 bus_teardown_intr(dev, sc->res[1], sc->ih_cookie);
 962
 963         if (sc->dmamap)
 964                 bus_dmamap_destroy(sc->dmatag, sc->dmamap);
 965
 966         if (sc->dmatag)
 967                 bus_dma_tag_destroy(sc->dmatag);
 968
 969         AML_SDXC_LOCK_DESTROY(sc);
 970
 971         (void)aml8726_sdxc_power_off(sc);
 972
 973         bus_release_resources(dev, aml8726_sdxc_spec, sc->res);
 974
 975         return (error);
 976 }
 977
 978 static int
 979 aml8726_sdxc_detach(device_t dev)
 980 {
 981         struct aml8726_sdxc_softc *sc = device_get_softc(dev);
 982
 983         AML_SDXC_LOCK(sc);
 984
 985         if (sc->cmd != NULL) {
 986                 AML_SDXC_UNLOCK(sc);
 987                 return (EBUSY);
 988         }
 989
 990         /*
 991          * Turn off the power, reset the hardware state machine,
 992          * and disable the interrupts.
 993          */
 994         aml8726_sdxc_power_off(sc);
 995         aml8726_sdxc_soft_reset(sc);
 996         CSR_WRITE_4(sc, AML_SDXC_IRQ_ENABLE_REG, 0);
 997
 998         AML_SDXC_UNLOCK(sc);
 999
1000         bus_generic_detach(dev);
1001
1002         bus_teardown_intr(dev, sc->res[1], sc->ih_cookie);
1003
1004         bus_dmamap_destroy(sc->dmatag, sc->dmamap);
1005
1006         bus_dma_tag_destroy(sc->dmatag);
1007
1008         AML_SDXC_LOCK_DESTROY(sc);
1009
1010         bus_release_resources(dev, aml8726_sdxc_spec, sc->res);
1011
1012         return (0);
1013 }
1014
1015 static int
1016 aml8726_sdxc_shutdown(device_t dev)
1017 {
1018         struct aml8726_sdxc_softc *sc = device_get_softc(dev);
1019
1020         /*
1021          * Turn off the power, reset the hardware state machine,
1022          * and disable the interrupts.
1023          */
1024         aml8726_sdxc_power_off(sc);
1025         aml8726_sdxc_soft_reset(sc);
1026         CSR_WRITE_4(sc, AML_SDXC_IRQ_ENABLE_REG, 0);
1027
1028         return (0);
1029 }
1030
1031 static int
1032 aml8726_sdxc_update_ios(device_t bus, device_t child)
1033 {
1034         struct aml8726_sdxc_softc *sc = device_get_softc(bus);
1035         struct mmc_ios *ios = &sc->host.ios;
1036         unsigned int divisor;
1037         int error;
1038         int i;
1039         uint32_t cctlr;
1040         uint32_t clk2r;
1041         uint32_t ctlr;
1042         uint32_t freq;
1043
1044         ctlr = (7 << AML_SDXC_CNTRL_TX_ENDIAN_SHIFT) |
1045             (7 << AML_SDXC_CNTRL_RX_ENDIAN_SHIFT) |
1046             (0xf << AML_SDXC_CNTRL_RX_PERIOD_SHIFT) |
1047             (0x7f << AML_SDXC_CNTRL_RX_TIMEOUT_SHIFT);
1048
1049         switch (ios->bus_width) {
1050         case bus_width_8:
1051                 ctlr |= AML_SDXC_CNTRL_BUS_WIDTH_8;
1052                 break;
1053         case bus_width_4:
1054                 ctlr |= AML_SDXC_CNTRL_BUS_WIDTH_4;
1055                 break;
1056         case bus_width_1:
1057                 ctlr |= AML_SDXC_CNTRL_BUS_WIDTH_1;
1058                 break;
1059         default:
1060                 return (EINVAL);
1061         }
1062
1063         CSR_WRITE_4(sc, AML_SDXC_CNTRL_REG, ctlr);
1064
1065         /*
1066          * Disable clocks and then clock module prior to setting desired values.
1067          */
1068         cctlr = CSR_READ_4(sc, AML_SDXC_CLK_CNTRL_REG);
1069         cctlr &= ~(AML_SDXC_CLK_CNTRL_TX_CLK_EN | AML_SDXC_CLK_CNTRL_RX_CLK_EN |
1070             AML_SDXC_CLK_CNTRL_SD_CLK_EN);
1071         CSR_WRITE_4(sc, AML_SDXC_CLK_CNTRL_REG, cctlr);
1072         CSR_BARRIER(sc, AML_SDXC_CLK_CNTRL_REG);
1073         cctlr &= ~AML_SDXC_CLK_CNTRL_CLK_MODULE_EN;
1074         CSR_WRITE_4(sc, AML_SDXC_CLK_CNTRL_REG, cctlr);
1075         CSR_BARRIER(sc, AML_SDXC_CLK_CNTRL_REG);
1076
1077         /*
1078          *                  aml8726-m8
1079          *
1080          * Clock select 1   fclk_div2 (1.275 GHz)
1081          */
1082         cctlr &= ~AML_SDXC_CLK_CNTRL_CLK_SEL_MASK;
1083         cctlr |= (1 << AML_SDXC_CLK_CNTRL_CLK_SEL_SHIFT);
1084
1085         divisor = sc->ref_freq / ios->clock - 1;
1086         if (divisor == 0 || divisor == -1)
1087                 divisor = 1;
1088         if ((sc->ref_freq / (divisor + 1)) > ios->clock)
1089                 divisor += 1;
1090         if (divisor > (AML_SDXC_CLK_CNTRL_CLK_DIV_MASK >>
1091             AML_SDXC_CLK_CNTRL_CLK_DIV_SHIFT))
1092                 divisor = AML_SDXC_CLK_CNTRL_CLK_DIV_MASK >>
1093                     AML_SDXC_CLK_CNTRL_CLK_DIV_SHIFT;
1094
1095         cctlr &= ~AML_SDXC_CLK_CNTRL_CLK_DIV_MASK;
1096         cctlr |= divisor << AML_SDXC_CLK_CNTRL_CLK_DIV_SHIFT;
1097
1098         cctlr &= ~AML_SDXC_CLK_CNTRL_MEM_PWR_MASK;
1099         cctlr |= AML_SDXC_CLK_CNTRL_MEM_PWR_ON;
1100
1101         CSR_WRITE_4(sc, AML_SDXC_CLK_CNTRL_REG, cctlr);
1102         CSR_BARRIER(sc, AML_SDXC_CLK_CNTRL_REG);
1103
1104         /*
1105          * Enable clock module and then clocks after setting desired values.
1106          */
1107         cctlr |= AML_SDXC_CLK_CNTRL_CLK_MODULE_EN;
1108         CSR_WRITE_4(sc, AML_SDXC_CLK_CNTRL_REG, cctlr);
1109         CSR_BARRIER(sc, AML_SDXC_CLK_CNTRL_REG);
1110         cctlr |= AML_SDXC_CLK_CNTRL_TX_CLK_EN | AML_SDXC_CLK_CNTRL_RX_CLK_EN |
1111             AML_SDXC_CLK_CNTRL_SD_CLK_EN;
1112         CSR_WRITE_4(sc, AML_SDXC_CLK_CNTRL_REG, cctlr);
1113         CSR_BARRIER(sc, AML_SDXC_CLK_CNTRL_REG);
1114
1115         freq = sc->ref_freq / divisor;
1116
1117         for (i = 0; aml8726_sdxc_clk_phases[i].voltage; i++) {
1118                 if ((aml8726_sdxc_clk_phases[i].voltage &
1119                     (1 << ios->vdd)) != 0 &&
1120                     freq > aml8726_sdxc_clk_phases[i].freq)
1121                         break;
1122                 if (aml8726_sdxc_clk_phases[i].freq == 0)
1123                         break;
1124         }
1125
1126         clk2r = (1 << AML_SDXC_CLK2_SD_PHASE_SHIFT) |
1127             (aml8726_sdxc_clk_phases[i].rx_phase <<
1128             AML_SDXC_CLK2_RX_PHASE_SHIFT);
1129         CSR_WRITE_4(sc, AML_SDXC_CLK2_REG, clk2r);
1130         CSR_BARRIER(sc, AML_SDXC_CLK2_REG);
1131
1132         error = 0;
1133
1134         switch (ios->power_mode) {
1135         case power_up:
1136                 /*
1137                  * Configure and power on the regulator so that the
1138                  * voltage stabilizes prior to powering on the card.
1139                  */
1140                 if (sc->vselect.dev != NULL) {
1141                         for (i = 0; i < 2; i++)
1142                                 if ((sc->voltages[i] & (1 << ios->vdd)) != 0)
1143                                         break;
1144                         if (i >= 2)
1145                                 return (EINVAL);
1146                         error = GPIO_PIN_SET(sc->vselect.dev,
1147                             sc->vselect.pin, i);
1148                 }
1149                 break;
1150         case power_on:
1151                 error = aml8726_sdxc_power_on(sc);
1152                 if (error)
1153                         break;
1154
1155                 if (sc->card_rst.dev != NULL) {
1156                         if (GPIO_PIN_SET(sc->card_rst.dev, sc->card_rst.pin,
1157                             PIN_ON_FLAG(sc->card_rst.pol)) != 0 ||
1158                             GPIO_PIN_SETFLAGS(sc->card_rst.dev,
1159                             sc->card_rst.pin,
1160                             GPIO_PIN_OUTPUT) != 0)
1161                                 error = ENXIO;
1162
1163                         DELAY(5);
1164
1165                         if (GPIO_PIN_SET(sc->card_rst.dev, sc->card_rst.pin,
1166                             PIN_OFF_FLAG(sc->card_rst.pol)) != 0)
1167                                 error = ENXIO;
1168
1169                         DELAY(5);
1170
1171                         if (error) {
1172                                 device_printf(sc->dev,
1173                                     "could not use gpio to reset card\n");
1174                                 break;
1175                         }
1176                 }
1177                 break;
1178         case power_off:
1179                 error = aml8726_sdxc_power_off(sc);
1180                 break;
1181         default:
1182                 return (EINVAL);
1183         }
1184
1185         return (error);
1186 }
1187
1188 static int
1189 aml8726_sdxc_request(device_t bus, device_t child, struct mmc_request *req)
1190 {
1191         struct aml8726_sdxc_softc *sc = device_get_softc(bus);
1192         int mmc_error;
1193
1194         AML_SDXC_LOCK(sc);
1195
1196         if (sc->cmd != NULL) {
1197                 AML_SDXC_UNLOCK(sc);
1198                 return (EBUSY);
1199         }
1200
1201         mmc_error = aml8726_sdxc_start_command(sc, req->cmd);
1202
1203         AML_SDXC_UNLOCK(sc);
1204
1205         /* Execute the callback after dropping the lock. */
1206         if (mmc_error != MMC_ERR_NONE) {
1207                 req->cmd->error = mmc_error;
1208                 req->done(req);
1209         }
1210
1211         return (0);
1212 }
1213
1214 static int
1215 aml8726_sdxc_read_ivar(device_t bus, device_t child,
1216     int which, uintptr_t *result)
1217 {
1218         struct aml8726_sdxc_softc *sc = device_get_softc(bus);
1219
1220         switch (which) {
1221         case MMCBR_IVAR_BUS_MODE:
1222                 *(int *)result = sc->host.ios.bus_mode;
1223                 break;
1224         case MMCBR_IVAR_BUS_WIDTH:
1225                 *(int *)result = sc->host.ios.bus_width;
1226                 break;
1227         case MMCBR_IVAR_CHIP_SELECT:
1228                 *(int *)result = sc->host.ios.chip_select;
1229                 break;
1230         case MMCBR_IVAR_CLOCK:
1231                 *(int *)result = sc->host.ios.clock;
1232                 break;
1233         case MMCBR_IVAR_F_MIN:
1234                 *(int *)result = sc->host.f_min;
1235                 break;
1236         case MMCBR_IVAR_F_MAX:
1237                 *(int *)result = sc->host.f_max;
1238                 break;
1239         case MMCBR_IVAR_HOST_OCR:
1240                 *(int *)result = sc->host.host_ocr;
1241                 break;
1242         case MMCBR_IVAR_MODE:
1243                 *(int *)result = sc->host.mode;
1244                 break;
1245         case MMCBR_IVAR_OCR:
1246                 *(int *)result = sc->host.ocr;
1247                 break;
1248         case MMCBR_IVAR_POWER_MODE:
1249                 *(int *)result = sc->host.ios.power_mode;
1250                 break;
1251         case MMCBR_IVAR_VDD:
1252                 *(int *)result = sc->host.ios.vdd;
1253                 break;
1254         case MMCBR_IVAR_CAPS:
1255                 *(int *)result = sc->host.caps;
1256                 break;
1257         case MMCBR_IVAR_MAX_DATA:
1258                 *(int *)result = AML_SDXC_MAX_DMA / MMC_SECTOR_SIZE;
1259                 break;
1260         default:
1261                 return (EINVAL);
1262         }
1263
1264         return (0);
1265 }
1266
1267 static int
1268 aml8726_sdxc_write_ivar(device_t bus, device_t child,
1269     int which, uintptr_t value)
1270 {
1271         struct aml8726_sdxc_softc *sc = device_get_softc(bus);
1272
1273         switch (which) {
1274         case MMCBR_IVAR_BUS_MODE:
1275                 sc->host.ios.bus_mode = value;
1276                 break;
1277         case MMCBR_IVAR_BUS_WIDTH:
1278                 sc->host.ios.bus_width = value;
1279                 break;
1280         case MMCBR_IVAR_CHIP_SELECT:
1281                 sc->host.ios.chip_select = value;
1282                 break;
1283         case MMCBR_IVAR_CLOCK:
1284                 sc->host.ios.clock = value;
1285                 break;
1286         case MMCBR_IVAR_MODE:
1287                 sc->host.mode = value;
1288                 break;
1289         case MMCBR_IVAR_OCR:
1290                 sc->host.ocr = value;
1291                 break;
1292         case MMCBR_IVAR_POWER_MODE:
1293                 sc->host.ios.power_mode = value;
1294                 break;
1295         case MMCBR_IVAR_VDD:
1296                 sc->host.ios.vdd = value;
1297                 break;
1298         /* These are read-only */
1299         case MMCBR_IVAR_CAPS:
1300         case MMCBR_IVAR_HOST_OCR:
1301         case MMCBR_IVAR_F_MIN:
1302         case MMCBR_IVAR_F_MAX:
1303         case MMCBR_IVAR_MAX_DATA:
1304         default:
1305                 return (EINVAL);
1306         }
1307
1308         return (0);
1309 }
1310
1311 static int
1312 aml8726_sdxc_get_ro(device_t bus, device_t child)
1313 {
1314
1315         return (0);
1316 }
1317
1318 static int
1319 aml8726_sdxc_acquire_host(device_t bus, device_t child)
1320 {
1321         struct aml8726_sdxc_softc *sc = device_get_softc(bus);
1322
1323         AML_SDXC_LOCK(sc);
1324
1325         while (sc->bus_busy)
1326                 mtx_sleep(sc, &sc->mtx, PZERO, "sdxc", hz / 5);
1327         sc->bus_busy++;
1328
1329         AML_SDXC_UNLOCK(sc);
1330
1331         return (0);
1332 }
1333
1334 static int
1335 aml8726_sdxc_release_host(device_t bus, device_t child)
1336 {
1337         struct aml8726_sdxc_softc *sc = device_get_softc(bus);
1338
1339         AML_SDXC_LOCK(sc);
1340
1341         sc->bus_busy--;
1342         wakeup(sc);
1343
1344         AML_SDXC_UNLOCK(sc);
1345
1346         return (0);
1347 }
1348
1349 static device_method_t aml8726_sdxc_methods[] = {
1350         /* Device interface */
1351         DEVMETHOD(device_probe,         aml8726_sdxc_probe),
1352         DEVMETHOD(device_attach,        aml8726_sdxc_attach),
1353         DEVMETHOD(device_detach,        aml8726_sdxc_detach),
1354         DEVMETHOD(device_shutdown,      aml8726_sdxc_shutdown),
1355
1356         /* Bus interface */
1357         DEVMETHOD(bus_read_ivar,        aml8726_sdxc_read_ivar),
1358         DEVMETHOD(bus_write_ivar,       aml8726_sdxc_write_ivar),
1359
1360         /* MMC bridge interface */
1361         DEVMETHOD(mmcbr_update_ios,     aml8726_sdxc_update_ios),
1362         DEVMETHOD(mmcbr_request,        aml8726_sdxc_request),
1363         DEVMETHOD(mmcbr_get_ro,         aml8726_sdxc_get_ro),
1364         DEVMETHOD(mmcbr_acquire_host,   aml8726_sdxc_acquire_host),
1365         DEVMETHOD(mmcbr_release_host,   aml8726_sdxc_release_host),
1366
1367         DEVMETHOD_END
1368 };
1369
1370 static driver_t aml8726_sdxc_driver = {
1371         "aml8726_sdxc",
1372         aml8726_sdxc_methods,
1373         sizeof(struct aml8726_sdxc_softc),
1374 };
1375
1376 static devclass_t aml8726_sdxc_devclass;
1377
1378 DRIVER_MODULE(aml8726_sdxc, simplebus, aml8726_sdxc_driver,
1379     aml8726_sdxc_devclass, 0, 0);
1380 MODULE_DEPEND(aml8726_sdxc, aml8726_gpio, 1, 1, 1);