sys/arm/amlogic/aml8726/aml8726_sdxc-m8.c

   1 /*-
   2  * Copyright 2015 John Wehle <john@feith.com>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 /*
  28  * Amlogic aml8726-m8 (and later) SDXC host controller driver.
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include <sys/param.h>
  35 #include <sys/systm.h>
  36 #include <sys/bus.h>
  37 #include <sys/kernel.h>
  38 #include <sys/module.h>
  39 #include <sys/lock.h>
  40 #include <sys/mutex.h>
  41 #include <sys/resource.h>
  42 #include <sys/rman.h>
  43
  44 #include <sys/gpio.h>
  45
  46 #include <machine/bus.h>
  47 #include <machine/cpu.h>
  48
  49 #include <dev/ofw/ofw_bus.h>
  50 #include <dev/ofw/ofw_bus_subr.h>
  51
  52 #include <dev/mmc/bridge.h>
  53 #include <dev/mmc/mmcreg.h>
  54 #include <dev/mmc/mmcbrvar.h>
  55
  56 #include <arm/amlogic/aml8726/aml8726_soc.h>
  57 #include <arm/amlogic/aml8726/aml8726_sdxc-m8.h>
  58
  59 #include "gpio_if.h"
  60 #include "mmcbr_if.h"
  61
  62 /*
  63  * The table is sorted from highest to lowest and
  64  * last entry in the table is mark by freq == 0.
  65  */
  66 struct {
  67         uint32_t        voltage;
  68         uint32_t        freq;
  69         uint32_t        rx_phase;
  70 } aml8726_sdxc_clk_phases[] = {
  71         {
  72                 MMC_OCR_LOW_VOLTAGE | MMC_OCR_320_330 | MMC_OCR_330_340,
  73                 100000000,
  74                 1
  75         },
  76         {
  77                 MMC_OCR_320_330 | MMC_OCR_330_340,
  78                 45000000,
  79                 15
  80         },
  81         {
  82                 MMC_OCR_LOW_VOLTAGE,
  83                 45000000,
  84                 11
  85         },
  86         {
  87                 MMC_OCR_LOW_VOLTAGE | MMC_OCR_320_330 | MMC_OCR_330_340,
  88                 24999999,
  89                 15
  90         },
  91         {
  92                 MMC_OCR_LOW_VOLTAGE | MMC_OCR_320_330 | MMC_OCR_330_340,
  93                 5000000,
  94                 23
  95         },
  96         {
  97                 MMC_OCR_LOW_VOLTAGE | MMC_OCR_320_330 | MMC_OCR_330_340,
  98                 1000000,
  99                 55
 100         },
 101         {
 102                 MMC_OCR_LOW_VOLTAGE | MMC_OCR_320_330 | MMC_OCR_330_340,
 103                 0,
 104                 1061
 105         },
 106 };
 107
 108 struct aml8726_sdxc_gpio {
 109         device_t        dev;
 110         uint32_t        pin;
 111         uint32_t        pol;
 112 };
 113
 114 struct aml8726_sdxc_softc {
 115         device_t                dev;
 116         boolean_t               auto_fill_flush;
 117         struct resource         *res[2];
 118         struct mtx              mtx;
 119         struct callout          ch;
 120         unsigned int            ref_freq;
 121         struct aml8726_sdxc_gpio pwr_en;
 122         int                     voltages[2];
 123         struct aml8726_sdxc_gpio vselect;
 124         struct aml8726_sdxc_gpio card_rst;
 125         bus_dma_tag_t           dmatag;
 126         bus_dmamap_t            dmamap;
 127         void                    *ih_cookie;
 128         struct mmc_host         host;
 129         int                     bus_busy;
 130         struct {
 131                 uint32_t        time;
 132                 uint32_t        error;
 133         } busy;
 134         struct mmc_command      *cmd;
 135 };
 136
 137 static struct resource_spec aml8726_sdxc_spec[] = {
 138         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
 139         { SYS_RES_IRQ,          0,      RF_ACTIVE },
 140         { -1, 0 }
 141 };
 142
 143 #define AML_SDXC_LOCK(sc)               mtx_lock(&(sc)->mtx)
 144 #define AML_SDXC_UNLOCK(sc)             mtx_unlock(&(sc)->mtx)
 145 #define AML_SDXC_LOCK_ASSERT(sc)        mtx_assert(&(sc)->mtx, MA_OWNED)
 146 #define AML_SDXC_LOCK_INIT(sc)          \
 147     mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev),        \
 148     "sdxc", MTX_DEF)
 149 #define AML_SDXC_LOCK_DESTROY(sc)       mtx_destroy(&(sc)->mtx);
 150
 151 #define CSR_WRITE_4(sc, reg, val)       bus_write_4((sc)->res[0], reg, (val))
 152 #define CSR_READ_4(sc, reg)             bus_read_4((sc)->res[0], reg)
 153 #define CSR_BARRIER(sc, reg)            bus_barrier((sc)->res[0], reg, 4, \
 154     (BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE))
 155
 156 #define PIN_ON_FLAG(pol)                ((pol) == 0 ? \
 157     GPIO_PIN_LOW : GPIO_PIN_HIGH)
 158 #define PIN_OFF_FLAG(pol)               ((pol) == 0 ? \
 159     GPIO_PIN_HIGH : GPIO_PIN_LOW)
 160
 161 #define msecs_to_ticks(ms)              (((ms)*hz)/1000 + 1)
 162
 163 static void aml8726_sdxc_timeout(void *arg);
 164
 165 static void
 166 aml8726_sdxc_mapmem(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 167 {
 168         bus_addr_t *busaddrp;
 169
 170         /*
 171          * There should only be one bus space address since
 172          * bus_dma_tag_create was called with nsegments = 1.
 173          */
 174
 175          busaddrp = (bus_addr_t *)arg;
 176          *busaddrp = segs->ds_addr;
 177 }
 178
 179 static int
 180 aml8726_sdxc_power_off(struct aml8726_sdxc_softc *sc)
 181 {
 182
 183         if (sc->pwr_en.dev == NULL)
 184                 return (0);
 185
 186         return (GPIO_PIN_SET(sc->pwr_en.dev, sc->pwr_en.pin,
 187             PIN_OFF_FLAG(sc->pwr_en.pol)));
 188 }
 189
 190 static int
 191 aml8726_sdxc_power_on(struct aml8726_sdxc_softc *sc)
 192 {
 193
 194         if (sc->pwr_en.dev == NULL)
 195                 return (0);
 196
 197         return (GPIO_PIN_SET(sc->pwr_en.dev, sc->pwr_en.pin,
 198             PIN_ON_FLAG(sc->pwr_en.pol)));
 199 }
 200
 201 static void
 202 aml8726_sdxc_soft_reset(struct aml8726_sdxc_softc *sc)
 203 {
 204
 205         CSR_WRITE_4(sc, AML_SDXC_SOFT_RESET_REG, AML_SDXC_SOFT_RESET);
 206         CSR_BARRIER(sc, AML_SDXC_SOFT_RESET_REG);
 207         DELAY(5);
 208 }
 209
 210 static void
 211 aml8726_sdxc_engage_dma(struct aml8726_sdxc_softc *sc)
 212 {
 213         int i;
 214         uint32_t pdmar;
 215         uint32_t sr;
 216         struct mmc_data *data;
 217
 218         data = sc->cmd->data;
 219
 220         if (data == NULL || data->len == 0)
 221                 return;
 222
 223         /*
 224          * Engaging the DMA hardware is recommended before writing
 225          * to AML_SDXC_SEND_REG so that the FIFOs are ready to go.
 226          *
 227          * Presumably AML_SDXC_CNTRL_REG and AML_SDXC_DMA_ADDR_REG
 228          * must be set up prior to this happening.
 229          */
 230
 231         pdmar = CSR_READ_4(sc, AML_SDXC_PDMA_REG);
 232
 233         pdmar &= ~AML_SDXC_PDMA_RX_FLUSH_MODE_SW;
 234         pdmar |= AML_SDXC_PDMA_DMA_EN;
 235
 236         if (sc->auto_fill_flush == true) {
 237                 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
 238                 CSR_BARRIER(sc, AML_SDXC_PDMA_REG);
 239                 return;
 240         }
 241
 242         if ((data->flags & MMC_DATA_READ) != 0) {
 243                 pdmar |= AML_SDXC_PDMA_RX_FLUSH_MODE_SW;
 244                 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
 245                 CSR_BARRIER(sc, AML_SDXC_PDMA_REG);
 246         } else {
 247                 pdmar |= AML_SDXC_PDMA_TX_FILL;
 248                 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
 249                 CSR_BARRIER(sc, AML_SDXC_PDMA_REG);
 250
 251                 /*
 252                  * Wait up to 100us for data to show up.
 253                  */
 254                 for (i = 0; i < 100; i++) {
 255                         sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG);
 256                         if ((sr & AML_SDXC_STATUS_TX_CNT_MASK) != 0)
 257                                 break;
 258                         DELAY(1);
 259                 }
 260                 if (i >= 100)
 261                         device_printf(sc->dev, "TX FIFO fill timeout\n");
 262         }
 263 }
 264
 265 static void
 266 aml8726_sdxc_disengage_dma(struct aml8726_sdxc_softc *sc)
 267 {
 268         int i;
 269         uint32_t pdmar;
 270         uint32_t sr;
 271         struct mmc_data *data;
 272
 273         data = sc->cmd->data;
 274
 275         if (data == NULL || data->len == 0)
 276                 return;
 277
 278         pdmar = CSR_READ_4(sc, AML_SDXC_PDMA_REG);
 279
 280         if (sc->auto_fill_flush == true) {
 281                 pdmar &= ~AML_SDXC_PDMA_DMA_EN;
 282                 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
 283                 CSR_BARRIER(sc, AML_SDXC_PDMA_REG);
 284                 return;
 285         }
 286
 287         if ((data->flags & MMC_DATA_READ) != 0) {
 288                 pdmar |= AML_SDXC_PDMA_RX_FLUSH_NOW;
 289                 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
 290                 CSR_BARRIER(sc, AML_SDXC_PDMA_REG);
 291
 292                 /*
 293                  * Wait up to 100us for data to drain.
 294                  */
 295                 for (i = 0; i < 100; i++) {
 296                         sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG);
 297                         if ((sr & AML_SDXC_STATUS_RX_CNT_MASK) == 0)
 298                                 break;
 299                         DELAY(1);
 300                 }
 301                 if (i >= 100)
 302                         device_printf(sc->dev, "RX FIFO drain timeout\n");
 303         }
 304
 305         pdmar &= ~(AML_SDXC_PDMA_DMA_EN | AML_SDXC_PDMA_RX_FLUSH_MODE_SW);
 306
 307         CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
 308         CSR_BARRIER(sc, AML_SDXC_PDMA_REG);
 309 }
 310
 311 static int
 312 aml8726_sdxc_start_command(struct aml8726_sdxc_softc *sc,
 313     struct mmc_command *cmd)
 314 {
 315         bus_addr_t baddr;
 316         uint32_t block_size;
 317         uint32_t ctlr;
 318         uint32_t ier;
 319         uint32_t sndr;
 320         uint32_t timeout;
 321         int error;
 322         struct mmc_data *data;
 323
 324         AML_SDXC_LOCK_ASSERT(sc);
 325
 326         if (cmd->opcode > 0x3f)
 327                 return (MMC_ERR_INVALID);
 328
 329         /*
 330          * Ensure the hardware state machine is in a known state.
 331          */
 332         aml8726_sdxc_soft_reset(sc);
 333
 334         sndr = cmd->opcode;
 335
 336         if ((cmd->flags & MMC_RSP_136) != 0) {
 337                 sndr |= AML_SDXC_SEND_CMD_HAS_RESP;
 338                 sndr |= AML_SDXC_SEND_RESP_136;
 339                 /*
 340                  * According to the SD spec the 136 bit response is
 341                  * used for getting the CID or CSD in which case the
 342                  * CRC7 is embedded in the contents rather than being
 343                  * calculated over the entire response (the controller
 344                  * always checks the CRC7 over the entire response).
 345                  */
 346                 sndr |= AML_SDXC_SEND_RESP_NO_CRC7_CHECK;
 347         } else if ((cmd->flags & MMC_RSP_PRESENT) != 0)
 348                 sndr |= AML_SDXC_SEND_CMD_HAS_RESP;
 349
 350         if ((cmd->flags & MMC_RSP_CRC) == 0)
 351                 sndr |= AML_SDXC_SEND_RESP_NO_CRC7_CHECK;
 352
 353         if (cmd->opcode == MMC_STOP_TRANSMISSION)
 354                 sndr |= AML_SDXC_SEND_DATA_STOP;
 355
 356         data = cmd->data;
 357
 358         baddr = 0;
 359         ctlr = CSR_READ_4(sc, AML_SDXC_CNTRL_REG);
 360         ier = AML_SDXC_IRQ_ENABLE_STANDARD;
 361         timeout = AML_SDXC_CMD_TIMEOUT;
 362
 363         ctlr &= ~AML_SDXC_CNTRL_PKG_LEN_MASK;
 364
 365         if (data && data->len &&
 366             (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) != 0) {
 367                 block_size = data->len;
 368
 369                 if ((data->flags & MMC_DATA_MULTI) != 0) {
 370                         block_size = MMC_SECTOR_SIZE;
 371                         if ((data->len % block_size) != 0)
 372                                 return (MMC_ERR_INVALID);
 373                 }
 374
 375                 if (block_size > 512)
 376                         return (MMC_ERR_INVALID);
 377
 378                 sndr |= AML_SDXC_SEND_CMD_HAS_DATA;
 379                 sndr |= ((data->flags & MMC_DATA_WRITE) != 0) ?
 380                     AML_SDXC_SEND_DATA_WRITE : 0;
 381                 sndr |= (((data->len / block_size) - 1) <<
 382                     AML_SDXC_SEND_REP_PKG_CNT_SHIFT);
 383
 384                 ctlr |= ((block_size < 512) ? block_size : 0) <<
 385                     AML_SDXC_CNTRL_PKG_LEN_SHIFT;
 386
 387                 ier &= ~AML_SDXC_IRQ_ENABLE_RESP_OK;
 388                 ier |= (sc->auto_fill_flush == true ||
 389                     (data->flags & MMC_DATA_WRITE) != 0) ?
 390                     AML_SDXC_IRQ_ENABLE_DMA_DONE :
 391                     AML_SDXC_IRQ_ENABLE_TRANSFER_DONE_OK;
 392
 393                 error = bus_dmamap_load(sc->dmatag, sc->dmamap,
 394                     data->data, data->len, aml8726_sdxc_mapmem, &baddr,
 395                     BUS_DMA_NOWAIT);
 396                 if (error)
 397                         return (MMC_ERR_NO_MEMORY);
 398
 399                 if ((data->flags & MMC_DATA_READ) != 0) {
 400                         bus_dmamap_sync(sc->dmatag, sc->dmamap,
 401                             BUS_DMASYNC_PREREAD);
 402                         timeout = AML_SDXC_READ_TIMEOUT *
 403                             (data->len / block_size);
 404                 } else {
 405                         bus_dmamap_sync(sc->dmatag, sc->dmamap,
 406                             BUS_DMASYNC_PREWRITE);
 407                         timeout = AML_SDXC_WRITE_TIMEOUT *
 408                             (data->len / block_size);
 409                 }
 410         }
 411
 412         sc->cmd = cmd;
 413
 414         cmd->error = MMC_ERR_NONE;
 415
 416         sc->busy.time = 0;
 417         sc->busy.error = MMC_ERR_NONE;
 418
 419         if (timeout > AML_SDXC_MAX_TIMEOUT)
 420                 timeout = AML_SDXC_MAX_TIMEOUT;
 421
 422         callout_reset(&sc->ch, msecs_to_ticks(timeout),
 423             aml8726_sdxc_timeout, sc);
 424
 425         CSR_WRITE_4(sc, AML_SDXC_IRQ_ENABLE_REG, ier);
 426
 427         CSR_WRITE_4(sc, AML_SDXC_CNTRL_REG, ctlr);
 428         CSR_WRITE_4(sc, AML_SDXC_DMA_ADDR_REG, (uint32_t)baddr);
 429         CSR_WRITE_4(sc, AML_SDXC_CMD_ARGUMENT_REG, cmd->arg);
 430
 431         aml8726_sdxc_engage_dma(sc);
 432
 433         CSR_WRITE_4(sc, AML_SDXC_SEND_REG, sndr);
 434         CSR_BARRIER(sc, AML_SDXC_SEND_REG);
 435
 436         return (MMC_ERR_NONE);
 437 }
 438
 439 static void
 440 aml8726_sdxc_finish_command(struct aml8726_sdxc_softc *sc, int mmc_error)
 441 {
 442         int mmc_stop_error;
 443         struct mmc_command *cmd;
 444         struct mmc_command *stop_cmd;
 445         struct mmc_data *data;
 446
 447         AML_SDXC_LOCK_ASSERT(sc);
 448
 449         /* Clear all interrupts since the request is no longer in flight. */
 450         CSR_WRITE_4(sc, AML_SDXC_IRQ_STATUS_REG, AML_SDXC_IRQ_STATUS_CLEAR);
 451         CSR_BARRIER(sc, AML_SDXC_IRQ_STATUS_REG);
 452
 453         /* In some cases (e.g. finish called via timeout) this is a NOP. */
 454         callout_stop(&sc->ch);
 455
 456         cmd = sc->cmd;
 457         sc->cmd = NULL;
 458
 459         cmd->error = mmc_error;
 460
 461         data = cmd->data;
 462
 463         if (data && data->len
 464             && (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) != 0) {
 465                 if ((data->flags & MMC_DATA_READ) != 0)
 466                         bus_dmamap_sync(sc->dmatag, sc->dmamap,
 467                             BUS_DMASYNC_POSTREAD);
 468                 else
 469                         bus_dmamap_sync(sc->dmatag, sc->dmamap,
 470                             BUS_DMASYNC_POSTWRITE);
 471                 bus_dmamap_unload(sc->dmatag, sc->dmamap);
 472         }
 473
 474         /*
 475          * If there's a linked stop command, then start the stop command.
 476          * In order to establish a known state attempt the stop command
 477          * even if the original request encountered an error.
 478          */
 479
 480         stop_cmd = (cmd->mrq->stop != cmd) ? cmd->mrq->stop : NULL;
 481
 482         if (stop_cmd != NULL) {
 483
 484                 /*
 485                  * If the original command executed successfully, then
 486                  * the hardware will also have automatically executed
 487                  * a stop command so don't bother with the one supplied
 488                  * with the original request.
 489                  */
 490
 491                 if (mmc_error == MMC_ERR_NONE) {
 492                         stop_cmd->error = MMC_ERR_NONE;
 493                         stop_cmd->resp[0] = cmd->resp[0];
 494                         stop_cmd->resp[1] = cmd->resp[1];
 495                         stop_cmd->resp[2] = cmd->resp[2];
 496                         stop_cmd->resp[3] = cmd->resp[3];
 497                 } else {
 498                         mmc_stop_error = aml8726_sdxc_start_command(sc,
 499                             stop_cmd);
 500                         if (mmc_stop_error == MMC_ERR_NONE) {
 501                                 AML_SDXC_UNLOCK(sc);
 502                                 return;
 503                         }
 504                         stop_cmd->error = mmc_stop_error;
 505                 }
 506         }
 507
 508         AML_SDXC_UNLOCK(sc);
 509
 510         /* Execute the callback after dropping the lock. */
 511         if (cmd->mrq != NULL)
 512                 cmd->mrq->done(cmd->mrq);
 513 }
 514
 515 static void
 516 aml8726_sdxc_timeout(void *arg)
 517 {
 518         struct aml8726_sdxc_softc *sc = (struct aml8726_sdxc_softc *)arg;
 519
 520         /*
 521          * The command failed to complete in time so forcefully
 522          * terminate it.
 523          */
 524         aml8726_sdxc_soft_reset(sc);
 525
 526         /*
 527          * Ensure the command has terminated before continuing on
 528          * to things such as bus_dmamap_sync / bus_dmamap_unload.
 529          */
 530         while ((CSR_READ_4(sc, AML_SDXC_STATUS_REG) &
 531             AML_SDXC_STATUS_BUSY) != 0)
 532                 cpu_spinwait();
 533
 534         aml8726_sdxc_finish_command(sc, MMC_ERR_TIMEOUT);
 535 }
 536
 537 static void
 538 aml8726_sdxc_busy_check(void *arg)
 539 {
 540         struct aml8726_sdxc_softc *sc = (struct aml8726_sdxc_softc *)arg;
 541         uint32_t sr;
 542
 543         sc->busy.time += AML_SDXC_BUSY_POLL_INTVL;
 544
 545         sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG);
 546
 547         if ((sr & AML_SDXC_STATUS_DAT0) == 0) {
 548                 if (sc->busy.time < AML_SDXC_BUSY_TIMEOUT) {
 549                         callout_reset(&sc->ch,
 550                             msecs_to_ticks(AML_SDXC_BUSY_POLL_INTVL),
 551                             aml8726_sdxc_busy_check, sc);
 552                         AML_SDXC_UNLOCK(sc);
 553                         return;
 554                 }
 555                 if (sc->busy.error == MMC_ERR_NONE)
 556                         sc->busy.error = MMC_ERR_TIMEOUT;
 557         }
 558
 559         aml8726_sdxc_finish_command(sc, sc->busy.error);
 560 }
 561
 562 static void
 563 aml8726_sdxc_intr(void *arg)
 564 {
 565         struct aml8726_sdxc_softc *sc = (struct aml8726_sdxc_softc *)arg;
 566         uint32_t isr;
 567         uint32_t pdmar;
 568         uint32_t sndr;
 569         uint32_t sr;
 570         int i;
 571         int mmc_error;
 572         int start;
 573         int stop;
 574
 575         AML_SDXC_LOCK(sc);
 576
 577         isr = CSR_READ_4(sc, AML_SDXC_IRQ_STATUS_REG);
 578         sndr = CSR_READ_4(sc, AML_SDXC_SEND_REG);
 579         sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG);
 580
 581         if (sc->cmd == NULL)
 582                 goto spurious;
 583
 584         mmc_error = MMC_ERR_NONE;
 585
 586         if ((isr & (AML_SDXC_IRQ_STATUS_TX_FIFO_EMPTY |
 587             AML_SDXC_IRQ_STATUS_RX_FIFO_FULL)) != 0)
 588                 mmc_error = MMC_ERR_FIFO;
 589         else if ((isr & (AML_SDXC_IRQ_ENABLE_A_PKG_CRC_ERR |
 590             AML_SDXC_IRQ_ENABLE_RESP_CRC_ERR)) != 0)
 591                 mmc_error = MMC_ERR_BADCRC;
 592         else if ((isr & (AML_SDXC_IRQ_ENABLE_A_PKG_TIMEOUT_ERR |
 593             AML_SDXC_IRQ_ENABLE_RESP_TIMEOUT_ERR)) != 0)
 594                 mmc_error = MMC_ERR_TIMEOUT;
 595         else if ((isr & (AML_SDXC_IRQ_STATUS_RESP_OK |
 596             AML_SDXC_IRQ_STATUS_DMA_DONE |
 597             AML_SDXC_IRQ_STATUS_TRANSFER_DONE_OK)) != 0) {
 598                 ;
 599         }
 600         else {
 601 spurious:
 602                 /*
 603                  * Clear spurious interrupts while leaving intacted any
 604                  * interrupts that may have occurred after we read the
 605                  * interrupt status register.
 606                  */
 607
 608                 CSR_WRITE_4(sc, AML_SDXC_IRQ_STATUS_REG,
 609                     (AML_SDXC_IRQ_STATUS_CLEAR & isr));
 610                 CSR_BARRIER(sc, AML_SDXC_IRQ_STATUS_REG);
 611                 AML_SDXC_UNLOCK(sc);
 612                 return;
 613         }
 614
 615         aml8726_sdxc_disengage_dma(sc);
 616
 617         if ((sndr & AML_SDXC_SEND_CMD_HAS_RESP) != 0) {
 618                 start = 0;
 619                 stop = 1;
 620                 if ((sndr & AML_SDXC_SEND_RESP_136) != 0) {
 621                         start = 1;
 622                         stop = start + 4;
 623                 }
 624                 for (i = start; i < stop; i++) {
 625                         pdmar = CSR_READ_4(sc, AML_SDXC_PDMA_REG);
 626                         pdmar &= ~(AML_SDXC_PDMA_DMA_EN |
 627                             AML_SDXC_PDMA_RESP_INDEX_MASK);
 628                         pdmar |= i << AML_SDXC_PDMA_RESP_INDEX_SHIFT;
 629                         CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
 630                         sc->cmd->resp[(stop - 1) - i] = CSR_READ_4(sc,
 631                             AML_SDXC_CMD_ARGUMENT_REG);
 632                 }
 633         }
 634
 635         if ((sr & AML_SDXC_STATUS_BUSY) != 0 &&
 636             /*
 637              * A multiblock operation may keep the hardware
 638              * busy until stop transmission is executed.
 639              */
 640             (isr & (AML_SDXC_IRQ_STATUS_DMA_DONE |
 641             AML_SDXC_IRQ_STATUS_TRANSFER_DONE_OK)) == 0) {
 642                 if (mmc_error == MMC_ERR_NONE)
 643                         mmc_error = MMC_ERR_FAILED;
 644
 645                 /*
 646                  * Issue a soft reset to terminate the command.
 647                  *
 648                  * Ensure the command has terminated before continuing on
 649                  * to things such as bus_dmamap_sync / bus_dmamap_unload.
 650                  */
 651
 652                 aml8726_sdxc_soft_reset(sc);
 653
 654                 while ((CSR_READ_4(sc, AML_SDXC_STATUS_REG) &
 655                     AML_SDXC_STATUS_BUSY) != 0)
 656                         cpu_spinwait();
 657         }
 658
 659         /*
 660          * The stop command can be generated either manually or
 661          * automatically by the hardware if MISC_MANUAL_STOP_MODE
 662          * has not been set.  In either case check for busy.
 663          */
 664
 665         if (((sc->cmd->flags & MMC_RSP_BUSY) != 0 ||
 666             (sndr & AML_SDXC_SEND_INDEX_MASK) == MMC_STOP_TRANSMISSION) &&
 667             (sr & AML_SDXC_STATUS_DAT0) == 0) {
 668                 sc->busy.error = mmc_error;
 669                 callout_reset(&sc->ch,
 670                     msecs_to_ticks(AML_SDXC_BUSY_POLL_INTVL),
 671                     aml8726_sdxc_busy_check, sc);
 672                 CSR_WRITE_4(sc, AML_SDXC_IRQ_STATUS_REG,
 673                     (AML_SDXC_IRQ_STATUS_CLEAR & isr));
 674                 CSR_BARRIER(sc, AML_SDXC_IRQ_STATUS_REG);
 675                 AML_SDXC_UNLOCK(sc);
 676                 return;
 677         }
 678
 679         aml8726_sdxc_finish_command(sc, mmc_error);
 680 }
 681
 682 static int
 683 aml8726_sdxc_probe(device_t dev)
 684 {
 685
 686         if (!ofw_bus_status_okay(dev))
 687                 return (ENXIO);
 688
 689         if (!ofw_bus_is_compatible(dev, "amlogic,aml8726-sdxc-m8"))
 690                 return (ENXIO);
 691
 692         device_set_desc(dev, "Amlogic aml8726-m8 SDXC");
 693
 694         return (BUS_PROBE_DEFAULT);
 695 }
 696
 697 static int
 698 aml8726_sdxc_attach(device_t dev)
 699 {
 700         struct aml8726_sdxc_softc *sc = device_get_softc(dev);
 701         char *voltages;
 702         char *voltage;
 703         int error;
 704         int nvoltages;
 705         pcell_t prop[3];
 706         phandle_t node;
 707         ssize_t len;
 708         device_t child;
 709         uint32_t ectlr;
 710         uint32_t miscr;
 711         uint32_t pdmar;
 712
 713         sc->dev = dev;
 714
 715         sc->auto_fill_flush = false;
 716
 717         pdmar = AML_SDXC_PDMA_DMA_URGENT |
 718             (49 << AML_SDXC_PDMA_TX_THOLD_SHIFT) |
 719             (7 << AML_SDXC_PDMA_RX_THOLD_SHIFT) |
 720             (15 << AML_SDXC_PDMA_RD_BURST_SHIFT) |
 721             (7 << AML_SDXC_PDMA_WR_BURST_SHIFT);
 722
 723         miscr = (2 << AML_SDXC_MISC_WCRC_OK_PAT_SHIFT) |
 724             (5 << AML_SDXC_MISC_WCRC_ERR_PAT_SHIFT);
 725
 726         ectlr = (12 << AML_SDXC_ENH_CNTRL_SDIO_IRQ_PERIOD_SHIFT);
 727
 728         /*
 729          * Certain bitfields are dependent on the hardware revision.
 730          */
 731         switch (aml8726_soc_hw_rev) {
 732         case AML_SOC_HW_REV_M8:
 733                 switch (aml8726_soc_metal_rev) {
 734                 case AML_SOC_M8_METAL_REV_M2_A:
 735                         sc->auto_fill_flush = true;
 736                         miscr |= (6 << AML_SDXC_MISC_TXSTART_THOLD_SHIFT);
 737                         ectlr |= (64 << AML_SDXC_ENH_CNTRL_RX_FULL_THOLD_SHIFT) |
 738                             AML_SDXC_ENH_CNTRL_WR_RESP_MODE_SKIP_M8M2;
 739                         break;
 740                 default:
 741                         miscr |= (7 << AML_SDXC_MISC_TXSTART_THOLD_SHIFT);
 742                         ectlr |= (63 << AML_SDXC_ENH_CNTRL_RX_FULL_THOLD_SHIFT) |
 743                             AML_SDXC_ENH_CNTRL_DMA_NO_WR_RESP_CHECK_M8 |
 744                             (255 << AML_SDXC_ENH_CNTRL_RX_TIMEOUT_SHIFT_M8);
 745
 746                         break;
 747                 }
 748                 break;
 749         case AML_SOC_HW_REV_M8B:
 750                 miscr |= (7 << AML_SDXC_MISC_TXSTART_THOLD_SHIFT);
 751                 ectlr |= (63 << AML_SDXC_ENH_CNTRL_RX_FULL_THOLD_SHIFT) |
 752                     AML_SDXC_ENH_CNTRL_DMA_NO_WR_RESP_CHECK_M8 |
 753                     (255 << AML_SDXC_ENH_CNTRL_RX_TIMEOUT_SHIFT_M8);
 754                 break;
 755         default:
 756                 device_printf(dev, "unsupported SoC\n");
 757                 return (ENXIO);
 758                 /* NOTREACHED */
 759         }
 760
 761         node = ofw_bus_get_node(dev);
 762
 763         len = OF_getencprop(node, "clock-frequency", prop, sizeof(prop));
 764         if ((len / sizeof(prop[0])) != 1 || prop[0] == 0) {
 765                 device_printf(dev,
 766                     "missing clock-frequency attribute in FDT\n");
 767                 return (ENXIO);
 768         }
 769
 770         sc->ref_freq = prop[0];
 771
 772         sc->pwr_en.dev = NULL;
 773
 774         len = OF_getencprop(node, "mmc-pwr-en", prop, sizeof(prop));
 775         if (len > 0) {
 776                 if ((len / sizeof(prop[0])) == 3) {
 777                         sc->pwr_en.dev = OF_device_from_xref(prop[0]);
 778                         sc->pwr_en.pin = prop[1];
 779                         sc->pwr_en.pol = prop[2];
 780                 }
 781
 782                 if (sc->pwr_en.dev == NULL) {
 783                         device_printf(dev,
 784                             "unable to process mmc-pwr-en attribute in FDT\n");
 785                         return (ENXIO);
 786                 }
 787
 788                 /* Turn off power and then configure the output driver. */
 789                 if (aml8726_sdxc_power_off(sc) != 0 ||
 790                     GPIO_PIN_SETFLAGS(sc->pwr_en.dev, sc->pwr_en.pin,
 791                     GPIO_PIN_OUTPUT) != 0) {
 792                         device_printf(dev,
 793                             "could not use gpio to control power\n");
 794                         return (ENXIO);
 795                 }
 796         }
 797
 798         len = OF_getprop_alloc(node, "mmc-voltages",
 799             sizeof(char), (void **)&voltages);
 800
 801         if (len < 0) {
 802                 device_printf(dev, "missing mmc-voltages attribute in FDT\n");
 803                 return (ENXIO);
 804         }
 805
 806         sc->voltages[0] = 0;
 807         sc->voltages[1] = 0;
 808
 809         voltage = voltages;
 810         nvoltages = 0;
 811
 812         while (len && nvoltages < 2) {
 813                 if (strncmp("1.8", voltage, len) == 0)
 814                         sc->voltages[nvoltages] = MMC_OCR_LOW_VOLTAGE;
 815                 else if (strncmp("3.3", voltage, len) == 0)
 816                         sc->voltages[nvoltages] = MMC_OCR_320_330 |
 817                             MMC_OCR_330_340;
 818                 else {
 819                         device_printf(dev,
 820                             "unknown voltage attribute %.*s in FDT\n",
 821                             len, voltage);
 822                         OF_prop_free(voltages);
 823                         return (ENXIO);
 824                 }
 825
 826                 nvoltages++;
 827
 828                 /* queue up next string */
 829                 while (*voltage && len) {
 830                         voltage++;
 831                         len--;
 832                 }
 833                 if (len) {
 834                         voltage++;
 835                         len--;
 836                 }
 837         }
 838
 839         OF_prop_free(voltages);
 840
 841         sc->vselect.dev = NULL;
 842
 843         len = OF_getencprop(node, "mmc-vselect", prop, sizeof(prop));
 844         if (len > 0) {
 845                 if ((len / sizeof(prop[0])) == 2) {
 846                         sc->vselect.dev = OF_device_from_xref(prop[0]);
 847                         sc->vselect.pin = prop[1];
 848                         sc->vselect.pol = 1;
 849                 }
 850
 851                 if (sc->vselect.dev == NULL) {
 852                         device_printf(dev,
 853                             "unable to process mmc-vselect attribute in FDT\n");
 854                         return (ENXIO);
 855                 }
 856
 857                 /*
 858                  * With the power off select voltage 0 and then
 859                  * configure the output driver.
 860                  */
 861                 if (GPIO_PIN_SET(sc->vselect.dev, sc->vselect.pin, 0) != 0 ||
 862                     GPIO_PIN_SETFLAGS(sc->vselect.dev, sc->vselect.pin,
 863                     GPIO_PIN_OUTPUT) != 0) {
 864                         device_printf(dev,
 865                             "could not use gpio to set voltage\n");
 866                         return (ENXIO);
 867                 }
 868         }
 869
 870         if (nvoltages == 0) {
 871                 device_printf(dev, "no voltages in FDT\n");
 872                 return (ENXIO);
 873         } else if (nvoltages == 1 && sc->vselect.dev != NULL) {
 874                 device_printf(dev, "only one voltage in FDT\n");
 875                 return (ENXIO);
 876         } else if (nvoltages == 2 && sc->vselect.dev == NULL) {
 877                 device_printf(dev, "too many voltages in FDT\n");
 878                 return (ENXIO);
 879         }
 880
 881         sc->card_rst.dev = NULL;
 882
 883         len = OF_getencprop(node, "mmc-rst", prop, sizeof(prop));
 884         if (len > 0) {
 885                 if ((len / sizeof(prop[0])) == 3) {
 886                         sc->card_rst.dev = OF_device_from_xref(prop[0]);
 887                         sc->card_rst.pin = prop[1];
 888                         sc->card_rst.pol = prop[2];
 889                 }
 890
 891                 if (sc->card_rst.dev == NULL) {
 892                         device_printf(dev,
 893                             "unable to process mmc-rst attribute in FDT\n");
 894                         return (ENXIO);
 895                 }
 896         }
 897
 898         if (bus_alloc_resources(dev, aml8726_sdxc_spec, sc->res)) {
 899                 device_printf(dev, "could not allocate resources for device\n");
 900                 return (ENXIO);
 901         }
 902
 903         AML_SDXC_LOCK_INIT(sc);
 904
 905         error = bus_dma_tag_create(bus_get_dma_tag(dev), AML_SDXC_ALIGN_DMA, 0,
 906             BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
 907             AML_SDXC_MAX_DMA, 1, AML_SDXC_MAX_DMA, 0, NULL, NULL, &sc->dmatag);
 908         if (error)
 909                 goto fail;
 910
 911         error = bus_dmamap_create(sc->dmatag, 0, &sc->dmamap);
 912
 913         if (error)
 914                 goto fail;
 915
 916         error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE,
 917             NULL, aml8726_sdxc_intr, sc, &sc->ih_cookie);
 918         if (error) {
 919                 device_printf(dev, "could not setup interrupt handler\n");
 920                 goto fail;
 921         }
 922
 923         callout_init_mtx(&sc->ch, &sc->mtx, CALLOUT_RETURNUNLOCKED);
 924
 925         sc->host.f_min = 200000;
 926         sc->host.f_max = 100000000;
 927         sc->host.host_ocr = sc->voltages[0] | sc->voltages[1];
 928         sc->host.caps = MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
 929             MMC_CAP_HSPEED;
 930
 931         aml8726_sdxc_soft_reset(sc);
 932
 933         CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
 934
 935         CSR_WRITE_4(sc, AML_SDXC_MISC_REG, miscr);
 936
 937         CSR_WRITE_4(sc, AML_SDXC_ENH_CNTRL_REG, ectlr);
 938
 939         child = device_add_child(dev, "mmc", -1);
 940
 941         if (!child) {
 942                 device_printf(dev, "could not add mmc\n");
 943                 error = ENXIO;
 944                 goto fail;
 945         }
 946
 947         error = device_probe_and_attach(child);
 948
 949         if (error) {
 950                 device_printf(dev, "could not attach mmc\n");
 951                 goto fail;
 952         }
 953
 954         return (0);
 955
 956 fail:
 957         if (sc->ih_cookie)
 958                 bus_teardown_intr(dev, sc->res[1], sc->ih_cookie);
 959
 960         if (sc->dmamap)
 961                 bus_dmamap_destroy(sc->dmatag, sc->dmamap);
 962
 963         if (sc->dmatag)
 964                 bus_dma_tag_destroy(sc->dmatag);
 965
 966         AML_SDXC_LOCK_DESTROY(sc);
 967
 968         (void)aml8726_sdxc_power_off(sc);
 969
 970         bus_release_resources(dev, aml8726_sdxc_spec, sc->res);
 971
 972         return (error);
 973 }
 974
 975 static int
 976 aml8726_sdxc_detach(device_t dev)
 977 {
 978         struct aml8726_sdxc_softc *sc = device_get_softc(dev);
 979
 980         AML_SDXC_LOCK(sc);
 981
 982         if (sc->cmd != NULL) {
 983                 AML_SDXC_UNLOCK(sc);
 984                 return (EBUSY);
 985         }
 986
 987         /*
 988          * Turn off the power, reset the hardware state machine,
 989          * and disable the interrupts.
 990          */
 991         aml8726_sdxc_power_off(sc);
 992         aml8726_sdxc_soft_reset(sc);
 993         CSR_WRITE_4(sc, AML_SDXC_IRQ_ENABLE_REG, 0);
 994
 995         AML_SDXC_UNLOCK(sc);
 996
 997         bus_generic_detach(dev);
 998
 999         bus_teardown_intr(dev, sc->res[1], sc->ih_cookie);
1000
1001         bus_dmamap_destroy(sc->dmatag, sc->dmamap);
1002
1003         bus_dma_tag_destroy(sc->dmatag);
1004
1005         AML_SDXC_LOCK_DESTROY(sc);
1006
1007         bus_release_resources(dev, aml8726_sdxc_spec, sc->res);
1008
1009         return (0);
1010 }
1011
1012 static int
1013 aml8726_sdxc_shutdown(device_t dev)
1014 {
1015         struct aml8726_sdxc_softc *sc = device_get_softc(dev);
1016
1017         /*
1018          * Turn off the power, reset the hardware state machine,
1019          * and disable the interrupts.
1020          */
1021         aml8726_sdxc_power_off(sc);
1022         aml8726_sdxc_soft_reset(sc);
1023         CSR_WRITE_4(sc, AML_SDXC_IRQ_ENABLE_REG, 0);
1024
1025         return (0);
1026 }
1027
1028 static int
1029 aml8726_sdxc_update_ios(device_t bus, device_t child)
1030 {
1031         struct aml8726_sdxc_softc *sc = device_get_softc(bus);
1032         struct mmc_ios *ios = &sc->host.ios;
1033         unsigned int divisor;
1034         int error;
1035         int i;
1036         uint32_t cctlr;
1037         uint32_t clk2r;
1038         uint32_t ctlr;
1039         uint32_t freq;
1040
1041         ctlr = (7 << AML_SDXC_CNTRL_TX_ENDIAN_SHIFT) |
1042             (7 << AML_SDXC_CNTRL_RX_ENDIAN_SHIFT) |
1043             (0xf << AML_SDXC_CNTRL_RX_PERIOD_SHIFT) |
1044             (0x7f << AML_SDXC_CNTRL_RX_TIMEOUT_SHIFT);
1045
1046         switch (ios->bus_width) {
1047         case bus_width_8:
1048                 ctlr |= AML_SDXC_CNTRL_BUS_WIDTH_8;
1049                 break;
1050         case bus_width_4:
1051                 ctlr |= AML_SDXC_CNTRL_BUS_WIDTH_4;
1052                 break;
1053         case bus_width_1:
1054                 ctlr |= AML_SDXC_CNTRL_BUS_WIDTH_1;
1055                 break;
1056         default:
1057                 return (EINVAL);
1058         }
1059
1060         CSR_WRITE_4(sc, AML_SDXC_CNTRL_REG, ctlr);
1061
1062         /*
1063          * Disable clocks and then clock module prior to setting desired values.
1064          */
1065         cctlr = CSR_READ_4(sc, AML_SDXC_CLK_CNTRL_REG);
1066         cctlr &= ~(AML_SDXC_CLK_CNTRL_TX_CLK_EN | AML_SDXC_CLK_CNTRL_RX_CLK_EN |
1067             AML_SDXC_CLK_CNTRL_SD_CLK_EN);
1068         CSR_WRITE_4(sc, AML_SDXC_CLK_CNTRL_REG, cctlr);
1069         CSR_BARRIER(sc, AML_SDXC_CLK_CNTRL_REG);
1070         cctlr &= ~AML_SDXC_CLK_CNTRL_CLK_MODULE_EN;
1071         CSR_WRITE_4(sc, AML_SDXC_CLK_CNTRL_REG, cctlr);
1072         CSR_BARRIER(sc, AML_SDXC_CLK_CNTRL_REG);
1073
1074         /*
1075          *                  aml8726-m8
1076          *
1077          * Clock select 1   fclk_div2 (1.275 GHz)
1078          */
1079         cctlr &= ~AML_SDXC_CLK_CNTRL_CLK_SEL_MASK;
1080         cctlr |= (1 << AML_SDXC_CLK_CNTRL_CLK_SEL_SHIFT);
1081
1082         divisor = sc->ref_freq / ios->clock - 1;
1083         if (divisor == 0 || divisor == -1)
1084                 divisor = 1;
1085         if ((sc->ref_freq / (divisor + 1)) > ios->clock)
1086                 divisor += 1;
1087         if (divisor > (AML_SDXC_CLK_CNTRL_CLK_DIV_MASK >>
1088             AML_SDXC_CLK_CNTRL_CLK_DIV_SHIFT))
1089                 divisor = AML_SDXC_CLK_CNTRL_CLK_DIV_MASK >>
1090                     AML_SDXC_CLK_CNTRL_CLK_DIV_SHIFT;
1091
1092         cctlr &= ~AML_SDXC_CLK_CNTRL_CLK_DIV_MASK;
1093         cctlr |= divisor << AML_SDXC_CLK_CNTRL_CLK_DIV_SHIFT;
1094
1095         cctlr &= ~AML_SDXC_CLK_CNTRL_MEM_PWR_MASK;
1096         cctlr |= AML_SDXC_CLK_CNTRL_MEM_PWR_ON;
1097
1098         CSR_WRITE_4(sc, AML_SDXC_CLK_CNTRL_REG, cctlr);
1099         CSR_BARRIER(sc, AML_SDXC_CLK_CNTRL_REG);
1100
1101         /*
1102          * Enable clock module and then clocks after setting desired values.
1103          */
1104         cctlr |= AML_SDXC_CLK_CNTRL_CLK_MODULE_EN;
1105         CSR_WRITE_4(sc, AML_SDXC_CLK_CNTRL_REG, cctlr);
1106         CSR_BARRIER(sc, AML_SDXC_CLK_CNTRL_REG);
1107         cctlr |= AML_SDXC_CLK_CNTRL_TX_CLK_EN | AML_SDXC_CLK_CNTRL_RX_CLK_EN |
1108             AML_SDXC_CLK_CNTRL_SD_CLK_EN;
1109         CSR_WRITE_4(sc, AML_SDXC_CLK_CNTRL_REG, cctlr);
1110         CSR_BARRIER(sc, AML_SDXC_CLK_CNTRL_REG);
1111
1112         freq = sc->ref_freq / divisor;
1113
1114         for (i = 0; aml8726_sdxc_clk_phases[i].voltage; i++) {
1115                 if ((aml8726_sdxc_clk_phases[i].voltage &
1116                     (1 << ios->vdd)) != 0 &&
1117                     freq > aml8726_sdxc_clk_phases[i].freq)
1118                         break;
1119                 if (aml8726_sdxc_clk_phases[i].freq == 0)
1120                         break;
1121         }
1122
1123         clk2r = (1 << AML_SDXC_CLK2_SD_PHASE_SHIFT) |
1124             (aml8726_sdxc_clk_phases[i].rx_phase <<
1125             AML_SDXC_CLK2_RX_PHASE_SHIFT);
1126         CSR_WRITE_4(sc, AML_SDXC_CLK2_REG, clk2r);
1127         CSR_BARRIER(sc, AML_SDXC_CLK2_REG);
1128
1129         error = 0;
1130
1131         switch (ios->power_mode) {
1132         case power_up:
1133                 /*
1134                  * Configure and power on the regulator so that the
1135                  * voltage stabilizes prior to powering on the card.
1136                  */
1137                 if (sc->vselect.dev != NULL) {
1138                         for (i = 0; i < 2; i++)
1139                                 if ((sc->voltages[i] & (1 << ios->vdd)) != 0)
1140                                         break;
1141                         if (i >= 2)
1142                                 return (EINVAL);
1143                         error = GPIO_PIN_SET(sc->vselect.dev,
1144                             sc->vselect.pin, i);
1145                 }
1146                 break;
1147         case power_on:
1148                 error = aml8726_sdxc_power_on(sc);
1149                 if (error)
1150                         break;
1151
1152                 if (sc->card_rst.dev != NULL) {
1153                         if (GPIO_PIN_SET(sc->card_rst.dev, sc->card_rst.pin,
1154                             PIN_ON_FLAG(sc->card_rst.pol)) != 0 ||
1155                             GPIO_PIN_SETFLAGS(sc->card_rst.dev,
1156                             sc->card_rst.pin,
1157                             GPIO_PIN_OUTPUT) != 0)
1158                                 error = ENXIO;
1159
1160                         DELAY(5);
1161
1162                         if (GPIO_PIN_SET(sc->card_rst.dev, sc->card_rst.pin,
1163                             PIN_OFF_FLAG(sc->card_rst.pol)) != 0)
1164                                 error = ENXIO;
1165
1166                         DELAY(5);
1167
1168                         if (error) {
1169                                 device_printf(sc->dev,
1170                                     "could not use gpio to reset card\n");
1171                                 break;
1172                         }
1173                 }
1174                 break;
1175         case power_off:
1176                 error = aml8726_sdxc_power_off(sc);
1177                 break;
1178         default:
1179                 return (EINVAL);
1180         }
1181
1182         return (error);
1183 }
1184
1185 static int
1186 aml8726_sdxc_request(device_t bus, device_t child, struct mmc_request *req)
1187 {
1188         struct aml8726_sdxc_softc *sc = device_get_softc(bus);
1189         int mmc_error;
1190
1191         AML_SDXC_LOCK(sc);
1192
1193         if (sc->cmd != NULL) {
1194                 AML_SDXC_UNLOCK(sc);
1195                 return (EBUSY);
1196         }
1197
1198         mmc_error = aml8726_sdxc_start_command(sc, req->cmd);
1199
1200         AML_SDXC_UNLOCK(sc);
1201
1202         /* Execute the callback after dropping the lock. */
1203         if (mmc_error != MMC_ERR_NONE) {
1204                 req->cmd->error = mmc_error;
1205                 req->done(req);
1206         }
1207
1208         return (0);
1209 }
1210
1211 static int
1212 aml8726_sdxc_read_ivar(device_t bus, device_t child,
1213     int which, uintptr_t *result)
1214 {
1215         struct aml8726_sdxc_softc *sc = device_get_softc(bus);
1216
1217         switch (which) {
1218         case MMCBR_IVAR_BUS_MODE:
1219                 *(int *)result = sc->host.ios.bus_mode;
1220                 break;
1221         case MMCBR_IVAR_BUS_WIDTH:
1222                 *(int *)result = sc->host.ios.bus_width;
1223                 break;
1224         case MMCBR_IVAR_CHIP_SELECT:
1225                 *(int *)result = sc->host.ios.chip_select;
1226                 break;
1227         case MMCBR_IVAR_CLOCK:
1228                 *(int *)result = sc->host.ios.clock;
1229                 break;
1230         case MMCBR_IVAR_F_MIN:
1231                 *(int *)result = sc->host.f_min;
1232                 break;
1233         case MMCBR_IVAR_F_MAX:
1234                 *(int *)result = sc->host.f_max;
1235                 break;
1236         case MMCBR_IVAR_HOST_OCR:
1237                 *(int *)result = sc->host.host_ocr;
1238                 break;
1239         case MMCBR_IVAR_MODE:
1240                 *(int *)result = sc->host.mode;
1241                 break;
1242         case MMCBR_IVAR_OCR:
1243                 *(int *)result = sc->host.ocr;
1244                 break;
1245         case MMCBR_IVAR_POWER_MODE:
1246                 *(int *)result = sc->host.ios.power_mode;
1247                 break;
1248         case MMCBR_IVAR_VDD:
1249                 *(int *)result = sc->host.ios.vdd;
1250                 break;
1251         case MMCBR_IVAR_CAPS:
1252                 *(int *)result = sc->host.caps;
1253                 break;
1254         case MMCBR_IVAR_MAX_DATA:
1255                 *(int *)result = AML_SDXC_MAX_DMA / MMC_SECTOR_SIZE;
1256                 break;
1257         default:
1258                 return (EINVAL);
1259         }
1260
1261         return (0);
1262 }
1263
1264 static int
1265 aml8726_sdxc_write_ivar(device_t bus, device_t child,
1266     int which, uintptr_t value)
1267 {
1268         struct aml8726_sdxc_softc *sc = device_get_softc(bus);
1269
1270         switch (which) {
1271         case MMCBR_IVAR_BUS_MODE:
1272                 sc->host.ios.bus_mode = value;
1273                 break;
1274         case MMCBR_IVAR_BUS_WIDTH:
1275                 sc->host.ios.bus_width = value;
1276                 break;
1277         case MMCBR_IVAR_CHIP_SELECT:
1278                 sc->host.ios.chip_select = value;
1279                 break;
1280         case MMCBR_IVAR_CLOCK:
1281                 sc->host.ios.clock = value;
1282                 break;
1283         case MMCBR_IVAR_MODE:
1284                 sc->host.mode = value;
1285                 break;
1286         case MMCBR_IVAR_OCR:
1287                 sc->host.ocr = value;
1288                 break;
1289         case MMCBR_IVAR_POWER_MODE:
1290                 sc->host.ios.power_mode = value;
1291                 break;
1292         case MMCBR_IVAR_VDD:
1293                 sc->host.ios.vdd = value;
1294                 break;
1295         /* These are read-only */
1296         case MMCBR_IVAR_CAPS:
1297         case MMCBR_IVAR_HOST_OCR:
1298         case MMCBR_IVAR_F_MIN:
1299         case MMCBR_IVAR_F_MAX:
1300         case MMCBR_IVAR_MAX_DATA:
1301         default:
1302                 return (EINVAL);
1303         }
1304
1305         return (0);
1306 }
1307
1308 static int
1309 aml8726_sdxc_get_ro(device_t bus, device_t child)
1310 {
1311
1312         return (0);
1313 }
1314
1315 static int
1316 aml8726_sdxc_acquire_host(device_t bus, device_t child)
1317 {
1318         struct aml8726_sdxc_softc *sc = device_get_softc(bus);
1319
1320         AML_SDXC_LOCK(sc);
1321
1322         while (sc->bus_busy)
1323                 mtx_sleep(sc, &sc->mtx, PZERO, "sdxc", hz / 5);
1324         sc->bus_busy++;
1325
1326         AML_SDXC_UNLOCK(sc);
1327
1328         return (0);
1329 }
1330
1331 static int
1332 aml8726_sdxc_release_host(device_t bus, device_t child)
1333 {
1334         struct aml8726_sdxc_softc *sc = device_get_softc(bus);
1335
1336         AML_SDXC_LOCK(sc);
1337
1338         sc->bus_busy--;
1339         wakeup(sc);
1340
1341         AML_SDXC_UNLOCK(sc);
1342
1343         return (0);
1344 }
1345
1346 static device_method_t aml8726_sdxc_methods[] = {
1347         /* Device interface */
1348         DEVMETHOD(device_probe,         aml8726_sdxc_probe),
1349         DEVMETHOD(device_attach,        aml8726_sdxc_attach),
1350         DEVMETHOD(device_detach,        aml8726_sdxc_detach),
1351         DEVMETHOD(device_shutdown,      aml8726_sdxc_shutdown),
1352
1353         /* Bus interface */
1354         DEVMETHOD(bus_read_ivar,        aml8726_sdxc_read_ivar),
1355         DEVMETHOD(bus_write_ivar,       aml8726_sdxc_write_ivar),
1356
1357         /* MMC bridge interface */
1358         DEVMETHOD(mmcbr_update_ios,     aml8726_sdxc_update_ios),
1359         DEVMETHOD(mmcbr_request,        aml8726_sdxc_request),
1360         DEVMETHOD(mmcbr_get_ro,         aml8726_sdxc_get_ro),
1361         DEVMETHOD(mmcbr_acquire_host,   aml8726_sdxc_acquire_host),
1362         DEVMETHOD(mmcbr_release_host,   aml8726_sdxc_release_host),
1363
1364         DEVMETHOD_END
1365 };
1366
1367 static driver_t aml8726_sdxc_driver = {
1368         "aml8726_sdxc",
1369         aml8726_sdxc_methods,
1370         sizeof(struct aml8726_sdxc_softc),
1371 };
1372
1373 static devclass_t aml8726_sdxc_devclass;
1374
1375 DRIVER_MODULE(aml8726_sdxc, simplebus, aml8726_sdxc_driver,
1376     aml8726_sdxc_devclass, NULL, NULL);
1377 MODULE_DEPEND(aml8726_sdxc, aml8726_gpio, 1, 1, 1);
1378 MMC_DECLARE_BRIDGE(aml8726_sdxc);