sys/arm/amlogic/aml8726/aml8726_sdxc-m8.c

   1 /*-
   2  * Copyright 2015 John Wehle <john@feith.com>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 /*
  28  * Amlogic aml8726-m8 (and later) SDXC host controller driver.
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include <sys/param.h>
  35 #include <sys/systm.h>
  36 #include <sys/bus.h>
  37 #include <sys/kernel.h>
  38 #include <sys/module.h>
  39 #include <sys/lock.h>
  40 #include <sys/mutex.h>
  41 #include <sys/resource.h>
  42 #include <sys/rman.h>
  43
  44 #include <sys/gpio.h>
  45
  46 #include <machine/bus.h>
  47 #include <machine/cpu.h>
  48
  49 #include <dev/ofw/ofw_bus.h>
  50 #include <dev/ofw/ofw_bus_subr.h>
  51
  52 #include <dev/mmc/bridge.h>
  53 #include <dev/mmc/mmcreg.h>
  54 #include <dev/mmc/mmcbrvar.h>
  55
  56 #include <arm/amlogic/aml8726/aml8726_soc.h>
  57 #include <arm/amlogic/aml8726/aml8726_sdxc-m8.h>
  58
  59 #include "gpio_if.h"
  60 #include "mmcbr_if.h"
  61
  62 /*
  63  * The table is sorted from highest to lowest and
  64  * last entry in the table is mark by freq == 0.
  65  */
  66 struct {
  67         uint32_t        voltage;
  68         uint32_t        freq;
  69         uint32_t        rx_phase;
  70 } aml8726_sdxc_clk_phases[] = {
  71         {
  72                 MMC_OCR_LOW_VOLTAGE | MMC_OCR_320_330 | MMC_OCR_330_340,
  73                 100000000,
  74                 1
  75         },
  76         {
  77                 MMC_OCR_320_330 | MMC_OCR_330_340,
  78                 45000000,
  79                 15
  80         },
  81         {
  82                 MMC_OCR_LOW_VOLTAGE,
  83                 45000000,
  84                 11
  85         },
  86         {
  87                 MMC_OCR_LOW_VOLTAGE | MMC_OCR_320_330 | MMC_OCR_330_340,
  88                 24999999,
  89                 15
  90         },
  91         {
  92                 MMC_OCR_LOW_VOLTAGE | MMC_OCR_320_330 | MMC_OCR_330_340,
  93                 5000000,
  94                 23
  95         },
  96         {
  97                 MMC_OCR_LOW_VOLTAGE | MMC_OCR_320_330 | MMC_OCR_330_340,
  98                 1000000,
  99                 55
 100         },
 101         {
 102                 MMC_OCR_LOW_VOLTAGE | MMC_OCR_320_330 | MMC_OCR_330_340,
 103                 0,
 104                 1061
 105         },
 106 };
 107
 108 struct aml8726_sdxc_gpio {
 109         device_t        dev;
 110         uint32_t        pin;
 111         uint32_t        pol;
 112 };
 113
 114 struct aml8726_sdxc_softc {
 115         device_t                dev;
 116         boolean_t               auto_fill_flush;
 117         struct resource         *res[2];
 118         struct mtx              mtx;
 119         struct callout          ch;
 120         unsigned int            ref_freq;
 121         struct aml8726_sdxc_gpio pwr_en;
 122         int                     voltages[2];
 123         struct aml8726_sdxc_gpio vselect;
 124         struct aml8726_sdxc_gpio card_rst;
 125         bus_dma_tag_t           dmatag;
 126         bus_dmamap_t            dmamap;
 127         void                    *ih_cookie;
 128         struct mmc_host         host;
 129         int                     bus_busy;
 130         struct {
 131                 uint32_t        time;
 132                 uint32_t        error;
 133         } busy;
 134         struct mmc_command      *cmd;
 135 };
 136
 137 static struct resource_spec aml8726_sdxc_spec[] = {
 138         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
 139         { SYS_RES_IRQ,          0,      RF_ACTIVE },
 140         { -1, 0 }
 141 };
 142
 143 #define AML_SDXC_LOCK(sc)               mtx_lock(&(sc)->mtx)
 144 #define AML_SDXC_UNLOCK(sc)             mtx_unlock(&(sc)->mtx)
 145 #define AML_SDXC_LOCK_ASSERT(sc)        mtx_assert(&(sc)->mtx, MA_OWNED)
 146 #define AML_SDXC_LOCK_INIT(sc)          \
 147     mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev),        \
 148     "sdxc", MTX_DEF)
 149 #define AML_SDXC_LOCK_DESTROY(sc)       mtx_destroy(&(sc)->mtx);
 150
 151 #define CSR_WRITE_4(sc, reg, val)       bus_write_4((sc)->res[0], reg, (val))
 152 #define CSR_READ_4(sc, reg)             bus_read_4((sc)->res[0], reg)
 153 #define CSR_BARRIER(sc, reg)            bus_barrier((sc)->res[0], reg, 4, \
 154     (BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE))
 155
 156 #define PIN_ON_FLAG(pol)                ((pol) == 0 ? \
 157     GPIO_PIN_LOW : GPIO_PIN_HIGH)
 158 #define PIN_OFF_FLAG(pol)               ((pol) == 0 ? \
 159     GPIO_PIN_HIGH : GPIO_PIN_LOW)
 160
 161 #define msecs_to_ticks(ms)              (((ms)*hz)/1000 + 1)
 162
 163 static void aml8726_sdxc_timeout(void *arg);
 164
 165 static void
 166 aml8726_sdxc_mapmem(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 167 {
 168         bus_addr_t *busaddrp;
 169
 170         /*
 171          * There should only be one bus space address since
 172          * bus_dma_tag_create was called with nsegments = 1.
 173          */
 174
 175          busaddrp = (bus_addr_t *)arg;
 176          *busaddrp = segs->ds_addr;
 177 }
 178
 179 static int
 180 aml8726_sdxc_power_off(struct aml8726_sdxc_softc *sc)
 181 {
 182
 183         if (sc->pwr_en.dev == NULL)
 184                 return (0);
 185
 186         return (GPIO_PIN_SET(sc->pwr_en.dev, sc->pwr_en.pin,
 187             PIN_OFF_FLAG(sc->pwr_en.pol)));
 188 }
 189
 190 static int
 191 aml8726_sdxc_power_on(struct aml8726_sdxc_softc *sc)
 192 {
 193
 194         if (sc->pwr_en.dev == NULL)
 195                 return (0);
 196
 197         return (GPIO_PIN_SET(sc->pwr_en.dev, sc->pwr_en.pin,
 198             PIN_ON_FLAG(sc->pwr_en.pol)));
 199 }
 200
 201 static void
 202 aml8726_sdxc_soft_reset(struct aml8726_sdxc_softc *sc)
 203 {
 204
 205         CSR_WRITE_4(sc, AML_SDXC_SOFT_RESET_REG, AML_SDXC_SOFT_RESET);
 206         CSR_BARRIER(sc, AML_SDXC_SOFT_RESET_REG);
 207         DELAY(5);
 208 }
 209
 210 static void
 211 aml8726_sdxc_engage_dma(struct aml8726_sdxc_softc *sc)
 212 {
 213         int i;
 214         uint32_t pdmar;
 215         uint32_t sr;
 216         struct mmc_data *data;
 217
 218         data = sc->cmd->data;
 219
 220         if (data == NULL || data->len == 0)
 221                 return;
 222
 223         /*
 224          * Engaging the DMA hardware is recommended before writing
 225          * to AML_SDXC_SEND_REG so that the FIFOs are ready to go.
 226          *
 227          * Presumably AML_SDXC_CNTRL_REG and AML_SDXC_DMA_ADDR_REG
 228          * must be set up prior to this happening.
 229          */
 230
 231         pdmar = CSR_READ_4(sc, AML_SDXC_PDMA_REG);
 232
 233         pdmar &= ~AML_SDXC_PDMA_RX_FLUSH_MODE_SW;
 234         pdmar |= AML_SDXC_PDMA_DMA_EN;
 235
 236         if (sc->auto_fill_flush == true) {
 237                 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
 238                 CSR_BARRIER(sc, AML_SDXC_PDMA_REG);
 239                 return;
 240         }
 241
 242         if ((data->flags & MMC_DATA_READ) != 0) {
 243                 pdmar |= AML_SDXC_PDMA_RX_FLUSH_MODE_SW;
 244                 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
 245                 CSR_BARRIER(sc, AML_SDXC_PDMA_REG);
 246         } else {
 247                 pdmar |= AML_SDXC_PDMA_TX_FILL;
 248                 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
 249                 CSR_BARRIER(sc, AML_SDXC_PDMA_REG);
 250
 251                 /*
 252                  * Wait up to 100us for data to show up.
 253                  */
 254                 for (i = 0; i < 100; i++) {
 255                         sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG);
 256                         if ((sr & AML_SDXC_STATUS_TX_CNT_MASK) != 0)
 257                                 break;
 258                         DELAY(1);
 259                 }
 260                 if (i >= 100)
 261                         device_printf(sc->dev, "TX FIFO fill timeout\n");
 262         }
 263 }
 264
 265 static void
 266 aml8726_sdxc_disengage_dma(struct aml8726_sdxc_softc *sc)
 267 {
 268         int i;
 269         uint32_t pdmar;
 270         uint32_t sr;
 271         struct mmc_data *data;
 272
 273         data = sc->cmd->data;
 274
 275         if (data == NULL || data->len == 0)
 276                 return;
 277
 278         pdmar = CSR_READ_4(sc, AML_SDXC_PDMA_REG);
 279
 280         if (sc->auto_fill_flush == true) {
 281                 pdmar &= ~AML_SDXC_PDMA_DMA_EN;
 282                 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
 283                 CSR_BARRIER(sc, AML_SDXC_PDMA_REG);
 284                 return;
 285         }
 286
 287         if ((data->flags & MMC_DATA_READ) != 0) {
 288                 pdmar |= AML_SDXC_PDMA_RX_FLUSH_NOW;
 289                 CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
 290                 CSR_BARRIER(sc, AML_SDXC_PDMA_REG);
 291
 292                 /*
 293                  * Wait up to 100us for data to drain.
 294                  */
 295                 for (i = 0; i < 100; i++) {
 296                         sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG);
 297                         if ((sr & AML_SDXC_STATUS_RX_CNT_MASK) == 0)
 298                                 break;
 299                         DELAY(1);
 300                 }
 301                 if (i >= 100)
 302                         device_printf(sc->dev, "RX FIFO drain timeout\n");
 303         }
 304
 305         pdmar &= ~(AML_SDXC_PDMA_DMA_EN | AML_SDXC_PDMA_RX_FLUSH_MODE_SW);
 306
 307         CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
 308         CSR_BARRIER(sc, AML_SDXC_PDMA_REG);
 309 }
 310
 311 static int
 312 aml8726_sdxc_start_command(struct aml8726_sdxc_softc *sc,
 313     struct mmc_command *cmd)
 314 {
 315         bus_addr_t baddr;
 316         uint32_t block_size;
 317         uint32_t ctlr;
 318         uint32_t ier;
 319         uint32_t sndr;
 320         uint32_t timeout;
 321         int error;
 322         struct mmc_data *data;
 323
 324         AML_SDXC_LOCK_ASSERT(sc);
 325
 326         if (cmd->opcode > 0x3f)
 327                 return (MMC_ERR_INVALID);
 328
 329         /*
 330          * Ensure the hardware state machine is in a known state.
 331          */
 332         aml8726_sdxc_soft_reset(sc);
 333
 334         sndr = cmd->opcode;
 335
 336         if ((cmd->flags & MMC_RSP_136) != 0) {
 337                 sndr |= AML_SDXC_SEND_CMD_HAS_RESP;
 338                 sndr |= AML_SDXC_SEND_RESP_136;
 339                 /*
 340                  * According to the SD spec the 136 bit response is
 341                  * used for getting the CID or CSD in which case the
 342                  * CRC7 is embedded in the contents rather than being
 343                  * calculated over the entire response (the controller
 344                  * always checks the CRC7 over the entire response).
 345                  */
 346                 sndr |= AML_SDXC_SEND_RESP_NO_CRC7_CHECK;
 347         } else if ((cmd->flags & MMC_RSP_PRESENT) != 0)
 348                 sndr |= AML_SDXC_SEND_CMD_HAS_RESP;
 349
 350         if ((cmd->flags & MMC_RSP_CRC) == 0)
 351                 sndr |= AML_SDXC_SEND_RESP_NO_CRC7_CHECK;
 352
 353         if (cmd->opcode == MMC_STOP_TRANSMISSION)
 354                 sndr |= AML_SDXC_SEND_DATA_STOP;
 355
 356         data = cmd->data;
 357
 358         baddr = 0;
 359         ctlr = CSR_READ_4(sc, AML_SDXC_CNTRL_REG);
 360         ier = AML_SDXC_IRQ_ENABLE_STANDARD;
 361         timeout = AML_SDXC_CMD_TIMEOUT;
 362
 363         ctlr &= ~AML_SDXC_CNTRL_PKG_LEN_MASK;
 364
 365         if (data && data->len &&
 366             (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) != 0) {
 367                 block_size = data->len;
 368
 369                 if ((data->flags & MMC_DATA_MULTI) != 0) {
 370                         block_size = MMC_SECTOR_SIZE;
 371                         if ((data->len % block_size) != 0)
 372                                 return (MMC_ERR_INVALID);
 373                 }
 374
 375                 if (block_size > 512)
 376                         return (MMC_ERR_INVALID);
 377
 378                 sndr |= AML_SDXC_SEND_CMD_HAS_DATA;
 379                 sndr |= ((data->flags & MMC_DATA_WRITE) != 0) ?
 380                     AML_SDXC_SEND_DATA_WRITE : 0;
 381                 sndr |= (((data->len / block_size) - 1) <<
 382                     AML_SDXC_SEND_REP_PKG_CNT_SHIFT);
 383
 384                 ctlr |= ((block_size < 512) ? block_size : 0) <<
 385                     AML_SDXC_CNTRL_PKG_LEN_SHIFT;
 386
 387                 ier &= ~AML_SDXC_IRQ_ENABLE_RESP_OK;
 388                 ier |= (sc->auto_fill_flush == true ||
 389                     (data->flags & MMC_DATA_WRITE) != 0) ?
 390                     AML_SDXC_IRQ_ENABLE_DMA_DONE :
 391                     AML_SDXC_IRQ_ENABLE_TRANSFER_DONE_OK;
 392
 393                 error = bus_dmamap_load(sc->dmatag, sc->dmamap,
 394                     data->data, data->len, aml8726_sdxc_mapmem, &baddr,
 395                     BUS_DMA_NOWAIT);
 396                 if (error)
 397                         return (MMC_ERR_NO_MEMORY);
 398
 399                 if ((data->flags & MMC_DATA_READ) != 0) {
 400                         bus_dmamap_sync(sc->dmatag, sc->dmamap,
 401                             BUS_DMASYNC_PREREAD);
 402                         timeout = AML_SDXC_READ_TIMEOUT *
 403                             (data->len / block_size);
 404                 } else {
 405                         bus_dmamap_sync(sc->dmatag, sc->dmamap,
 406                             BUS_DMASYNC_PREWRITE);
 407                         timeout = AML_SDXC_WRITE_TIMEOUT *
 408                             (data->len / block_size);
 409                 }
 410         }
 411
 412         sc->cmd = cmd;
 413
 414         cmd->error = MMC_ERR_NONE;
 415
 416         sc->busy.time = 0;
 417         sc->busy.error = MMC_ERR_NONE;
 418
 419         if (timeout > AML_SDXC_MAX_TIMEOUT)
 420                 timeout = AML_SDXC_MAX_TIMEOUT;
 421
 422         callout_reset(&sc->ch, msecs_to_ticks(timeout),
 423             aml8726_sdxc_timeout, sc);
 424
 425         CSR_WRITE_4(sc, AML_SDXC_IRQ_ENABLE_REG, ier);
 426
 427         CSR_WRITE_4(sc, AML_SDXC_CNTRL_REG, ctlr);
 428         CSR_WRITE_4(sc, AML_SDXC_DMA_ADDR_REG, (uint32_t)baddr);
 429         CSR_WRITE_4(sc, AML_SDXC_CMD_ARGUMENT_REG, cmd->arg);
 430
 431         aml8726_sdxc_engage_dma(sc);
 432
 433         CSR_WRITE_4(sc, AML_SDXC_SEND_REG, sndr);
 434         CSR_BARRIER(sc, AML_SDXC_SEND_REG);
 435
 436         return (MMC_ERR_NONE);
 437 }
 438
 439 static void
 440 aml8726_sdxc_finish_command(struct aml8726_sdxc_softc *sc, int mmc_error)
 441 {
 442         int mmc_stop_error;
 443         struct mmc_command *cmd;
 444         struct mmc_command *stop_cmd;
 445         struct mmc_data *data;
 446
 447         AML_SDXC_LOCK_ASSERT(sc);
 448
 449         /* Clear all interrupts since the request is no longer in flight. */
 450         CSR_WRITE_4(sc, AML_SDXC_IRQ_STATUS_REG, AML_SDXC_IRQ_STATUS_CLEAR);
 451         CSR_BARRIER(sc, AML_SDXC_IRQ_STATUS_REG);
 452
 453         /* In some cases (e.g. finish called via timeout) this is a NOP. */
 454         callout_stop(&sc->ch);
 455
 456         cmd = sc->cmd;
 457         sc->cmd = NULL;
 458
 459         cmd->error = mmc_error;
 460
 461         data = cmd->data;
 462
 463         if (data && data->len
 464             && (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) != 0) {
 465                 if ((data->flags & MMC_DATA_READ) != 0)
 466                         bus_dmamap_sync(sc->dmatag, sc->dmamap,
 467                             BUS_DMASYNC_POSTREAD);
 468                 else
 469                         bus_dmamap_sync(sc->dmatag, sc->dmamap,
 470                             BUS_DMASYNC_POSTWRITE);
 471                 bus_dmamap_unload(sc->dmatag, sc->dmamap);
 472         }
 473
 474         /*
 475          * If there's a linked stop command, then start the stop command.
 476          * In order to establish a known state attempt the stop command
 477          * even if the original request encountered an error.
 478          */
 479
 480         stop_cmd = (cmd->mrq->stop != cmd) ? cmd->mrq->stop : NULL;
 481
 482         if (stop_cmd != NULL) {
 483                 /*
 484                  * If the original command executed successfully, then
 485                  * the hardware will also have automatically executed
 486                  * a stop command so don't bother with the one supplied
 487                  * with the original request.
 488                  */
 489
 490                 if (mmc_error == MMC_ERR_NONE) {
 491                         stop_cmd->error = MMC_ERR_NONE;
 492                         stop_cmd->resp[0] = cmd->resp[0];
 493                         stop_cmd->resp[1] = cmd->resp[1];
 494                         stop_cmd->resp[2] = cmd->resp[2];
 495                         stop_cmd->resp[3] = cmd->resp[3];
 496                 } else {
 497                         mmc_stop_error = aml8726_sdxc_start_command(sc,
 498                             stop_cmd);
 499                         if (mmc_stop_error == MMC_ERR_NONE) {
 500                                 AML_SDXC_UNLOCK(sc);
 501                                 return;
 502                         }
 503                         stop_cmd->error = mmc_stop_error;
 504                 }
 505         }
 506
 507         AML_SDXC_UNLOCK(sc);
 508
 509         /* Execute the callback after dropping the lock. */
 510         if (cmd->mrq != NULL)
 511                 cmd->mrq->done(cmd->mrq);
 512 }
 513
 514 static void
 515 aml8726_sdxc_timeout(void *arg)
 516 {
 517         struct aml8726_sdxc_softc *sc = (struct aml8726_sdxc_softc *)arg;
 518
 519         /*
 520          * The command failed to complete in time so forcefully
 521          * terminate it.
 522          */
 523         aml8726_sdxc_soft_reset(sc);
 524
 525         /*
 526          * Ensure the command has terminated before continuing on
 527          * to things such as bus_dmamap_sync / bus_dmamap_unload.
 528          */
 529         while ((CSR_READ_4(sc, AML_SDXC_STATUS_REG) &
 530             AML_SDXC_STATUS_BUSY) != 0)
 531                 cpu_spinwait();
 532
 533         aml8726_sdxc_finish_command(sc, MMC_ERR_TIMEOUT);
 534 }
 535
 536 static void
 537 aml8726_sdxc_busy_check(void *arg)
 538 {
 539         struct aml8726_sdxc_softc *sc = (struct aml8726_sdxc_softc *)arg;
 540         uint32_t sr;
 541
 542         sc->busy.time += AML_SDXC_BUSY_POLL_INTVL;
 543
 544         sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG);
 545
 546         if ((sr & AML_SDXC_STATUS_DAT0) == 0) {
 547                 if (sc->busy.time < AML_SDXC_BUSY_TIMEOUT) {
 548                         callout_reset(&sc->ch,
 549                             msecs_to_ticks(AML_SDXC_BUSY_POLL_INTVL),
 550                             aml8726_sdxc_busy_check, sc);
 551                         AML_SDXC_UNLOCK(sc);
 552                         return;
 553                 }
 554                 if (sc->busy.error == MMC_ERR_NONE)
 555                         sc->busy.error = MMC_ERR_TIMEOUT;
 556         }
 557
 558         aml8726_sdxc_finish_command(sc, sc->busy.error);
 559 }
 560
 561 static void
 562 aml8726_sdxc_intr(void *arg)
 563 {
 564         struct aml8726_sdxc_softc *sc = (struct aml8726_sdxc_softc *)arg;
 565         uint32_t isr;
 566         uint32_t pdmar;
 567         uint32_t sndr;
 568         uint32_t sr;
 569         int i;
 570         int mmc_error;
 571         int start;
 572         int stop;
 573
 574         AML_SDXC_LOCK(sc);
 575
 576         isr = CSR_READ_4(sc, AML_SDXC_IRQ_STATUS_REG);
 577         sndr = CSR_READ_4(sc, AML_SDXC_SEND_REG);
 578         sr = CSR_READ_4(sc, AML_SDXC_STATUS_REG);
 579
 580         if (sc->cmd == NULL)
 581                 goto spurious;
 582
 583         mmc_error = MMC_ERR_NONE;
 584
 585         if ((isr & (AML_SDXC_IRQ_STATUS_TX_FIFO_EMPTY |
 586             AML_SDXC_IRQ_STATUS_RX_FIFO_FULL)) != 0)
 587                 mmc_error = MMC_ERR_FIFO;
 588         else if ((isr & (AML_SDXC_IRQ_ENABLE_A_PKG_CRC_ERR |
 589             AML_SDXC_IRQ_ENABLE_RESP_CRC_ERR)) != 0)
 590                 mmc_error = MMC_ERR_BADCRC;
 591         else if ((isr & (AML_SDXC_IRQ_ENABLE_A_PKG_TIMEOUT_ERR |
 592             AML_SDXC_IRQ_ENABLE_RESP_TIMEOUT_ERR)) != 0)
 593                 mmc_error = MMC_ERR_TIMEOUT;
 594         else if ((isr & (AML_SDXC_IRQ_STATUS_RESP_OK |
 595             AML_SDXC_IRQ_STATUS_DMA_DONE |
 596             AML_SDXC_IRQ_STATUS_TRANSFER_DONE_OK)) != 0) {
 597                 ;
 598         }
 599         else {
 600 spurious:
 601                 /*
 602                  * Clear spurious interrupts while leaving intacted any
 603                  * interrupts that may have occurred after we read the
 604                  * interrupt status register.
 605                  */
 606
 607                 CSR_WRITE_4(sc, AML_SDXC_IRQ_STATUS_REG,
 608                     (AML_SDXC_IRQ_STATUS_CLEAR & isr));
 609                 CSR_BARRIER(sc, AML_SDXC_IRQ_STATUS_REG);
 610                 AML_SDXC_UNLOCK(sc);
 611                 return;
 612         }
 613
 614         aml8726_sdxc_disengage_dma(sc);
 615
 616         if ((sndr & AML_SDXC_SEND_CMD_HAS_RESP) != 0) {
 617                 start = 0;
 618                 stop = 1;
 619                 if ((sndr & AML_SDXC_SEND_RESP_136) != 0) {
 620                         start = 1;
 621                         stop = start + 4;
 622                 }
 623                 for (i = start; i < stop; i++) {
 624                         pdmar = CSR_READ_4(sc, AML_SDXC_PDMA_REG);
 625                         pdmar &= ~(AML_SDXC_PDMA_DMA_EN |
 626                             AML_SDXC_PDMA_RESP_INDEX_MASK);
 627                         pdmar |= i << AML_SDXC_PDMA_RESP_INDEX_SHIFT;
 628                         CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
 629                         sc->cmd->resp[(stop - 1) - i] = CSR_READ_4(sc,
 630                             AML_SDXC_CMD_ARGUMENT_REG);
 631                 }
 632         }
 633
 634         if ((sr & AML_SDXC_STATUS_BUSY) != 0 &&
 635             /*
 636              * A multiblock operation may keep the hardware
 637              * busy until stop transmission is executed.
 638              */
 639             (isr & (AML_SDXC_IRQ_STATUS_DMA_DONE |
 640             AML_SDXC_IRQ_STATUS_TRANSFER_DONE_OK)) == 0) {
 641                 if (mmc_error == MMC_ERR_NONE)
 642                         mmc_error = MMC_ERR_FAILED;
 643
 644                 /*
 645                  * Issue a soft reset to terminate the command.
 646                  *
 647                  * Ensure the command has terminated before continuing on
 648                  * to things such as bus_dmamap_sync / bus_dmamap_unload.
 649                  */
 650
 651                 aml8726_sdxc_soft_reset(sc);
 652
 653                 while ((CSR_READ_4(sc, AML_SDXC_STATUS_REG) &
 654                     AML_SDXC_STATUS_BUSY) != 0)
 655                         cpu_spinwait();
 656         }
 657
 658         /*
 659          * The stop command can be generated either manually or
 660          * automatically by the hardware if MISC_MANUAL_STOP_MODE
 661          * has not been set.  In either case check for busy.
 662          */
 663
 664         if (((sc->cmd->flags & MMC_RSP_BUSY) != 0 ||
 665             (sndr & AML_SDXC_SEND_INDEX_MASK) == MMC_STOP_TRANSMISSION) &&
 666             (sr & AML_SDXC_STATUS_DAT0) == 0) {
 667                 sc->busy.error = mmc_error;
 668                 callout_reset(&sc->ch,
 669                     msecs_to_ticks(AML_SDXC_BUSY_POLL_INTVL),
 670                     aml8726_sdxc_busy_check, sc);
 671                 CSR_WRITE_4(sc, AML_SDXC_IRQ_STATUS_REG,
 672                     (AML_SDXC_IRQ_STATUS_CLEAR & isr));
 673                 CSR_BARRIER(sc, AML_SDXC_IRQ_STATUS_REG);
 674                 AML_SDXC_UNLOCK(sc);
 675                 return;
 676         }
 677
 678         aml8726_sdxc_finish_command(sc, mmc_error);
 679 }
 680
 681 static int
 682 aml8726_sdxc_probe(device_t dev)
 683 {
 684
 685         if (!ofw_bus_status_okay(dev))
 686                 return (ENXIO);
 687
 688         if (!ofw_bus_is_compatible(dev, "amlogic,aml8726-sdxc-m8"))
 689                 return (ENXIO);
 690
 691         device_set_desc(dev, "Amlogic aml8726-m8 SDXC");
 692
 693         return (BUS_PROBE_DEFAULT);
 694 }
 695
 696 static int
 697 aml8726_sdxc_attach(device_t dev)
 698 {
 699         struct aml8726_sdxc_softc *sc = device_get_softc(dev);
 700         char *voltages;
 701         char *voltage;
 702         int error;
 703         int nvoltages;
 704         pcell_t prop[3];
 705         phandle_t node;
 706         ssize_t len;
 707         device_t child;
 708         uint32_t ectlr;
 709         uint32_t miscr;
 710         uint32_t pdmar;
 711
 712         sc->dev = dev;
 713
 714         sc->auto_fill_flush = false;
 715
 716         pdmar = AML_SDXC_PDMA_DMA_URGENT |
 717             (49 << AML_SDXC_PDMA_TX_THOLD_SHIFT) |
 718             (7 << AML_SDXC_PDMA_RX_THOLD_SHIFT) |
 719             (15 << AML_SDXC_PDMA_RD_BURST_SHIFT) |
 720             (7 << AML_SDXC_PDMA_WR_BURST_SHIFT);
 721
 722         miscr = (2 << AML_SDXC_MISC_WCRC_OK_PAT_SHIFT) |
 723             (5 << AML_SDXC_MISC_WCRC_ERR_PAT_SHIFT);
 724
 725         ectlr = (12 << AML_SDXC_ENH_CNTRL_SDIO_IRQ_PERIOD_SHIFT);
 726
 727         /*
 728          * Certain bitfields are dependent on the hardware revision.
 729          */
 730         switch (aml8726_soc_hw_rev) {
 731         case AML_SOC_HW_REV_M8:
 732                 switch (aml8726_soc_metal_rev) {
 733                 case AML_SOC_M8_METAL_REV_M2_A:
 734                         sc->auto_fill_flush = true;
 735                         miscr |= (6 << AML_SDXC_MISC_TXSTART_THOLD_SHIFT);
 736                         ectlr |= (64 << AML_SDXC_ENH_CNTRL_RX_FULL_THOLD_SHIFT) |
 737                             AML_SDXC_ENH_CNTRL_WR_RESP_MODE_SKIP_M8M2;
 738                         break;
 739                 default:
 740                         miscr |= (7 << AML_SDXC_MISC_TXSTART_THOLD_SHIFT);
 741                         ectlr |= (63 << AML_SDXC_ENH_CNTRL_RX_FULL_THOLD_SHIFT) |
 742                             AML_SDXC_ENH_CNTRL_DMA_NO_WR_RESP_CHECK_M8 |
 743                             (255 << AML_SDXC_ENH_CNTRL_RX_TIMEOUT_SHIFT_M8);
 744
 745                         break;
 746                 }
 747                 break;
 748         case AML_SOC_HW_REV_M8B:
 749                 miscr |= (7 << AML_SDXC_MISC_TXSTART_THOLD_SHIFT);
 750                 ectlr |= (63 << AML_SDXC_ENH_CNTRL_RX_FULL_THOLD_SHIFT) |
 751                     AML_SDXC_ENH_CNTRL_DMA_NO_WR_RESP_CHECK_M8 |
 752                     (255 << AML_SDXC_ENH_CNTRL_RX_TIMEOUT_SHIFT_M8);
 753                 break;
 754         default:
 755                 device_printf(dev, "unsupported SoC\n");
 756                 return (ENXIO);
 757                 /* NOTREACHED */
 758         }
 759
 760         node = ofw_bus_get_node(dev);
 761
 762         len = OF_getencprop(node, "clock-frequency", prop, sizeof(prop));
 763         if ((len / sizeof(prop[0])) != 1 || prop[0] == 0) {
 764                 device_printf(dev,
 765                     "missing clock-frequency attribute in FDT\n");
 766                 return (ENXIO);
 767         }
 768
 769         sc->ref_freq = prop[0];
 770
 771         sc->pwr_en.dev = NULL;
 772
 773         len = OF_getencprop(node, "mmc-pwr-en", prop, sizeof(prop));
 774         if (len > 0) {
 775                 if ((len / sizeof(prop[0])) == 3) {
 776                         sc->pwr_en.dev = OF_device_from_xref(prop[0]);
 777                         sc->pwr_en.pin = prop[1];
 778                         sc->pwr_en.pol = prop[2];
 779                 }
 780
 781                 if (sc->pwr_en.dev == NULL) {
 782                         device_printf(dev,
 783                             "unable to process mmc-pwr-en attribute in FDT\n");
 784                         return (ENXIO);
 785                 }
 786
 787                 /* Turn off power and then configure the output driver. */
 788                 if (aml8726_sdxc_power_off(sc) != 0 ||
 789                     GPIO_PIN_SETFLAGS(sc->pwr_en.dev, sc->pwr_en.pin,
 790                     GPIO_PIN_OUTPUT) != 0) {
 791                         device_printf(dev,
 792                             "could not use gpio to control power\n");
 793                         return (ENXIO);
 794                 }
 795         }
 796
 797         len = OF_getprop_alloc(node, "mmc-voltages",
 798             (void **)&voltages);
 799
 800         if (len < 0) {
 801                 device_printf(dev, "missing mmc-voltages attribute in FDT\n");
 802                 return (ENXIO);
 803         }
 804
 805         sc->voltages[0] = 0;
 806         sc->voltages[1] = 0;
 807
 808         voltage = voltages;
 809         nvoltages = 0;
 810
 811         while (len && nvoltages < 2) {
 812                 if (strncmp("1.8", voltage, len) == 0)
 813                         sc->voltages[nvoltages] = MMC_OCR_LOW_VOLTAGE;
 814                 else if (strncmp("3.3", voltage, len) == 0)
 815                         sc->voltages[nvoltages] = MMC_OCR_320_330 |
 816                             MMC_OCR_330_340;
 817                 else {
 818                         device_printf(dev,
 819                             "unknown voltage attribute %.*s in FDT\n",
 820                             len, voltage);
 821                         OF_prop_free(voltages);
 822                         return (ENXIO);
 823                 }
 824
 825                 nvoltages++;
 826
 827                 /* queue up next string */
 828                 while (*voltage && len) {
 829                         voltage++;
 830                         len--;
 831                 }
 832                 if (len) {
 833                         voltage++;
 834                         len--;
 835                 }
 836         }
 837
 838         OF_prop_free(voltages);
 839
 840         sc->vselect.dev = NULL;
 841
 842         len = OF_getencprop(node, "mmc-vselect", prop, sizeof(prop));
 843         if (len > 0) {
 844                 if ((len / sizeof(prop[0])) == 2) {
 845                         sc->vselect.dev = OF_device_from_xref(prop[0]);
 846                         sc->vselect.pin = prop[1];
 847                         sc->vselect.pol = 1;
 848                 }
 849
 850                 if (sc->vselect.dev == NULL) {
 851                         device_printf(dev,
 852                             "unable to process mmc-vselect attribute in FDT\n");
 853                         return (ENXIO);
 854                 }
 855
 856                 /*
 857                  * With the power off select voltage 0 and then
 858                  * configure the output driver.
 859                  */
 860                 if (GPIO_PIN_SET(sc->vselect.dev, sc->vselect.pin, 0) != 0 ||
 861                     GPIO_PIN_SETFLAGS(sc->vselect.dev, sc->vselect.pin,
 862                     GPIO_PIN_OUTPUT) != 0) {
 863                         device_printf(dev,
 864                             "could not use gpio to set voltage\n");
 865                         return (ENXIO);
 866                 }
 867         }
 868
 869         if (nvoltages == 0) {
 870                 device_printf(dev, "no voltages in FDT\n");
 871                 return (ENXIO);
 872         } else if (nvoltages == 1 && sc->vselect.dev != NULL) {
 873                 device_printf(dev, "only one voltage in FDT\n");
 874                 return (ENXIO);
 875         } else if (nvoltages == 2 && sc->vselect.dev == NULL) {
 876                 device_printf(dev, "too many voltages in FDT\n");
 877                 return (ENXIO);
 878         }
 879
 880         sc->card_rst.dev = NULL;
 881
 882         len = OF_getencprop(node, "mmc-rst", prop, sizeof(prop));
 883         if (len > 0) {
 884                 if ((len / sizeof(prop[0])) == 3) {
 885                         sc->card_rst.dev = OF_device_from_xref(prop[0]);
 886                         sc->card_rst.pin = prop[1];
 887                         sc->card_rst.pol = prop[2];
 888                 }
 889
 890                 if (sc->card_rst.dev == NULL) {
 891                         device_printf(dev,
 892                             "unable to process mmc-rst attribute in FDT\n");
 893                         return (ENXIO);
 894                 }
 895         }
 896
 897         if (bus_alloc_resources(dev, aml8726_sdxc_spec, sc->res)) {
 898                 device_printf(dev, "could not allocate resources for device\n");
 899                 return (ENXIO);
 900         }
 901
 902         AML_SDXC_LOCK_INIT(sc);
 903
 904         error = bus_dma_tag_create(bus_get_dma_tag(dev), AML_SDXC_ALIGN_DMA, 0,
 905             BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
 906             AML_SDXC_MAX_DMA, 1, AML_SDXC_MAX_DMA, 0, NULL, NULL, &sc->dmatag);
 907         if (error)
 908                 goto fail;
 909
 910         error = bus_dmamap_create(sc->dmatag, 0, &sc->dmamap);
 911
 912         if (error)
 913                 goto fail;
 914
 915         error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE,
 916             NULL, aml8726_sdxc_intr, sc, &sc->ih_cookie);
 917         if (error) {
 918                 device_printf(dev, "could not setup interrupt handler\n");
 919                 goto fail;
 920         }
 921
 922         callout_init_mtx(&sc->ch, &sc->mtx, CALLOUT_RETURNUNLOCKED);
 923
 924         sc->host.f_min = 200000;
 925         sc->host.f_max = 100000000;
 926         sc->host.host_ocr = sc->voltages[0] | sc->voltages[1];
 927         sc->host.caps = MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
 928             MMC_CAP_HSPEED;
 929
 930         aml8726_sdxc_soft_reset(sc);
 931
 932         CSR_WRITE_4(sc, AML_SDXC_PDMA_REG, pdmar);
 933
 934         CSR_WRITE_4(sc, AML_SDXC_MISC_REG, miscr);
 935
 936         CSR_WRITE_4(sc, AML_SDXC_ENH_CNTRL_REG, ectlr);
 937
 938         child = device_add_child(dev, "mmc", -1);
 939
 940         if (!child) {
 941                 device_printf(dev, "could not add mmc\n");
 942                 error = ENXIO;
 943                 goto fail;
 944         }
 945
 946         error = device_probe_and_attach(child);
 947
 948         if (error) {
 949                 device_printf(dev, "could not attach mmc\n");
 950                 goto fail;
 951         }
 952
 953         return (0);
 954
 955 fail:
 956         if (sc->ih_cookie)
 957                 bus_teardown_intr(dev, sc->res[1], sc->ih_cookie);
 958
 959         if (sc->dmamap)
 960                 bus_dmamap_destroy(sc->dmatag, sc->dmamap);
 961
 962         if (sc->dmatag)
 963                 bus_dma_tag_destroy(sc->dmatag);
 964
 965         AML_SDXC_LOCK_DESTROY(sc);
 966
 967         (void)aml8726_sdxc_power_off(sc);
 968
 969         bus_release_resources(dev, aml8726_sdxc_spec, sc->res);
 970
 971         return (error);
 972 }
 973
 974 static int
 975 aml8726_sdxc_detach(device_t dev)
 976 {
 977         struct aml8726_sdxc_softc *sc = device_get_softc(dev);
 978
 979         AML_SDXC_LOCK(sc);
 980
 981         if (sc->cmd != NULL) {
 982                 AML_SDXC_UNLOCK(sc);
 983                 return (EBUSY);
 984         }
 985
 986         /*
 987          * Turn off the power, reset the hardware state machine,
 988          * and disable the interrupts.
 989          */
 990         aml8726_sdxc_power_off(sc);
 991         aml8726_sdxc_soft_reset(sc);
 992         CSR_WRITE_4(sc, AML_SDXC_IRQ_ENABLE_REG, 0);
 993
 994         AML_SDXC_UNLOCK(sc);
 995
 996         bus_generic_detach(dev);
 997
 998         bus_teardown_intr(dev, sc->res[1], sc->ih_cookie);
 999
1000         bus_dmamap_destroy(sc->dmatag, sc->dmamap);
1001
1002         bus_dma_tag_destroy(sc->dmatag);
1003
1004         AML_SDXC_LOCK_DESTROY(sc);
1005
1006         bus_release_resources(dev, aml8726_sdxc_spec, sc->res);
1007
1008         return (0);
1009 }
1010
1011 static int
1012 aml8726_sdxc_shutdown(device_t dev)
1013 {
1014         struct aml8726_sdxc_softc *sc = device_get_softc(dev);
1015
1016         /*
1017          * Turn off the power, reset the hardware state machine,
1018          * and disable the interrupts.
1019          */
1020         aml8726_sdxc_power_off(sc);
1021         aml8726_sdxc_soft_reset(sc);
1022         CSR_WRITE_4(sc, AML_SDXC_IRQ_ENABLE_REG, 0);
1023
1024         return (0);
1025 }
1026
1027 static int
1028 aml8726_sdxc_update_ios(device_t bus, device_t child)
1029 {
1030         struct aml8726_sdxc_softc *sc = device_get_softc(bus);
1031         struct mmc_ios *ios = &sc->host.ios;
1032         unsigned int divisor;
1033         int error;
1034         int i;
1035         uint32_t cctlr;
1036         uint32_t clk2r;
1037         uint32_t ctlr;
1038         uint32_t freq;
1039
1040         ctlr = (7 << AML_SDXC_CNTRL_TX_ENDIAN_SHIFT) |
1041             (7 << AML_SDXC_CNTRL_RX_ENDIAN_SHIFT) |
1042             (0xf << AML_SDXC_CNTRL_RX_PERIOD_SHIFT) |
1043             (0x7f << AML_SDXC_CNTRL_RX_TIMEOUT_SHIFT);
1044
1045         switch (ios->bus_width) {
1046         case bus_width_8:
1047                 ctlr |= AML_SDXC_CNTRL_BUS_WIDTH_8;
1048                 break;
1049         case bus_width_4:
1050                 ctlr |= AML_SDXC_CNTRL_BUS_WIDTH_4;
1051                 break;
1052         case bus_width_1:
1053                 ctlr |= AML_SDXC_CNTRL_BUS_WIDTH_1;
1054                 break;
1055         default:
1056                 return (EINVAL);
1057         }
1058
1059         CSR_WRITE_4(sc, AML_SDXC_CNTRL_REG, ctlr);
1060
1061         /*
1062          * Disable clocks and then clock module prior to setting desired values.
1063          */
1064         cctlr = CSR_READ_4(sc, AML_SDXC_CLK_CNTRL_REG);
1065         cctlr &= ~(AML_SDXC_CLK_CNTRL_TX_CLK_EN | AML_SDXC_CLK_CNTRL_RX_CLK_EN |
1066             AML_SDXC_CLK_CNTRL_SD_CLK_EN);
1067         CSR_WRITE_4(sc, AML_SDXC_CLK_CNTRL_REG, cctlr);
1068         CSR_BARRIER(sc, AML_SDXC_CLK_CNTRL_REG);
1069         cctlr &= ~AML_SDXC_CLK_CNTRL_CLK_MODULE_EN;
1070         CSR_WRITE_4(sc, AML_SDXC_CLK_CNTRL_REG, cctlr);
1071         CSR_BARRIER(sc, AML_SDXC_CLK_CNTRL_REG);
1072
1073         /*
1074          *                  aml8726-m8
1075          *
1076          * Clock select 1   fclk_div2 (1.275 GHz)
1077          */
1078         cctlr &= ~AML_SDXC_CLK_CNTRL_CLK_SEL_MASK;
1079         cctlr |= (1 << AML_SDXC_CLK_CNTRL_CLK_SEL_SHIFT);
1080
1081         divisor = sc->ref_freq / ios->clock - 1;
1082         if (divisor == 0 || divisor == -1)
1083                 divisor = 1;
1084         if ((sc->ref_freq / (divisor + 1)) > ios->clock)
1085                 divisor += 1;
1086         if (divisor > (AML_SDXC_CLK_CNTRL_CLK_DIV_MASK >>
1087             AML_SDXC_CLK_CNTRL_CLK_DIV_SHIFT))
1088                 divisor = AML_SDXC_CLK_CNTRL_CLK_DIV_MASK >>
1089                     AML_SDXC_CLK_CNTRL_CLK_DIV_SHIFT;
1090
1091         cctlr &= ~AML_SDXC_CLK_CNTRL_CLK_DIV_MASK;
1092         cctlr |= divisor << AML_SDXC_CLK_CNTRL_CLK_DIV_SHIFT;
1093
1094         cctlr &= ~AML_SDXC_CLK_CNTRL_MEM_PWR_MASK;
1095         cctlr |= AML_SDXC_CLK_CNTRL_MEM_PWR_ON;
1096
1097         CSR_WRITE_4(sc, AML_SDXC_CLK_CNTRL_REG, cctlr);
1098         CSR_BARRIER(sc, AML_SDXC_CLK_CNTRL_REG);
1099
1100         /*
1101          * Enable clock module and then clocks after setting desired values.
1102          */
1103         cctlr |= AML_SDXC_CLK_CNTRL_CLK_MODULE_EN;
1104         CSR_WRITE_4(sc, AML_SDXC_CLK_CNTRL_REG, cctlr);
1105         CSR_BARRIER(sc, AML_SDXC_CLK_CNTRL_REG);
1106         cctlr |= AML_SDXC_CLK_CNTRL_TX_CLK_EN | AML_SDXC_CLK_CNTRL_RX_CLK_EN |
1107             AML_SDXC_CLK_CNTRL_SD_CLK_EN;
1108         CSR_WRITE_4(sc, AML_SDXC_CLK_CNTRL_REG, cctlr);
1109         CSR_BARRIER(sc, AML_SDXC_CLK_CNTRL_REG);
1110
1111         freq = sc->ref_freq / divisor;
1112
1113         for (i = 0; aml8726_sdxc_clk_phases[i].voltage; i++) {
1114                 if ((aml8726_sdxc_clk_phases[i].voltage &
1115                     (1 << ios->vdd)) != 0 &&
1116                     freq > aml8726_sdxc_clk_phases[i].freq)
1117                         break;
1118                 if (aml8726_sdxc_clk_phases[i].freq == 0)
1119                         break;
1120         }
1121
1122         clk2r = (1 << AML_SDXC_CLK2_SD_PHASE_SHIFT) |
1123             (aml8726_sdxc_clk_phases[i].rx_phase <<
1124             AML_SDXC_CLK2_RX_PHASE_SHIFT);
1125         CSR_WRITE_4(sc, AML_SDXC_CLK2_REG, clk2r);
1126         CSR_BARRIER(sc, AML_SDXC_CLK2_REG);
1127
1128         error = 0;
1129
1130         switch (ios->power_mode) {
1131         case power_up:
1132                 /*
1133                  * Configure and power on the regulator so that the
1134                  * voltage stabilizes prior to powering on the card.
1135                  */
1136                 if (sc->vselect.dev != NULL) {
1137                         for (i = 0; i < 2; i++)
1138                                 if ((sc->voltages[i] & (1 << ios->vdd)) != 0)
1139                                         break;
1140                         if (i >= 2)
1141                                 return (EINVAL);
1142                         error = GPIO_PIN_SET(sc->vselect.dev,
1143                             sc->vselect.pin, i);
1144                 }
1145                 break;
1146         case power_on:
1147                 error = aml8726_sdxc_power_on(sc);
1148                 if (error)
1149                         break;
1150
1151                 if (sc->card_rst.dev != NULL) {
1152                         if (GPIO_PIN_SET(sc->card_rst.dev, sc->card_rst.pin,
1153                             PIN_ON_FLAG(sc->card_rst.pol)) != 0 ||
1154                             GPIO_PIN_SETFLAGS(sc->card_rst.dev,
1155                             sc->card_rst.pin,
1156                             GPIO_PIN_OUTPUT) != 0)
1157                                 error = ENXIO;
1158
1159                         DELAY(5);
1160
1161                         if (GPIO_PIN_SET(sc->card_rst.dev, sc->card_rst.pin,
1162                             PIN_OFF_FLAG(sc->card_rst.pol)) != 0)
1163                                 error = ENXIO;
1164
1165                         DELAY(5);
1166
1167                         if (error) {
1168                                 device_printf(sc->dev,
1169                                     "could not use gpio to reset card\n");
1170                                 break;
1171                         }
1172                 }
1173                 break;
1174         case power_off:
1175                 error = aml8726_sdxc_power_off(sc);
1176                 break;
1177         default:
1178                 return (EINVAL);
1179         }
1180
1181         return (error);
1182 }
1183
1184 static int
1185 aml8726_sdxc_request(device_t bus, device_t child, struct mmc_request *req)
1186 {
1187         struct aml8726_sdxc_softc *sc = device_get_softc(bus);
1188         int mmc_error;
1189
1190         AML_SDXC_LOCK(sc);
1191
1192         if (sc->cmd != NULL) {
1193                 AML_SDXC_UNLOCK(sc);
1194                 return (EBUSY);
1195         }
1196
1197         mmc_error = aml8726_sdxc_start_command(sc, req->cmd);
1198
1199         AML_SDXC_UNLOCK(sc);
1200
1201         /* Execute the callback after dropping the lock. */
1202         if (mmc_error != MMC_ERR_NONE) {
1203                 req->cmd->error = mmc_error;
1204                 req->done(req);
1205         }
1206
1207         return (0);
1208 }
1209
1210 static int
1211 aml8726_sdxc_read_ivar(device_t bus, device_t child,
1212     int which, uintptr_t *result)
1213 {
1214         struct aml8726_sdxc_softc *sc = device_get_softc(bus);
1215
1216         switch (which) {
1217         case MMCBR_IVAR_BUS_MODE:
1218                 *(int *)result = sc->host.ios.bus_mode;
1219                 break;
1220         case MMCBR_IVAR_BUS_WIDTH:
1221                 *(int *)result = sc->host.ios.bus_width;
1222                 break;
1223         case MMCBR_IVAR_CHIP_SELECT:
1224                 *(int *)result = sc->host.ios.chip_select;
1225                 break;
1226         case MMCBR_IVAR_CLOCK:
1227                 *(int *)result = sc->host.ios.clock;
1228                 break;
1229         case MMCBR_IVAR_F_MIN:
1230                 *(int *)result = sc->host.f_min;
1231                 break;
1232         case MMCBR_IVAR_F_MAX:
1233                 *(int *)result = sc->host.f_max;
1234                 break;
1235         case MMCBR_IVAR_HOST_OCR:
1236                 *(int *)result = sc->host.host_ocr;
1237                 break;
1238         case MMCBR_IVAR_MODE:
1239                 *(int *)result = sc->host.mode;
1240                 break;
1241         case MMCBR_IVAR_OCR:
1242                 *(int *)result = sc->host.ocr;
1243                 break;
1244         case MMCBR_IVAR_POWER_MODE:
1245                 *(int *)result = sc->host.ios.power_mode;
1246                 break;
1247         case MMCBR_IVAR_RETUNE_REQ:
1248                 *(int *)result = return_req_none;
1249                 break;
1250         case MMCBR_IVAR_VDD:
1251                 *(int *)result = sc->host.ios.vdd;
1252                 break;
1253         case MMCBR_IVAR_VCCQ:
1254                 *result = sc->host.ios.vccq;
1255                 break;
1256         case MMCBR_IVAR_CAPS:
1257                 *(int *)result = sc->host.caps;
1258                 break;
1259         case MMCBR_IVAR_TIMING:
1260                 *(int *)result = sc->host.ios.timing;
1261                 break;
1262         case MMCBR_IVAR_MAX_DATA:
1263                 *(int *)result = AML_SDXC_MAX_DMA / MMC_SECTOR_SIZE;
1264                 break;
1265         case MMCBR_IVAR_MAX_BUSY_TIMEOUT:
1266                 *(int *)result = 1000000;       /* 1s max */
1267                 break;
1268         default:
1269                 return (EINVAL);
1270         }
1271
1272         return (0);
1273 }
1274
1275 static int
1276 aml8726_sdxc_write_ivar(device_t bus, device_t child,
1277     int which, uintptr_t value)
1278 {
1279         struct aml8726_sdxc_softc *sc = device_get_softc(bus);
1280
1281         switch (which) {
1282         case MMCBR_IVAR_BUS_MODE:
1283                 sc->host.ios.bus_mode = value;
1284                 break;
1285         case MMCBR_IVAR_BUS_WIDTH:
1286                 sc->host.ios.bus_width = value;
1287                 break;
1288         case MMCBR_IVAR_CHIP_SELECT:
1289                 sc->host.ios.chip_select = value;
1290                 break;
1291         case MMCBR_IVAR_CLOCK:
1292                 sc->host.ios.clock = value;
1293                 break;
1294         case MMCBR_IVAR_MODE:
1295                 sc->host.mode = value;
1296                 break;
1297         case MMCBR_IVAR_OCR:
1298                 sc->host.ocr = value;
1299                 break;
1300         case MMCBR_IVAR_POWER_MODE:
1301                 sc->host.ios.power_mode = value;
1302                 break;
1303         case MMCBR_IVAR_VDD:
1304                 sc->host.ios.vdd = value;
1305                 break;
1306         case MMCBR_IVAR_VCCQ:
1307                 sc->host.ios.vccq = value;
1308                 break;
1309         case MMCBR_IVAR_TIMING:
1310                 sc->host.ios.timing = value;
1311                 break;
1312         /* These are read-only */
1313         case MMCBR_IVAR_CAPS:
1314         case MMCBR_IVAR_HOST_OCR:
1315         case MMCBR_IVAR_F_MIN:
1316         case MMCBR_IVAR_F_MAX:
1317         case MMCBR_IVAR_MAX_DATA:
1318         default:
1319                 return (EINVAL);
1320         }
1321
1322         return (0);
1323 }
1324
1325 static int
1326 aml8726_sdxc_get_ro(device_t bus, device_t child)
1327 {
1328
1329         return (0);
1330 }
1331
1332 static int
1333 aml8726_sdxc_acquire_host(device_t bus, device_t child)
1334 {
1335         struct aml8726_sdxc_softc *sc = device_get_softc(bus);
1336
1337         AML_SDXC_LOCK(sc);
1338
1339         while (sc->bus_busy)
1340                 mtx_sleep(sc, &sc->mtx, PZERO, "sdxc", hz / 5);
1341         sc->bus_busy++;
1342
1343         AML_SDXC_UNLOCK(sc);
1344
1345         return (0);
1346 }
1347
1348 static int
1349 aml8726_sdxc_release_host(device_t bus, device_t child)
1350 {
1351         struct aml8726_sdxc_softc *sc = device_get_softc(bus);
1352
1353         AML_SDXC_LOCK(sc);
1354
1355         sc->bus_busy--;
1356         wakeup(sc);
1357
1358         AML_SDXC_UNLOCK(sc);
1359
1360         return (0);
1361 }
1362
1363 static device_method_t aml8726_sdxc_methods[] = {
1364         /* Device interface */
1365         DEVMETHOD(device_probe,         aml8726_sdxc_probe),
1366         DEVMETHOD(device_attach,        aml8726_sdxc_attach),
1367         DEVMETHOD(device_detach,        aml8726_sdxc_detach),
1368         DEVMETHOD(device_shutdown,      aml8726_sdxc_shutdown),
1369
1370         /* Bus interface */
1371         DEVMETHOD(bus_read_ivar,        aml8726_sdxc_read_ivar),
1372         DEVMETHOD(bus_write_ivar,       aml8726_sdxc_write_ivar),
1373
1374         /* MMC bridge interface */
1375         DEVMETHOD(mmcbr_update_ios,     aml8726_sdxc_update_ios),
1376         DEVMETHOD(mmcbr_request,        aml8726_sdxc_request),
1377         DEVMETHOD(mmcbr_get_ro,         aml8726_sdxc_get_ro),
1378         DEVMETHOD(mmcbr_acquire_host,   aml8726_sdxc_acquire_host),
1379         DEVMETHOD(mmcbr_release_host,   aml8726_sdxc_release_host),
1380
1381         DEVMETHOD_END
1382 };
1383
1384 static driver_t aml8726_sdxc_driver = {
1385         "aml8726_sdxc",
1386         aml8726_sdxc_methods,
1387         sizeof(struct aml8726_sdxc_softc),
1388 };
1389
1390 static devclass_t aml8726_sdxc_devclass;
1391
1392 DRIVER_MODULE(aml8726_sdxc, simplebus, aml8726_sdxc_driver,
1393     aml8726_sdxc_devclass, NULL, NULL);
1394 MODULE_DEPEND(aml8726_sdxc, aml8726_gpio, 1, 1, 1);
1395 MMC_DECLARE_BRIDGE(aml8726_sdxc);