2 * Copyright 2015 John Wehle <john@feith.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef _ARM_AMLOGIC_AML8726_SDXC_M8_H
30 #define _ARM_AMLOGIC_AML8726_SDXC_M8_H
32 #define AML_SDXC_ALIGN_DMA 4
33 #define AML_SDXC_MAX_DMA 4096
36 * Timeouts are in milliseconds
38 * Read and write are per section 4.6.2 of the:
40 * SD Specifications Part 1
41 * Physical Layer Simplified Specification
44 #define AML_SDXC_CMD_TIMEOUT 50
45 #define AML_SDXC_READ_TIMEOUT 100
46 #define AML_SDXC_WRITE_TIMEOUT 500
47 #define AML_SDXC_MAX_TIMEOUT 5000
49 #define AML_SDXC_BUSY_POLL_INTVL 1
50 #define AML_SDXC_BUSY_TIMEOUT 1000
53 * There's some disagreements between the S805 documentation
54 * and the Amlogic Linux platform code regarding the exact
55 * layout of various registers ... when in doubt we follow
59 #define AML_SDXC_CMD_ARGUMENT_REG 0
61 #define AML_SDXC_SEND_REG 4
62 #define AML_SDXC_SEND_REP_PKG_CNT_MASK (0xffffU << 16)
63 #define AML_SDXC_SEND_REP_PKG_CNT_SHIFT 16
64 #define AML_SDXC_SEND_DATA_STOP (1 << 11)
65 #define AML_SDXC_SEND_DATA_WRITE (1 << 10)
66 #define AML_SDXC_SEND_RESP_NO_CRC7_CHECK (1 << 9)
67 #define AML_SDXC_SEND_RESP_136 (1 << 8)
68 #define AML_SDXC_SEND_CMD_HAS_DATA (1 << 7)
69 #define AML_SDXC_SEND_CMD_HAS_RESP (1 << 6)
70 #define AML_SDXC_SEND_INDEX_MASK 0x3f
71 #define AML_SDXC_SEND_INDEX_SHIFT 0
73 #define AML_SDXC_CNTRL_REG 8
74 #define AML_SDXC_CNTRL_TX_ENDIAN_MASK (7 << 29)
75 #define AML_SDXC_CNTRL_TX_ENDIAN_SHIFT 29
76 #define AML_SDXC_CNTRL_RX_ENDIAN_MASK (7 << 24)
77 #define AML_SDXC_CNTRL_RX_ENDIAN_SHIFT 24
78 #define AML_SDXC_CNTRL_RX_PERIOD_SHIFT 20
79 #define AML_SDXC_CNTRL_RX_TIMEOUT_SHIFT 13
80 #define AML_SDXC_CNTRL_PKG_LEN_MASK (0x1ff << 4)
81 #define AML_SDXC_CNTRL_PKG_LEN_SHIFT 4
82 #define AML_SDXC_CNTRL_BUS_WIDTH_MASK (3 << 0)
83 #define AML_SDXC_CNTRL_BUS_WIDTH_1 (0 << 0)
84 #define AML_SDXC_CNTRL_BUS_WIDTH_4 (1 << 0)
85 #define AML_SDXC_CNTRL_BUS_WIDTH_8 (2 << 0)
87 #define AML_SDXC_STATUS_REG 12
88 #define AML_SDXC_STATUS_TX_CNT_MASK (0x7f << 13)
89 #define AML_SDXC_STATUS_TX_CNT_SHIFT 13
90 #define AML_SDXC_STATUS_RX_CNT_MASK (0x7f << 6)
91 #define AML_SDXC_STATUS_RX_CNT_SHIFT 6
92 #define AML_SDXC_STATUS_CMD (1 << 5)
93 #define AML_SDXC_STATUS_DAT3 (1 << 4)
94 #define AML_SDXC_STATUS_DAT2 (1 << 3)
95 #define AML_SDXC_STATUS_DAT1 (1 << 2)
96 #define AML_SDXC_STATUS_DAT0 (1 << 1)
97 #define AML_SDXC_STATUS_BUSY (1 << 0)
99 #define AML_SDXC_CLK_CNTRL_REG 16
100 #define AML_SDXC_CLK_CNTRL_MEM_PWR_MASK (3 << 25)
101 #define AML_SDXC_CLK_CNTRL_MEM_PWR_OFF (3 << 25)
102 #define AML_SDXC_CLK_CNTRL_MEM_PWR_ON (0 << 25)
103 #define AML_SDXC_CLK_CNTRL_CLK_SEL_MASK (3 << 16)
104 #define AML_SDXC_CLK_CNTRL_CLK_SEL_SHIFT 16
105 #define AML_SDXC_CLK_CNTRL_CLK_MODULE_EN (1 << 15)
106 #define AML_SDXC_CLK_CNTRL_SD_CLK_EN (1 << 14)
107 #define AML_SDXC_CLK_CNTRL_RX_CLK_EN (1 << 13)
108 #define AML_SDXC_CLK_CNTRL_TX_CLK_EN (1 << 12)
109 #define AML_SDXC_CLK_CNTRL_CLK_DIV_MASK 0x0fff
110 #define AML_SDXC_CLK_CNTRL_CLK_DIV_SHIFT 0
112 #define AML_SDXC_DMA_ADDR_REG 20
114 #define AML_SDXC_PDMA_REG 24
115 #define AML_SDXC_PDMA_TX_FILL (1U << 31)
116 #define AML_SDXC_PDMA_RX_FLUSH_NOW (1 << 30)
117 #define AML_SDXC_PDMA_RX_FLUSH_MODE_SW (1 << 29)
118 #define AML_SDXC_PDMA_TX_THOLD_MASK (0x3f << 22)
119 #define AML_SDXC_PDMA_TX_THOLD_SHIFT 22
120 #define AML_SDXC_PDMA_RX_THOLD_MASK (0x3f << 15)
121 #define AML_SDXC_PDMA_RX_THOLD_SHIFT 15
122 #define AML_SDXC_PDMA_RD_BURST_MASK (0x1f << 10)
123 #define AML_SDXC_PDMA_RD_BURST_SHIFT 10
124 #define AML_SDXC_PDMA_WR_BURST_MASK (0x1f << 5)
125 #define AML_SDXC_PDMA_WR_BURST_SHIFT 5
126 #define AML_SDXC_PDMA_DMA_URGENT (1 << 4)
127 #define AML_SDXC_PDMA_RESP_INDEX_MASK (7 << 1)
128 #define AML_SDXC_PDMA_RESP_INDEX_SHIFT 1
129 #define AML_SDXC_PDMA_DMA_EN (1 << 0)
131 #define AML_SDXC_MISC_REG 28
132 #define AML_SDXC_MISC_TXSTART_THOLD_MASK (7U << 29)
133 #define AML_SDXC_MISC_TXSTART_THOLD_SHIFT 29
134 #define AML_SDXC_MISC_MANUAL_STOP_MODE (1 << 28)
135 #define AML_SDXC_MISC_WCRC_OK_PAT_MASK (7 << 7)
136 #define AML_SDXC_MISC_WCRC_OK_PAT_SHIFT 7
137 #define AML_SDXC_MISC_WCRC_ERR_PAT_MASK (7 << 4)
138 #define AML_SDXC_MISC_WCRC_ERR_PAT_SHIFT 4
140 #define AML_SDXC_DATA_REG 32
142 #define AML_SDXC_IRQ_ENABLE_REG 36
143 #define AML_SDXC_IRQ_ENABLE_TX_FIFO_EMPTY (1 << 13)
144 #define AML_SDXC_IRQ_ENABLE_RX_FIFO_FULL (1 << 12)
145 #define AML_SDXC_IRQ_ENABLE_DMA_DONE (1 << 11)
146 #define AML_SDXC_IRQ_ENABLE_TRANSFER_DONE_OK (1 << 7)
147 #define AML_SDXC_IRQ_ENABLE_A_PKG_CRC_ERR (1 << 6)
148 #define AML_SDXC_IRQ_ENABLE_A_PKG_TIMEOUT_ERR (1 << 5)
149 #define AML_SDXC_IRQ_ENABLE_A_PKG_DONE_OK (1 << 4)
150 #define AML_SDXC_IRQ_ENABLE_RESP_CRC_ERR (1 << 2)
151 #define AML_SDXC_IRQ_ENABLE_RESP_TIMEOUT_ERR (1 << 1)
152 #define AML_SDXC_IRQ_ENABLE_RESP_OK (1 << 0)
154 #define AML_SDXC_IRQ_ENABLE_STANDARD \
155 (AML_SDXC_IRQ_ENABLE_TX_FIFO_EMPTY | \
156 AML_SDXC_IRQ_ENABLE_RX_FIFO_FULL | \
157 AML_SDXC_IRQ_ENABLE_A_PKG_CRC_ERR | \
158 AML_SDXC_IRQ_ENABLE_A_PKG_TIMEOUT_ERR | \
159 AML_SDXC_IRQ_ENABLE_RESP_CRC_ERR | \
160 AML_SDXC_IRQ_ENABLE_RESP_TIMEOUT_ERR | \
161 AML_SDXC_IRQ_ENABLE_RESP_OK)
163 #define AML_SDXC_IRQ_STATUS_REG 40
164 #define AML_SDXC_IRQ_STATUS_TX_FIFO_EMPTY (1 << 13)
165 #define AML_SDXC_IRQ_STATUS_RX_FIFO_FULL (1 << 12)
166 #define AML_SDXC_IRQ_STATUS_DMA_DONE (1 << 11)
167 #define AML_SDXC_IRQ_STATUS_TRANSFER_DONE_OK (1 << 7)
168 #define AML_SDXC_IRQ_STATUS_A_PKG_CRC_ERR (1 << 6)
169 #define AML_SDXC_IRQ_STATUS_A_PKG_TIMEOUT_ERR (1 << 5)
170 #define AML_SDXC_IRQ_STATUS_A_PKG_DONE_OK (1 << 4)
171 #define AML_SDXC_IRQ_STATUS_RESP_CRC_ERR (1 << 2)
172 #define AML_SDXC_IRQ_STATUS_RESP_TIMEOUT_ERR (1 << 1)
173 #define AML_SDXC_IRQ_STATUS_RESP_OK (1 << 0)
175 #define AML_SDXC_IRQ_STATUS_CLEAR \
176 (AML_SDXC_IRQ_STATUS_TX_FIFO_EMPTY | \
177 AML_SDXC_IRQ_STATUS_RX_FIFO_FULL | \
178 AML_SDXC_IRQ_STATUS_DMA_DONE | \
179 AML_SDXC_IRQ_STATUS_TRANSFER_DONE_OK | \
180 AML_SDXC_IRQ_STATUS_A_PKG_CRC_ERR | \
181 AML_SDXC_IRQ_STATUS_A_PKG_TIMEOUT_ERR | \
182 AML_SDXC_IRQ_STATUS_RESP_CRC_ERR | \
183 AML_SDXC_IRQ_STATUS_RESP_TIMEOUT_ERR | \
184 AML_SDXC_IRQ_STATUS_RESP_OK)
186 #define AML_SDXC_SOFT_RESET_REG 44
187 #define AML_SDXC_SOFT_RESET_DMA (1 << 5)
188 #define AML_SDXC_SOFT_RESET_TX_PHY (1 << 4)
189 #define AML_SDXC_SOFT_RESET_RX_PHY (1 << 3)
190 #define AML_SDXC_SOFT_RESET_TX_FIFO (1 << 2)
191 #define AML_SDXC_SOFT_RESET_RX_FIFO (1 << 1)
192 #define AML_SDXC_SOFT_RESET_MAIN (1 << 0)
194 #define AML_SDXC_SOFT_RESET \
195 (AML_SDXC_SOFT_RESET_DMA | \
196 AML_SDXC_SOFT_RESET_TX_FIFO | \
197 AML_SDXC_SOFT_RESET_RX_FIFO | \
198 AML_SDXC_SOFT_RESET_MAIN)
200 #define AML_SDXC_ENH_CNTRL_REG 52
201 #define AML_SDXC_ENH_CNTRL_TX_EMPTY_THOLD_MASK (0x7f << 25)
202 #define AML_SDXC_ENH_CNTRL_TX_EMPTY_THOLD_SHIFT 25
203 #define AML_SDXC_ENH_CNTRL_RX_FULL_THOLD_MASK (0x7f << 18)
204 #define AML_SDXC_ENH_CNTRL_RX_FULL_THOLD_SHIFT 18
205 #define AML_SDXC_ENH_CNTRL_SDIO_IRQ_PERIOD_MASK (0xff << 8)
206 #define AML_SDXC_ENH_CNTRL_SDIO_IRQ_PERIOD_SHIFT 8
208 #define AML_SDXC_ENH_CNTRL_DMA_NO_WR_RESP_CHECK_M8 (1 << 17)
209 #define AML_SDXC_ENH_CNTRL_DMA_NO_RD_RESP_CHECK_M8 (1 << 16)
210 #define AML_SDXC_ENH_CNTRL_RX_TIMEOUT_MASK_M8 (0xff << 0)
211 #define AML_SDXC_ENH_CNTRL_RX_TIMEOUT_SHIFT_M8 0
213 #define AML_SDXC_ENH_CNTRL_NO_DMA_CHECK_M8M2 (1 << 2)
214 #define AML_SDXC_ENH_CNTRL_NO_WR_RESP_CHECK_M8M2 (1 << 1)
215 #define AML_SDXC_ENH_CNTRL_WR_RESP_MODE_SKIP_M8M2 (1 << 0)
217 #define AML_SDXC_CLK2_REG 56
218 #define AML_SDXC_CLK2_SD_PHASE_MASK (0x3ff << 12)
219 #define AML_SDXC_CLK2_SD_PHASE_SHIFT 12
220 #define AML_SDXC_CLK2_RX_PHASE_MASK (0x3ff << 0)
221 #define AML_SDXC_CLK2_RX_PHASE_SHIFT 0
223 #endif /* _ARM_AMLOGIC_AML8726_SDXC_M8_H */