2 * Copyright 2013-2015 John Wehle <john@feith.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Amlogic aml8726 timer driver.
31 * 16 bit Timer A is used for the event timer / hard clock.
32 * 32 bit Timer E is used for the timecounter / DELAY.
34 * The current implementation doesn't use Timers B-D. Another approach is
35 * to split the timers between the cores implementing per cpu event timers.
37 * The timers all share the MUX register which requires a mutex to serialize
38 * access. The mutex is also used to avoid potential problems between the
39 * interrupt handler and timer_start / timer_stop.
42 #include <sys/cdefs.h>
43 __FBSDID("$FreeBSD$");
45 #include <sys/param.h>
46 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/module.h>
50 #include <sys/malloc.h>
52 #include <sys/timetc.h>
53 #include <sys/timeet.h>
55 #include <machine/bus.h>
56 #include <machine/cpu.h>
58 #include <dev/ofw/ofw_bus.h>
59 #include <dev/ofw/ofw_bus_subr.h>
61 struct aml8726_timer_softc {
63 struct resource * res[2];
68 uint32_t period_ticks;
69 struct timecounter tc;
72 static struct resource_spec aml8726_timer_spec[] = {
73 { SYS_RES_MEMORY, 0, RF_ACTIVE },
74 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* INT_TIMER_A */
79 * devclass_get_device / device_get_softc could be used
80 * to dynamically locate this, however the timers are a
81 * required device which can't be unloaded so there's
82 * no need for the overhead.
84 static struct aml8726_timer_softc *aml8726_timer_sc = NULL;
86 #define AML_TIMER_LOCK(sc) mtx_lock_spin(&(sc)->mtx)
87 #define AML_TIMER_UNLOCK(sc) mtx_unlock_spin(&(sc)->mtx)
88 #define AML_TIMER_LOCK_INIT(sc) \
89 mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \
91 #define AML_TIMER_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx);
93 #define AML_TIMER_MUX_REG 0
94 #define AML_TIMER_INPUT_1us 0
95 #define AML_TIMER_INPUT_10us 1
96 #define AML_TIMER_INPUT_100us 2
97 #define AML_TIMER_INPUT_1ms 3
98 #define AML_TIMER_INPUT_MASK 3
99 #define AML_TIMER_A_INPUT_MASK 3
100 #define AML_TIMER_A_INPUT_SHIFT 0
101 #define AML_TIMER_B_INPUT_MASK (3 << 2)
102 #define AML_TIMER_B_INPUT_SHIFT 2
103 #define AML_TIMER_C_INPUT_MASK (3 << 4)
104 #define AML_TIMER_C_INPUT_SHIFT 4
105 #define AML_TIMER_D_INPUT_MASK (3 << 6)
106 #define AML_TIMER_D_INPUT_SHIFT 6
107 #define AML_TIMER_E_INPUT_SYS 0
108 #define AML_TIMER_E_INPUT_1us 1
109 #define AML_TIMER_E_INPUT_10us 2
110 #define AML_TIMER_E_INPUT_100us 3
111 #define AML_TIMER_E_INPUT_1ms 4
112 #define AML_TIMER_E_INPUT_MASK (7 << 8)
113 #define AML_TIMER_E_INPUT_SHIFT 8
114 #define AML_TIMER_A_PERIODIC (1 << 12)
115 #define AML_TIMER_B_PERIODIC (1 << 13)
116 #define AML_TIMER_C_PERIODIC (1 << 14)
117 #define AML_TIMER_D_PERIODIC (1 << 15)
118 #define AML_TIMER_A_EN (1 << 16)
119 #define AML_TIMER_B_EN (1 << 17)
120 #define AML_TIMER_C_EN (1 << 18)
121 #define AML_TIMER_D_EN (1 << 19)
122 #define AML_TIMER_E_EN (1 << 20)
123 #define AML_TIMER_A_REG 4
124 #define AML_TIMER_B_REG 8
125 #define AML_TIMER_C_REG 12
126 #define AML_TIMER_D_REG 16
127 #define AML_TIMER_E_REG 20
129 #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val))
130 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg)
133 aml8726_get_timecount(struct timecounter *tc)
135 struct aml8726_timer_softc *sc =
136 (struct aml8726_timer_softc *)tc->tc_priv;
138 return CSR_READ_4(sc, AML_TIMER_E_REG);
142 aml8726_hardclock(void *arg)
144 struct aml8726_timer_softc *sc = (struct aml8726_timer_softc *)arg;
148 if (sc->first_ticks != 0 && sc->period_ticks != 0) {
151 CSR_WRITE_4(sc, AML_TIMER_A_REG, sc->period_ticks);
152 CSR_WRITE_4(sc, AML_TIMER_MUX_REG,
153 (CSR_READ_4(sc, AML_TIMER_MUX_REG) |
154 AML_TIMER_A_PERIODIC | AML_TIMER_A_EN));
157 AML_TIMER_UNLOCK(sc);
159 if (sc->et.et_active)
160 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
162 return (FILTER_HANDLED);
166 aml8726_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
168 struct aml8726_timer_softc *sc =
169 (struct aml8726_timer_softc *)et->et_priv;
170 uint32_t first_ticks;
171 uint32_t period_ticks;
175 first_ticks = (first * et->et_frequency) / SBT_1S;
176 period_ticks = (period * et->et_frequency) / SBT_1S;
178 if (first_ticks != 0) {
183 ticks = period_ticks;
184 periodic = AML_TIMER_A_PERIODIC;
192 sc->first_ticks = first_ticks;
193 sc->period_ticks = period_ticks;
195 CSR_WRITE_4(sc, AML_TIMER_A_REG, ticks);
196 CSR_WRITE_4(sc, AML_TIMER_MUX_REG,
197 ((CSR_READ_4(sc, AML_TIMER_MUX_REG) & ~AML_TIMER_A_PERIODIC) |
198 AML_TIMER_A_EN | periodic));
200 AML_TIMER_UNLOCK(sc);
206 aml8726_timer_stop(struct eventtimer *et)
208 struct aml8726_timer_softc *sc =
209 (struct aml8726_timer_softc *)et->et_priv;
213 CSR_WRITE_4(sc, AML_TIMER_MUX_REG,
214 (CSR_READ_4(sc, AML_TIMER_MUX_REG) & ~AML_TIMER_A_EN));
216 AML_TIMER_UNLOCK(sc);
222 aml8726_timer_probe(device_t dev)
225 if (!ofw_bus_status_okay(dev))
228 if (!ofw_bus_is_compatible(dev, "amlogic,meson6-timer"))
231 device_set_desc(dev, "Amlogic aml8726 timer");
233 return (BUS_PROBE_DEFAULT);
237 aml8726_timer_attach(device_t dev)
239 struct aml8726_timer_softc *sc = device_get_softc(dev);
241 /* There should be exactly one instance. */
242 if (aml8726_timer_sc != NULL)
247 if (bus_alloc_resources(dev, aml8726_timer_spec, sc->res)) {
248 device_printf(dev, "can not allocate resources for device\n");
253 * Disable the timers, select the input for each timer,
254 * clear timer E, and then enable timer E.
256 CSR_WRITE_4(sc, AML_TIMER_MUX_REG,
257 ((CSR_READ_4(sc, AML_TIMER_MUX_REG) &
258 ~(AML_TIMER_A_EN | AML_TIMER_A_INPUT_MASK |
259 AML_TIMER_E_EN | AML_TIMER_E_INPUT_MASK)) |
260 (AML_TIMER_INPUT_1us << AML_TIMER_A_INPUT_SHIFT) |
261 (AML_TIMER_E_INPUT_1us << AML_TIMER_E_INPUT_SHIFT)));
263 CSR_WRITE_4(sc, AML_TIMER_E_REG, 0);
265 CSR_WRITE_4(sc, AML_TIMER_MUX_REG,
266 (CSR_READ_4(sc, AML_TIMER_MUX_REG) | AML_TIMER_E_EN));
269 * Initialize the mutex prior to installing the interrupt handler
270 * in case of a spurious interrupt.
272 AML_TIMER_LOCK_INIT(sc);
274 if (bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK,
275 aml8726_hardclock, NULL, sc, &sc->ih_cookie)) {
276 device_printf(dev, "could not setup interrupt handler\n");
277 bus_release_resources(dev, aml8726_timer_spec, sc->res);
278 AML_TIMER_LOCK_DESTROY(sc);
282 aml8726_timer_sc = sc;
284 sc->et.et_name = "aml8726 timer A";
285 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
286 sc->et.et_frequency = 1000000;
287 sc->et.et_quality = 1000;
288 sc->et.et_min_period = (0x00000002LLU * SBT_1S) / sc->et.et_frequency;
289 sc->et.et_max_period = (0x0000fffeLLU * SBT_1S) / sc->et.et_frequency;
290 sc->et.et_start = aml8726_timer_start;
291 sc->et.et_stop = aml8726_timer_stop;
294 et_register(&sc->et);
296 sc->tc.tc_get_timecount = aml8726_get_timecount;
297 sc->tc.tc_name = "aml8726 timer E";
298 sc->tc.tc_frequency = 1000000;
299 sc->tc.tc_counter_mask = ~0u;
300 sc->tc.tc_quality = 1000;
309 aml8726_timer_detach(device_t dev)
315 static device_method_t aml8726_timer_methods[] = {
316 /* Device interface */
317 DEVMETHOD(device_probe, aml8726_timer_probe),
318 DEVMETHOD(device_attach, aml8726_timer_attach),
319 DEVMETHOD(device_detach, aml8726_timer_detach),
324 static driver_t aml8726_timer_driver = {
326 aml8726_timer_methods,
327 sizeof(struct aml8726_timer_softc),
330 static devclass_t aml8726_timer_devclass;
332 EARLY_DRIVER_MODULE(timer, simplebus, aml8726_timer_driver,
333 aml8726_timer_devclass, 0, 0, BUS_PASS_TIMER);
339 uint32_t delta, now, previous, remaining;
341 /* Timer has not yet been initialized */
342 if (aml8726_timer_sc == NULL) {
343 for (; usec > 0; usec--)
344 for (counter = 200; counter > 0; counter--) {
345 /* Prevent gcc from optimizing out the loop */
352 * Some of the other timers in the source tree do this calculation as:
354 * usec * ((sc->tc.tc_frequency / 1000000) + 1)
356 * which gives a fairly pessimistic result when tc_frequency is an exact
357 * multiple of 1000000. Given the data type and typical values for
358 * tc_frequency adding 999999 shouldn't overflow.
360 remaining = usec * ((aml8726_timer_sc->tc.tc_frequency + 999999) /
364 * We add one since the first iteration may catch the counter just
369 previous = aml8726_get_timecount(&aml8726_timer_sc->tc);
372 now = aml8726_get_timecount(&aml8726_timer_sc->tc);
375 * If the timer has rolled over, then we have the case:
377 * if (previous > now) {
378 * delta = (0 - previous) + now
381 * which is really no different then the normal case.
382 * Both cases are simply:
384 * delta = now - previous.
386 delta = now - previous;
388 if (delta >= remaining)