2 * Copyright 2013-2015 John Wehle <john@feith.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Amlogic aml8726 watchdog driver.
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
40 #include <sys/malloc.h>
43 #include <sys/watchdog.h>
45 #include <machine/bus.h>
46 #include <machine/cpufunc.h>
48 #include <dev/fdt/fdt_common.h>
49 #include <dev/ofw/ofw_bus.h>
50 #include <dev/ofw/ofw_bus_subr.h>
52 #include <arm/amlogic/aml8726/aml8726_soc.h>
55 struct aml8726_wdt_softc {
57 struct resource * res[2];
62 static struct resource_spec aml8726_wdt_spec[] = {
63 { SYS_RES_MEMORY, 0, RF_ACTIVE },
64 { SYS_RES_IRQ, 0, RF_ACTIVE },
69 uint32_t ctrl_cpu_mask;
71 uint32_t term_cnt_mask;
72 uint32_t reset_cnt_mask;
73 } aml8726_wdt_soc_params;
76 * devclass_get_device / device_get_softc could be used
77 * to dynamically locate this, however the wdt is a
78 * required device which can't be unloaded so there's
79 * no need for the overhead.
81 static struct aml8726_wdt_softc *aml8726_wdt_sc = NULL;
83 #define AML_WDT_LOCK(sc) mtx_lock_spin(&(sc)->mtx)
84 #define AML_WDT_UNLOCK(sc) mtx_unlock_spin(&(sc)->mtx)
85 #define AML_WDT_LOCK_INIT(sc) \
86 mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \
88 #define AML_WDT_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx);
90 #define AML_WDT_CTRL_REG 0
91 #define AML_WDT_CTRL_CPU_WDRESET_MASK aml8726_wdt_soc_params.ctrl_cpu_mask
92 #define AML_WDT_CTRL_CPU_WDRESET_SHIFT 24
93 #define AML_WDT_CTRL_IRQ_EN (1 << 23)
94 #define AML_WDT_CTRL_EN aml8726_wdt_soc_params.ctrl_en
95 #define AML_WDT_CTRL_TERMINAL_CNT_MASK aml8726_wdt_soc_params.term_cnt_mask
96 #define AML_WDT_CTRL_TERMINAL_CNT_SHIFT 0
97 #define AML_WDT_RESET_REG 4
98 #define AML_WDT_RESET_CNT_MASK aml8726_wdt_soc_params.reset_cnt_mask
99 #define AML_WDT_RESET_CNT_SHIFT 0
101 #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val))
102 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg)
103 #define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \
104 (BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE))
107 aml8726_wdt_watchdog(void *private, u_int cmd, int *error)
109 struct aml8726_wdt_softc *sc = (struct aml8726_wdt_softc *)private;
111 uint64_t tens_of_usec;
115 tens_of_usec = (((uint64_t)1 << (cmd & WD_INTERVAL)) + 9999) / 10000;
117 if (cmd != 0 && tens_of_usec <= (AML_WDT_CTRL_TERMINAL_CNT_MASK >>
118 AML_WDT_CTRL_TERMINAL_CNT_SHIFT)) {
120 wcr = AML_WDT_CTRL_CPU_WDRESET_MASK |
121 AML_WDT_CTRL_EN | ((uint32_t)tens_of_usec <<
122 AML_WDT_CTRL_TERMINAL_CNT_SHIFT);
124 CSR_WRITE_4(sc, AML_WDT_RESET_REG, 0);
125 CSR_WRITE_4(sc, AML_WDT_CTRL_REG, wcr);
129 CSR_WRITE_4(sc, AML_WDT_CTRL_REG,
130 (CSR_READ_4(sc, AML_WDT_CTRL_REG) &
131 ~(AML_WDT_CTRL_IRQ_EN | AML_WDT_CTRL_EN)));
137 aml8726_wdt_intr(void *arg)
139 struct aml8726_wdt_softc *sc = (struct aml8726_wdt_softc *)arg;
142 * Normally a timeout causes a hardware reset, however
143 * the watchdog timer can be configured to cause an
144 * interrupt instead by setting AML_WDT_CTRL_IRQ_EN
145 * and clearing AML_WDT_CTRL_CPU_WDRESET_MASK.
150 CSR_WRITE_4(sc, AML_WDT_CTRL_REG,
151 (CSR_READ_4(sc, AML_WDT_CTRL_REG) & ~(AML_WDT_CTRL_IRQ_EN |
154 CSR_BARRIER(sc, AML_WDT_CTRL_REG);
158 device_printf(sc->dev, "timeout expired\n");
160 return (FILTER_HANDLED);
164 aml8726_wdt_probe(device_t dev)
167 if (!ofw_bus_status_okay(dev))
170 if (!ofw_bus_is_compatible(dev, "amlogic,aml8726-wdt"))
173 device_set_desc(dev, "Amlogic aml8726 WDT");
175 return (BUS_PROBE_DEFAULT);
179 aml8726_wdt_attach(device_t dev)
181 struct aml8726_wdt_softc *sc = device_get_softc(dev);
183 /* There should be exactly one instance. */
184 if (aml8726_wdt_sc != NULL)
189 if (bus_alloc_resources(dev, aml8726_wdt_spec, sc->res)) {
190 device_printf(dev, "can not allocate resources for device\n");
195 * Certain bitfields are dependent on the hardware revision.
197 switch (aml8726_soc_hw_rev) {
198 case AML_SOC_HW_REV_M8:
199 aml8726_wdt_soc_params.ctrl_cpu_mask = 0xf <<
200 AML_WDT_CTRL_CPU_WDRESET_SHIFT;
201 switch (aml8726_soc_metal_rev) {
202 case AML_SOC_M8_METAL_REV_M2_A:
203 aml8726_wdt_soc_params.ctrl_en = 1 << 19;
204 aml8726_wdt_soc_params.term_cnt_mask = 0x07ffff <<
205 AML_WDT_CTRL_TERMINAL_CNT_SHIFT;
206 aml8726_wdt_soc_params.reset_cnt_mask = 0x07ffff <<
207 AML_WDT_RESET_CNT_SHIFT;
210 aml8726_wdt_soc_params.ctrl_en = 1 << 22;
211 aml8726_wdt_soc_params.term_cnt_mask = 0x3fffff <<
212 AML_WDT_CTRL_TERMINAL_CNT_SHIFT;
213 aml8726_wdt_soc_params.reset_cnt_mask = 0x3fffff <<
214 AML_WDT_RESET_CNT_SHIFT;
218 case AML_SOC_HW_REV_M8B:
219 aml8726_wdt_soc_params.ctrl_cpu_mask = 0xf <<
220 AML_WDT_CTRL_CPU_WDRESET_SHIFT;
221 aml8726_wdt_soc_params.ctrl_en = 1 << 19;
222 aml8726_wdt_soc_params.term_cnt_mask = 0x07ffff <<
223 AML_WDT_CTRL_TERMINAL_CNT_SHIFT;
224 aml8726_wdt_soc_params.reset_cnt_mask = 0x07ffff <<
225 AML_WDT_RESET_CNT_SHIFT;
228 aml8726_wdt_soc_params.ctrl_cpu_mask = 3 <<
229 AML_WDT_CTRL_CPU_WDRESET_SHIFT;
230 aml8726_wdt_soc_params.ctrl_en = 1 << 22;
231 aml8726_wdt_soc_params.term_cnt_mask = 0x3fffff <<
232 AML_WDT_CTRL_TERMINAL_CNT_SHIFT;
233 aml8726_wdt_soc_params.reset_cnt_mask = 0x3fffff <<
234 AML_WDT_RESET_CNT_SHIFT;
239 * Disable the watchdog.
241 CSR_WRITE_4(sc, AML_WDT_CTRL_REG,
242 (CSR_READ_4(sc, AML_WDT_CTRL_REG) & ~(AML_WDT_CTRL_IRQ_EN |
246 * Initialize the mutex prior to installing the interrupt handler
247 * in case of a spurious interrupt.
249 AML_WDT_LOCK_INIT(sc);
251 if (bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE,
252 aml8726_wdt_intr, NULL, sc, &sc->ih_cookie)) {
253 device_printf(dev, "could not setup interrupt handler\n");
254 bus_release_resources(dev, aml8726_wdt_spec, sc->res);
255 AML_WDT_LOCK_DESTROY(sc);
261 EVENTHANDLER_REGISTER(watchdog_list, aml8726_wdt_watchdog, sc, 0);
267 aml8726_wdt_detach(device_t dev)
273 static device_method_t aml8726_wdt_methods[] = {
274 /* Device interface */
275 DEVMETHOD(device_probe, aml8726_wdt_probe),
276 DEVMETHOD(device_attach, aml8726_wdt_attach),
277 DEVMETHOD(device_detach, aml8726_wdt_detach),
282 static driver_t aml8726_wdt_driver = {
285 sizeof(struct aml8726_wdt_softc),
288 static devclass_t aml8726_wdt_devclass;
290 EARLY_DRIVER_MODULE(wdt, simplebus, aml8726_wdt_driver, aml8726_wdt_devclass,
291 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
297 /* Watchdog has not yet been initialized */
298 if (aml8726_wdt_sc == NULL)
299 printf("Reset hardware has not yet been initialized.\n");
301 CSR_WRITE_4(aml8726_wdt_sc, AML_WDT_RESET_REG, 0);
302 CSR_WRITE_4(aml8726_wdt_sc, AML_WDT_CTRL_REG,
303 (AML_WDT_CTRL_CPU_WDRESET_MASK | AML_WDT_CTRL_EN |
304 (10 << AML_WDT_CTRL_TERMINAL_CNT_SHIFT)));