2 * Copyright 2013-2015 John Wehle <john@feith.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Amlogic aml8726 UART driver.
30 * The current implementation only targets features common to all
31 * uarts. For example ... though UART A as a 128 byte FIFO, the
32 * others only have a 64 byte FIFO.
34 * Also, it's assumed that the USE_XTAL_CLK feature (available on
35 * the aml8726-m6 and later) has not been activated.
38 #include <sys/cdefs.h>
39 __FBSDID("$FreeBSD$");
41 #include <sys/param.h>
42 #include <sys/systm.h>
45 #include <sys/kernel.h>
46 #include <sys/sysctl.h>
48 #include <machine/bus.h>
49 #include <machine/cpu.h>
51 #include <dev/fdt/fdt_common.h>
52 #include <dev/ofw/ofw_bus.h>
53 #include <dev/ofw/ofw_bus_subr.h>
55 #include <dev/uart/uart.h>
56 #include <dev/uart/uart_cpu.h>
57 #include <dev/uart/uart_cpu_fdt.h>
58 #include <dev/uart/uart_bus.h>
60 #include <arm/amlogic/aml8726/aml8726_soc.h>
61 #include <arm/amlogic/aml8726/aml8726_uart.h>
68 #define uart_getreg(bas, reg) \
69 bus_space_read_4((bas)->bst, (bas)->bsh, reg)
70 #define uart_setreg(bas, reg, value) \
71 bus_space_write_4((bas)->bst, (bas)->bsh, reg, value)
73 #define SIGCHG(c, i, s, d) \
76 i |= (i & s) ? s : s | d; \
78 i = (i & s) ? (i & ~s) | d : i; \
83 aml8726_uart_divisor(int rclk, int baudrate)
85 int actual_baud, divisor;
91 /* integer version of (rclk / baudrate + .5) */
92 divisor = ((rclk << 1) + baudrate) / (baudrate << 1);
95 actual_baud = rclk / divisor;
97 /* 10 times error in percent: */
98 error = (((actual_baud - baudrate) * 2000) / baudrate + 1) >> 1;
100 /* 3.0% maximum error tolerance: */
101 if (error < -30 || error > 30)
108 aml8726_uart_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
116 cr = uart_getreg(bas, AML_UART_CONTROL_REG);
118 cr &= ~(AML_UART_CONTROL_DB_MASK | AML_UART_CONTROL_SB_MASK |
119 AML_UART_CONTROL_P_MASK);
122 case 5: cr |= AML_UART_CONTROL_5_DB; break;
123 case 6: cr |= AML_UART_CONTROL_6_DB; break;
124 case 7: cr |= AML_UART_CONTROL_7_DB; break;
125 case 8: cr |= AML_UART_CONTROL_8_DB; break;
126 default: return (EINVAL);
130 case 1: cr |= AML_UART_CONTROL_1_SB; break;
131 case 2: cr |= AML_UART_CONTROL_2_SB; break;
132 default: return (EINVAL);
136 case UART_PARITY_EVEN: cr |= AML_UART_CONTROL_P_EVEN;
137 cr |= AML_UART_CONTROL_P_EN;
140 case UART_PARITY_ODD: cr |= AML_UART_CONTROL_P_ODD;
141 cr |= AML_UART_CONTROL_P_EN;
144 case UART_PARITY_NONE: break;
146 default: return (EINVAL);
150 if (baudrate > 0 && bas->rclk != 0) {
151 divisor = aml8726_uart_divisor(bas->rclk / 4, baudrate) - 1;
153 switch (aml8726_soc_hw_rev) {
154 case AML_SOC_HW_REV_M6:
155 case AML_SOC_HW_REV_M8:
156 case AML_SOC_HW_REV_M8B:
157 if (divisor > (AML_UART_NEW_BAUD_RATE_MASK >>
158 AML_UART_NEW_BAUD_RATE_SHIFT))
161 nbr = uart_getreg(bas, AML_UART_NEW_BAUD_REG);
162 nbr &= ~(AML_UART_NEW_BAUD_USE_XTAL_CLK |
163 AML_UART_NEW_BAUD_RATE_MASK);
164 nbr |= AML_UART_NEW_BAUD_RATE_EN |
165 (divisor << AML_UART_NEW_BAUD_RATE_SHIFT);
166 uart_setreg(bas, AML_UART_NEW_BAUD_REG, nbr);
171 if (divisor > 0xffff)
176 cr &= ~AML_UART_CONTROL_BAUD_MASK;
177 cr |= (divisor & AML_UART_CONTROL_BAUD_MASK);
179 divisor >>= AML_UART_CONTROL_BAUD_WIDTH;
181 mr = uart_getreg(bas, AML_UART_MISC_REG);
182 mr &= ~(AML_UART_MISC_OLD_RX_BAUD |
183 AML_UART_MISC_BAUD_EXT_MASK);
184 mr |= ((divisor << AML_UART_MISC_BAUD_EXT_SHIFT) &
185 AML_UART_MISC_BAUD_EXT_MASK);
186 uart_setreg(bas, AML_UART_MISC_REG, mr);
189 uart_setreg(bas, AML_UART_CONTROL_REG, cr);
196 * Low-level UART interface.
200 aml8726_uart_probe(struct uart_bas *bas)
207 aml8726_uart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
213 (void)aml8726_uart_param(bas, baudrate, databits, stopbits, parity);
215 cr = uart_getreg(bas, AML_UART_CONTROL_REG);
216 /* Disable all interrupt sources. */
217 cr &= ~(AML_UART_CONTROL_TX_INT_EN | AML_UART_CONTROL_RX_INT_EN);
218 /* Reset the transmitter and receiver. */
219 cr |= (AML_UART_CONTROL_TX_RST | AML_UART_CONTROL_RX_RST);
220 /* Enable the transmitter and receiver. */
221 cr |= (AML_UART_CONTROL_TX_EN | AML_UART_CONTROL_RX_EN);
222 uart_setreg(bas, AML_UART_CONTROL_REG, cr);
225 /* Clear RX FIFO level for generating interrupts. */
226 mr = uart_getreg(bas, AML_UART_MISC_REG);
227 mr &= ~AML_UART_MISC_RECV_IRQ_CNT_MASK;
228 uart_setreg(bas, AML_UART_MISC_REG, mr);
231 /* Ensure the reset bits are clear. */
232 cr &= ~(AML_UART_CONTROL_TX_RST | AML_UART_CONTROL_RX_RST);
233 uart_setreg(bas, AML_UART_CONTROL_REG, cr);
238 aml8726_uart_term(struct uart_bas *bas)
243 aml8726_uart_putc(struct uart_bas *bas, int c)
246 while ((uart_getreg(bas, AML_UART_STATUS_REG) &
247 AML_UART_STATUS_TX_FIFO_FULL) != 0)
250 uart_setreg(bas, AML_UART_WFIFO_REG, c);
255 aml8726_uart_rxready(struct uart_bas *bas)
258 return ((uart_getreg(bas, AML_UART_STATUS_REG) &
259 AML_UART_STATUS_RX_FIFO_EMPTY) == 0 ? 1 : 0);
263 aml8726_uart_getc(struct uart_bas *bas, struct mtx *hwmtx)
269 while ((uart_getreg(bas, AML_UART_STATUS_REG) &
270 AML_UART_STATUS_RX_FIFO_EMPTY) != 0) {
276 c = uart_getreg(bas, AML_UART_RFIFO_REG) & 0xff;
283 struct uart_ops aml8726_uart_ops = {
284 .probe = aml8726_uart_probe,
285 .init = aml8726_uart_init,
286 .term = aml8726_uart_term,
287 .putc = aml8726_uart_putc,
288 .rxready = aml8726_uart_rxready,
289 .getc = aml8726_uart_getc,
293 aml8726_uart_bus_clk(phandle_t node)
299 len = OF_getencprop(node, "clocks", &prop, sizeof(prop));
300 if ((len / sizeof(prop)) != 1 || prop == 0 ||
301 (clk_node = OF_node_from_xref(prop)) == 0)
304 len = OF_getencprop(clk_node, "clock-frequency", &prop, sizeof(prop));
305 if ((len / sizeof(prop)) != 1 || prop == 0)
308 return ((unsigned int)prop);
312 aml8726_uart_bus_probe(struct uart_softc *sc)
316 error = aml8726_uart_probe(&sc->sc_bas);
320 sc->sc_rxfifosz = 64;
321 sc->sc_txfifosz = 64;
325 device_set_desc(sc->sc_dev, "Amlogic aml8726 UART");
331 aml8726_uart_bus_getsig(struct uart_softc *sc)
333 uint32_t new, old, sig;
336 * Treat DSR, DCD, and CTS as always on.
342 SIGCHG(1, sig, SER_DSR, SER_DDSR);
343 SIGCHG(1, sig, SER_DCD, SER_DDCD);
344 SIGCHG(1, sig, SER_CTS, SER_DCTS);
345 new = sig & ~SER_MASK_DELTA;
346 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
352 aml8726_uart_bus_setsig(struct uart_softc *sc, int sig)
359 if (sig & SER_DDTR) {
360 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR);
362 if (sig & SER_DRTS) {
363 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS);
365 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
371 aml8726_uart_bus_attach(struct uart_softc *sc)
373 struct uart_bas *bas;
379 bas->rclk = aml8726_uart_bus_clk(ofw_bus_get_node(sc->sc_dev));
381 if (bas->rclk == 0) {
382 device_printf(sc->sc_dev, "missing clocks attribute in FDT\n");
386 cr = uart_getreg(bas, AML_UART_CONTROL_REG);
387 /* Disable all interrupt sources. */
388 cr &= ~(AML_UART_CONTROL_TX_INT_EN | AML_UART_CONTROL_RX_INT_EN);
389 /* Ensure the reset bits are clear. */
390 cr &= ~(AML_UART_CONTROL_TX_RST | AML_UART_CONTROL_RX_RST);
393 * Reset the transmitter and receiver only if not acting as a
394 * console, otherwise it means that:
396 * 1) aml8726_uart_init was already called which did the reset
398 * 2) there may be console bytes sitting in the transmit fifo
400 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE)
403 cr |= (AML_UART_CONTROL_TX_RST | AML_UART_CONTROL_RX_RST);
405 /* Default to two wire mode. */
406 cr |= AML_UART_CONTROL_TWO_WIRE_EN;
407 /* Enable the transmitter and receiver. */
408 cr |= (AML_UART_CONTROL_TX_EN | AML_UART_CONTROL_RX_EN);
409 /* Reset error bits. */
410 cr |= AML_UART_CONTROL_CLR_ERR;
411 uart_setreg(bas, AML_UART_CONTROL_REG, cr);
414 /* Set FIFO levels for generating interrupts. */
415 mr = uart_getreg(bas, AML_UART_MISC_REG);
416 mr &= ~AML_UART_MISC_XMIT_IRQ_CNT_MASK;
417 mr |= (0 << AML_UART_MISC_XMIT_IRQ_CNT_SHIFT);
418 mr &= ~AML_UART_MISC_RECV_IRQ_CNT_MASK;
419 mr |= (1 << AML_UART_MISC_RECV_IRQ_CNT_SHIFT);
420 uart_setreg(bas, AML_UART_MISC_REG, mr);
423 aml8726_uart_bus_getsig(sc);
425 /* Ensure the reset bits are clear. */
426 cr &= ~(AML_UART_CONTROL_TX_RST | AML_UART_CONTROL_RX_RST);
427 cr &= ~AML_UART_CONTROL_CLR_ERR;
428 /* Enable the receive interrupt. */
429 cr |= AML_UART_CONTROL_RX_INT_EN;
430 uart_setreg(bas, AML_UART_CONTROL_REG, cr);
437 aml8726_uart_bus_detach(struct uart_softc *sc)
439 struct uart_bas *bas;
445 /* Disable all interrupt sources. */
446 cr = uart_getreg(bas, AML_UART_CONTROL_REG);
447 cr &= ~(AML_UART_CONTROL_TX_INT_EN | AML_UART_CONTROL_RX_INT_EN);
448 uart_setreg(bas, AML_UART_CONTROL_REG, cr);
451 /* Clear RX FIFO level for generating interrupts. */
452 mr = uart_getreg(bas, AML_UART_MISC_REG);
453 mr &= ~AML_UART_MISC_RECV_IRQ_CNT_MASK;
454 uart_setreg(bas, AML_UART_MISC_REG, mr);
461 aml8726_uart_bus_flush(struct uart_softc *sc, int what)
463 struct uart_bas *bas;
467 uart_lock(sc->sc_hwmtx);
469 cr = uart_getreg(bas, AML_UART_CONTROL_REG);
470 if (what & UART_FLUSH_TRANSMITTER)
471 cr |= AML_UART_CONTROL_TX_RST;
472 if (what & UART_FLUSH_RECEIVER)
473 cr |= AML_UART_CONTROL_RX_RST;
474 uart_setreg(bas, AML_UART_CONTROL_REG, cr);
477 /* Ensure the reset bits are clear. */
478 cr &= ~(AML_UART_CONTROL_TX_RST | AML_UART_CONTROL_RX_RST);
479 uart_setreg(bas, AML_UART_CONTROL_REG, cr);
482 uart_unlock(sc->sc_hwmtx);
488 aml8726_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
490 struct uart_bas *bas;
491 int baudrate, divisor, error;
492 uint32_t cr, mr, nbr;
495 uart_lock(sc->sc_hwmtx);
499 case UART_IOCTL_BAUD:
500 cr = uart_getreg(bas, AML_UART_CONTROL_REG);
501 cr &= AML_UART_CONTROL_BAUD_MASK;
503 mr = uart_getreg(bas, AML_UART_MISC_REG);
504 mr &= AML_UART_MISC_BAUD_EXT_MASK;
506 divisor = ((mr >> AML_UART_MISC_BAUD_EXT_SHIFT) <<
507 AML_UART_CONTROL_BAUD_WIDTH) | cr;
509 switch (aml8726_soc_hw_rev) {
510 case AML_SOC_HW_REV_M6:
511 case AML_SOC_HW_REV_M8:
512 case AML_SOC_HW_REV_M8B:
513 nbr = uart_getreg(bas, AML_UART_NEW_BAUD_REG);
514 if ((nbr & AML_UART_NEW_BAUD_RATE_EN) != 0) {
515 divisor = (nbr & AML_UART_NEW_BAUD_RATE_MASK) >>
516 AML_UART_NEW_BAUD_RATE_SHIFT;
523 baudrate = bas->rclk / 4 / (divisor + 1);
525 *(int*)data = baudrate;
530 case UART_IOCTL_IFLOW:
531 case UART_IOCTL_OFLOW:
532 cr = uart_getreg(bas, AML_UART_CONTROL_REG);
534 cr &= ~AML_UART_CONTROL_TWO_WIRE_EN;
536 cr |= AML_UART_CONTROL_TWO_WIRE_EN;
537 uart_setreg(bas, AML_UART_CONTROL_REG, cr);
545 uart_unlock(sc->sc_hwmtx);
551 aml8726_uart_bus_ipend(struct uart_softc *sc)
553 struct uart_bas *bas;
559 uart_lock(sc->sc_hwmtx);
562 sr = uart_getreg(bas, AML_UART_STATUS_REG);
563 cr = uart_getreg(bas, AML_UART_CONTROL_REG);
565 if ((sr & AML_UART_STATUS_RX_FIFO_OVERFLOW) != 0)
566 ipend |= SER_INT_OVERRUN;
568 if ((sr & AML_UART_STATUS_TX_FIFO_EMPTY) != 0 &&
569 (cr & AML_UART_CONTROL_TX_INT_EN) != 0) {
570 ipend |= SER_INT_TXIDLE;
572 cr &= ~AML_UART_CONTROL_TX_INT_EN;
573 uart_setreg(bas, AML_UART_CONTROL_REG, cr);
577 if ((sr & AML_UART_STATUS_RX_FIFO_EMPTY) == 0)
578 ipend |= SER_INT_RXREADY;
580 uart_unlock(sc->sc_hwmtx);
586 aml8726_uart_bus_param(struct uart_softc *sc, int baudrate, int databits,
587 int stopbits, int parity)
589 struct uart_bas *bas;
593 uart_lock(sc->sc_hwmtx);
595 error = aml8726_uart_param(bas, baudrate, databits, stopbits, parity);
597 uart_unlock(sc->sc_hwmtx);
603 aml8726_uart_bus_receive(struct uart_softc *sc)
605 struct uart_bas *bas;
610 uart_lock(sc->sc_hwmtx);
612 sr = uart_getreg(bas, AML_UART_STATUS_REG);
613 while ((sr & AML_UART_STATUS_RX_FIFO_EMPTY) == 0) {
614 if (uart_rx_full(sc)) {
615 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
618 xc = uart_getreg(bas, AML_UART_RFIFO_REG) & 0xff;
619 if (sr & AML_UART_STATUS_FRAME_ERR)
620 xc |= UART_STAT_FRAMERR;
621 if (sr & AML_UART_STATUS_PARITY_ERR)
622 xc |= UART_STAT_PARERR;
624 sr = uart_getreg(bas, AML_UART_STATUS_REG);
626 /* Discard everything left in the RX FIFO. */
627 while ((sr & AML_UART_STATUS_RX_FIFO_EMPTY) == 0) {
628 (void)uart_getreg(bas, AML_UART_RFIFO_REG);
629 sr = uart_getreg(bas, AML_UART_STATUS_REG);
631 /* Reset error bits */
632 if ((sr & (AML_UART_STATUS_FRAME_ERR | AML_UART_STATUS_PARITY_ERR)) != 0) {
633 uart_setreg(bas, AML_UART_CONTROL_REG,
634 (uart_getreg(bas, AML_UART_CONTROL_REG) |
635 AML_UART_CONTROL_CLR_ERR));
637 uart_setreg(bas, AML_UART_CONTROL_REG,
638 (uart_getreg(bas, AML_UART_CONTROL_REG) &
639 ~AML_UART_CONTROL_CLR_ERR));
643 uart_unlock(sc->sc_hwmtx);
649 aml8726_uart_bus_transmit(struct uart_softc *sc)
651 struct uart_bas *bas;
656 uart_lock(sc->sc_hwmtx);
659 * Wait for sufficient space since aml8726_uart_putc
660 * may have been called after SER_INT_TXIDLE occurred.
662 while ((uart_getreg(bas, AML_UART_STATUS_REG) &
663 AML_UART_STATUS_TX_FIFO_EMPTY) == 0)
666 for (i = 0; i < sc->sc_txdatasz; i++) {
667 uart_setreg(bas, AML_UART_WFIFO_REG, sc->sc_txbuf[i]);
673 cr = uart_getreg(bas, AML_UART_CONTROL_REG);
674 cr |= AML_UART_CONTROL_TX_INT_EN;
675 uart_setreg(bas, AML_UART_CONTROL_REG, cr);
678 uart_unlock(sc->sc_hwmtx);
684 aml8726_uart_bus_grab(struct uart_softc *sc)
686 struct uart_bas *bas;
690 * Disable the receive interrupt to avoid a race between
691 * aml8726_uart_getc and aml8726_uart_bus_receive which
694 * panic: bad stray interrupt
696 * due to the RX FIFO receiving a character causing an
697 * interrupt which gets serviced after aml8726_uart_getc
698 * has been called (meaning the RX FIFO is now empty).
702 uart_lock(sc->sc_hwmtx);
704 cr = uart_getreg(bas, AML_UART_CONTROL_REG);
705 cr &= ~AML_UART_CONTROL_RX_INT_EN;
706 uart_setreg(bas, AML_UART_CONTROL_REG, cr);
709 uart_unlock(sc->sc_hwmtx);
713 aml8726_uart_bus_ungrab(struct uart_softc *sc)
715 struct uart_bas *bas;
720 * The RX FIFO level being set indicates that the device
721 * is currently attached meaning the receive interrupt
726 uart_lock(sc->sc_hwmtx);
728 mr = uart_getreg(bas, AML_UART_MISC_REG);
729 mr &= AML_UART_MISC_RECV_IRQ_CNT_MASK;
732 cr = uart_getreg(bas, AML_UART_CONTROL_REG);
733 cr |= AML_UART_CONTROL_RX_INT_EN;
734 uart_setreg(bas, AML_UART_CONTROL_REG, cr);
738 uart_unlock(sc->sc_hwmtx);
741 static kobj_method_t aml8726_uart_methods[] = {
742 KOBJMETHOD(uart_probe, aml8726_uart_bus_probe),
743 KOBJMETHOD(uart_attach, aml8726_uart_bus_attach),
744 KOBJMETHOD(uart_detach, aml8726_uart_bus_detach),
745 KOBJMETHOD(uart_flush, aml8726_uart_bus_flush),
746 KOBJMETHOD(uart_getsig, aml8726_uart_bus_getsig),
747 KOBJMETHOD(uart_setsig, aml8726_uart_bus_setsig),
748 KOBJMETHOD(uart_ioctl, aml8726_uart_bus_ioctl),
749 KOBJMETHOD(uart_ipend, aml8726_uart_bus_ipend),
750 KOBJMETHOD(uart_param, aml8726_uart_bus_param),
751 KOBJMETHOD(uart_receive, aml8726_uart_bus_receive),
752 KOBJMETHOD(uart_transmit, aml8726_uart_bus_transmit),
753 KOBJMETHOD(uart_grab, aml8726_uart_bus_grab),
754 KOBJMETHOD(uart_ungrab, aml8726_uart_bus_ungrab),
758 struct uart_class uart_aml8726_class = {
760 aml8726_uart_methods,
761 sizeof(struct uart_softc),
762 .uc_ops = &aml8726_uart_ops,
768 static struct ofw_compat_data compat_data[] = {
769 { "amlogic,meson-uart", (uintptr_t)&uart_aml8726_class },
770 { NULL, (uintptr_t)NULL }
772 UART_FDT_CLASS_AND_DEVICE(compat_data);