2 * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
3 * Copyright (c) 2015 Semihalf
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
35 #include <sys/mutex.h>
37 #include <sys/cpuset.h>
42 #include <machine/smp.h>
43 #include <machine/fdt.h>
44 #include <machine/intr.h>
45 #include <machine/cpu-v6.h>
46 #include <machine/platformvar.h>
48 #include <dev/fdt/fdt_common.h>
49 #include <dev/ofw/openfirm.h>
50 #include <dev/ofw/ofw_cpu.h>
51 #include <dev/ofw/ofw_bus_subr.h>
53 #include <arm/annapurna/alpine/alpine_mp.h>
55 #define AL_CPU_RESUME_WATERMARK_REG 0x00
56 #define AL_CPU_RESUME_FLAGS_REG 0x04
57 #define AL_CPU_RESUME_PCPU_RADDR_REG(cpu) (0x08 + 0x04 + 8*(cpu))
58 #define AL_CPU_RESUME_PCPU_FLAGS(cpu) (0x08 + 8*(cpu))
61 #define AL_CPU_RESUME_FLG_PERCPU_DONT_RESUME (1 << 2)
63 /* The expected magic number for validating the resume addresses */
64 #define AL_CPU_RESUME_MAGIC_NUM 0xf0e1d200
65 #define AL_CPU_RESUME_MAGIC_NUM_MASK 0xffffff00
67 /* The expected minimal version number for validating the capabilities */
68 #define AL_CPU_RESUME_MIN_VER 0x000000c3
69 #define AL_CPU_RESUME_MIN_VER_MASK 0x000000ff
71 /* Field controlling the boot-up of companion cores */
72 #define AL_NB_INIT_CONTROL (0x8)
73 #define AL_NB_CONFIG_STATUS_PWR_CTRL(cpu) (0x2020 + (cpu)*0x100)
75 extern bus_addr_t al_devmap_pa;
76 extern bus_addr_t al_devmap_size;
78 extern void mpentry(void);
80 static int platform_mp_get_core_cnt(void);
81 static int alpine_get_cpu_resume_base(u_long *pbase, u_long *psize);
82 static int alpine_get_nb_base(u_long *pbase, u_long *psize);
83 static boolean_t alpine_validate_cpu(u_int, phandle_t, u_int, pcell_t *);
86 alpine_validate_cpu(u_int id, phandle_t child, u_int addr_cell, pcell_t *reg)
88 return ofw_bus_node_is_compatible(child, "arm,cortex-a15");
92 platform_mp_get_core_cnt(void)
94 static int ncores = 0;
98 /* Calculate ncores value only once */
102 reg = cp15_l2ctlr_get();
103 ncores = CPUV7_L2CTLR_NPROC(reg);
105 nchilds = ofw_cpu_early_foreach(alpine_validate_cpu, false);
107 /* Limit CPUs if DTS has configured less than available */
108 if ((nchilds > 0) && (nchilds < ncores)) {
109 printf("SMP: limiting number of active CPUs to %d out of %d\n",
118 alpine_mp_setmaxid(platform_t plat)
121 mp_ncpus = platform_mp_get_core_cnt();
122 mp_maxid = mp_ncpus - 1;
126 alpine_get_cpu_resume_base(u_long *pbase, u_long *psize)
132 if (pbase == NULL || psize == NULL)
135 if ((node = OF_finddevice("/")) == -1)
139 ofw_bus_find_compatible(node, "annapurna-labs,al-cpu-resume")) == 0)
142 if (fdt_regsize(node, &base, &size))
152 alpine_get_nb_base(u_long *pbase, u_long *psize)
158 if (pbase == NULL || psize == NULL)
161 if ((node = OF_finddevice("/")) == -1)
165 ofw_bus_find_compatible(node, "annapurna-labs,al-nb-service")) == 0)
168 if (fdt_regsize(node, &base, &size))
178 alpine_mp_start_ap(platform_t plat)
184 u_long cpu_resume_base;
186 u_long cpu_resume_size;
188 bus_addr_t cpu_resume_baddr;
192 if (alpine_get_cpu_resume_base(&cpu_resume_base, &cpu_resume_size))
193 panic("Couldn't resolve cpu_resume_base address\n");
195 if (alpine_get_nb_base(&nb_base, &nb_size))
196 panic("Couldn't resolve_nb_base address\n");
198 /* Proceed with start addresses for additional CPUs */
199 if (bus_space_map(fdtbus_bs_tag, al_devmap_pa + cpu_resume_base,
200 cpu_resume_size, 0, &cpu_resume_baddr))
201 panic("Couldn't map CPU-resume area");
202 if (bus_space_map(fdtbus_bs_tag, al_devmap_pa + nb_base,
203 nb_size, 0, &nb_baddr))
204 panic("Couldn't map NB-service area");
206 /* Proceed with start addresses for additional CPUs */
207 val = bus_space_read_4(fdtbus_bs_tag, cpu_resume_baddr,
208 AL_CPU_RESUME_WATERMARK_REG);
209 if (((val & AL_CPU_RESUME_MAGIC_NUM_MASK) != AL_CPU_RESUME_MAGIC_NUM) ||
210 ((val & AL_CPU_RESUME_MIN_VER_MASK) < AL_CPU_RESUME_MIN_VER)) {
211 panic("CPU-resume device is not compatible");
214 vaddr = (vm_offset_t)mpentry;
215 physaddr = pmap_kextract(vaddr);
217 for (a = 1; a < platform_mp_get_core_cnt(); a++) {
218 /* Power up the core */
219 bus_space_write_4(fdtbus_bs_tag, nb_baddr,
220 AL_NB_CONFIG_STATUS_PWR_CTRL(a), 0);
224 val = bus_space_read_4(fdtbus_bs_tag, cpu_resume_baddr,
225 AL_CPU_RESUME_PCPU_FLAGS(a));
226 val &= ~AL_CPU_RESUME_FLG_PERCPU_DONT_RESUME;
227 bus_space_write_4(fdtbus_bs_tag, cpu_resume_baddr,
228 AL_CPU_RESUME_PCPU_FLAGS(a), val);
231 /* Set resume physical address */
232 bus_space_write_4(fdtbus_bs_tag, cpu_resume_baddr,
233 AL_CPU_RESUME_PCPU_RADDR_REG(a), physaddr);
237 /* Release cores from reset */
238 if (bus_space_map(fdtbus_bs_tag, al_devmap_pa + nb_base,
239 nb_size, 0, &nb_baddr))
240 panic("Couldn't map NB-service area");
242 start_mask = (1 << platform_mp_get_core_cnt()) - 1;
244 /* Release cores from reset */
245 val = bus_space_read_4(fdtbus_bs_tag, nb_baddr, AL_NB_INIT_CONTROL);
247 bus_space_write_4(fdtbus_bs_tag, nb_baddr, AL_NB_INIT_CONTROL, val);
250 bus_space_unmap(fdtbus_bs_tag, nb_baddr, nb_size);
251 bus_space_unmap(fdtbus_bs_tag, cpu_resume_baddr, cpu_resume_size);