2 * Copyright (c) 2015,2016 Annapurna Labs Ltd. and affiliates
5 * Developed by Semihalf.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/mutex.h>
43 #include <dev/ofw/ofw_bus.h>
44 #include <dev/ofw/ofw_bus_subr.h>
50 #define AL_EDGE_HIGH 1
51 #define ERR_NOT_IN_MAP -1
53 #define GIC_INTR_CELL_CNT 3
54 #define INTR_RANGE_COUNT 2
55 #define MAX_MSIX_COUNT 160
57 static int al_msix_attach(device_t);
58 static int al_msix_probe(device_t);
60 static msi_alloc_msi_t al_msix_alloc_msi;
61 static msi_release_msi_t al_msix_release_msi;
62 static msi_alloc_msix_t al_msix_alloc_msix;
63 static msi_release_msix_t al_msix_release_msix;
64 static msi_map_msi_t al_msix_map_msi;
66 static int al_find_intr_pos_in_map(device_t, struct intr_irqsrc *);
68 static struct ofw_compat_data compat_data[] = {
69 {"annapurna-labs,al-msix", true},
70 {"annapurna-labs,alpine-msix", true},
75 * Bus interface definitions.
77 static device_method_t al_msix_methods[] = {
78 DEVMETHOD(device_probe, al_msix_probe),
79 DEVMETHOD(device_attach, al_msix_attach),
81 /* Interrupt controller interface */
82 DEVMETHOD(msi_alloc_msi, al_msix_alloc_msi),
83 DEVMETHOD(msi_release_msi, al_msix_release_msi),
84 DEVMETHOD(msi_alloc_msix, al_msix_alloc_msix),
85 DEVMETHOD(msi_release_msix, al_msix_release_msix),
86 DEVMETHOD(msi_map_msi, al_msix_map_msi),
91 struct al_msix_softc {
100 /* Table of isrcs maps isrc pointer to vmem_alloc'd irq number */
101 struct intr_irqsrc *isrcs[MAX_MSIX_COUNT];
104 static driver_t al_msix_driver = {
107 sizeof(struct al_msix_softc),
110 devclass_t al_msix_devclass;
112 DRIVER_MODULE(al_msix, ofwbus, al_msix_driver, al_msix_devclass, 0, 0);
113 DRIVER_MODULE(al_msix, simplebus, al_msix_driver, al_msix_devclass, 0, 0);
115 MALLOC_DECLARE(M_AL_MSIX);
116 MALLOC_DEFINE(M_AL_MSIX, "al_msix", "Alpine MSIX");
119 al_msix_probe(device_t dev)
122 if (!ofw_bus_status_okay(dev))
125 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
128 device_set_desc(dev, "Annapurna-Labs MSI-X Controller");
129 return (BUS_PROBE_DEFAULT);
133 al_msix_attach(device_t dev)
135 struct al_msix_softc *sc;
140 int interrupts[INTR_RANGE_COUNT];
142 uint32_t icells, *intr;
144 sc = device_get_softc(dev);
146 node = ofw_bus_get_node(dev);
147 xref = OF_xref_from_node(node);
148 OF_device_register_xref(xref, dev);
151 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
152 if (sc->res == NULL) {
153 device_printf(dev, "Failed to allocate resource\n");
157 sc->base_addr = (bus_addr_t)rman_get_start(sc->res);
159 /* Register this device to handle MSI interrupts */
160 if (intr_msi_register(dev, xref) != 0) {
161 device_printf(dev, "could not register MSI-X controller\n");
165 device_printf(dev, "MSI-X controller registered\n");
167 /* Find root interrupt controller */
168 iparent = ofw_bus_find_iparent(node);
170 device_printf(dev, "No interrupt-parrent found. "
174 /* While at parent - store interrupt cells prop */
175 if (OF_searchencprop(OF_node_from_xref(iparent),
176 "#interrupt-cells", &icells, sizeof(icells)) == -1) {
177 device_printf(dev, "DTB: Missing #interrupt-cells "
178 "property in GIC node\n");
183 gic_dev = OF_device_from_xref(iparent);
184 if (gic_dev == NULL) {
185 device_printf(dev, "Cannot find GIC device\n");
188 sc->gic_dev = gic_dev;
190 /* Manually read range of interrupts from DTB */
191 nintr = OF_getencprop_alloc_multi(node, "interrupts", sizeof(*intr),
194 device_printf(dev, "Cannot read interrupts prop from DTB\n");
196 } else if ((nintr / icells) != INTR_RANGE_COUNT) {
197 /* Supposed to have min and max value only */
198 device_printf(dev, "Unexpected count of interrupts "
203 /* Read interrupt range values */
204 for (i = 0; i < INTR_RANGE_COUNT; i++)
205 interrupts[i] = intr[(i * icells) + IRQ_OFFSET];
207 sc->irq_min = interrupts[0];
208 sc->irq_max = interrupts[1];
209 sc->irq_count = (sc->irq_max - sc->irq_min + 1);
211 if (sc->irq_count > MAX_MSIX_COUNT) {
212 device_printf(dev, "Available MSI-X count exceeds buffer size."
213 " Capping to %d\n", MAX_MSIX_COUNT);
214 sc->irq_count = MAX_MSIX_COUNT;
217 mtx_init(&sc->msi_mtx, "msi_mtx", NULL, MTX_DEF);
219 sc->irq_alloc = vmem_create("Alpine MSI-X IRQs", 0, sc->irq_count,
220 1, 0, M_FIRSTFIT | M_WAITOK);
222 device_printf(dev, "MSI-X SPI IRQ %d-%d\n", sc->irq_min, sc->irq_max);
224 return (bus_generic_attach(dev));
228 al_find_intr_pos_in_map(device_t dev, struct intr_irqsrc *isrc)
230 struct al_msix_softc *sc;
233 sc = device_get_softc(dev);
234 for (i = 0; i < MAX_MSIX_COUNT; i++)
235 if (sc->isrcs[i] == isrc)
237 return (ERR_NOT_IN_MAP);
241 al_msix_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc,
242 uint64_t *addr, uint32_t *data)
244 struct al_msix_softc *sc;
247 sc = device_get_softc(dev);
249 i = al_find_intr_pos_in_map(dev, isrc);
250 if (i == ERR_NOT_IN_MAP)
253 spi = sc->irq_min + i;
256 * MSIX message address format:
257 * [63:20] - MSIx TBAR
258 * Same value as the MSIx Translation Base Address Register
260 * Once set by MSIx message, an EVENTI is signal to the CPUs
261 * cluster specified by ‘Local GIC Target List’
262 * [18:17] - Target GIC ID
263 * Specifies which IO-GIC (external shared GIC) is targeted
264 * 0: Local GIC, as specified by the Local GIC Target List
268 * [16:13] - Local GIC Target List
269 * Specifies the Local GICs list targeted by this MSIx
271 * [16] If set, SPIn is set in Cluster 0 local GIC
273 * [15] If set, SPIn is set in Cluster 1 local GIC
274 * [14] If set, SPIn is set in Cluster 2 local GIC
275 * [13] If set, SPIn is set in Cluster 3 local GIC
277 * Specifies the SPI (Shared Peripheral Interrupt) index to
278 * be set in target GICs
280 * If targeting any local GIC than only SPI[249:0] are valid
281 * [2] - Function vector
282 * MSI Data vector extension hint
284 * Must be set to zero
286 *addr = (uint64_t)sc->base_addr + (uint64_t)((1 << 16) + (spi << 3));
290 device_printf(dev, "MSI mapping: SPI: %d addr: %jx data: %x\n",
291 spi, (uintmax_t)*addr, *data);
296 al_msix_alloc_msi(device_t dev, device_t child, int count, int maxcount,
297 device_t *pic, struct intr_irqsrc **srcs)
299 struct intr_map_data_fdt *fdt_data;
300 struct al_msix_softc *sc;
301 vmem_addr_t irq_base;
305 sc = device_get_softc(dev);
307 if ((powerof2(count) == 0) || (count > 8))
310 if (vmem_alloc(sc->irq_alloc, count, M_FIRSTFIT | M_NOWAIT,
314 /* Fabricate OFW data to get ISRC from GIC and return it */
315 fdt_data = malloc(sizeof(*fdt_data) +
316 GIC_INTR_CELL_CNT * sizeof(pcell_t), M_AL_MSIX, M_WAITOK);
317 fdt_data->hdr.type = INTR_MAP_DATA_FDT;
318 fdt_data->iparent = 0;
319 fdt_data->ncells = GIC_INTR_CELL_CNT;
320 fdt_data->cells[0] = AL_SPI_INTR; /* code for SPI interrupt */
321 fdt_data->cells[1] = 0; /* SPI number (uninitialized) */
322 fdt_data->cells[2] = AL_EDGE_HIGH; /* trig = edge, pol = high */
324 mtx_lock(&sc->msi_mtx);
326 for (i = irq_base; i < irq_base + count; i++) {
327 fdt_data->cells[1] = sc->irq_min + i;
328 error = PIC_MAP_INTR(sc->gic_dev,
329 (struct intr_map_data *)fdt_data, srcs);
331 for (j = irq_base; j < i; j++)
333 mtx_unlock(&sc->msi_mtx);
334 vmem_free(sc->irq_alloc, irq_base, count);
335 free(fdt_data, M_AL_MSIX);
339 sc->isrcs[i] = *srcs;
343 mtx_unlock(&sc->msi_mtx);
344 free(fdt_data, M_AL_MSIX);
348 "MSI-X allocation: start SPI %d, count %d\n",
349 (int)irq_base + sc->irq_min, count);
357 al_msix_release_msi(device_t dev, device_t child, int count,
358 struct intr_irqsrc **srcs)
360 struct al_msix_softc *sc;
363 sc = device_get_softc(dev);
365 mtx_lock(&sc->msi_mtx);
367 pos = al_find_intr_pos_in_map(dev, *srcs);
368 vmem_free(sc->irq_alloc, pos, count);
369 for (i = 0; i < count; i++) {
370 pos = al_find_intr_pos_in_map(dev, *srcs);
371 if (pos != ERR_NOT_IN_MAP)
372 sc->isrcs[pos] = NULL;
376 mtx_unlock(&sc->msi_mtx);
382 al_msix_alloc_msix(device_t dev, device_t child, device_t *pic,
383 struct intr_irqsrc **isrcp)
386 return (al_msix_alloc_msi(dev, child, 1, 1, pic, isrcp));
390 al_msix_release_msix(device_t dev, device_t child, struct intr_irqsrc *isrc)
393 return (al_msix_release_msi(dev, child, 1, &isrc));