1 /* $NetBSD: cpufunc_asm.S,v 1.12 2003/09/06 09:14:52 rearnsha Exp $ */
4 * Copyright (c) 1997,1998 Mark Brinicombe.
5 * Copyright (c) 1997 Causality Limited
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
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13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
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17 * must display the following acknowledgement:
18 * This product includes software developed by Causality Limited.
19 * 4. The name of Causality Limited may not be used to endorse or promote
20 * products derived from this software without specific prior written
23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * RiscBSD kernel project
39 * Assembly functions for CPU / MMU / TLB specific operations
45 #include <machine/asm.h>
46 __FBSDID("$FreeBSD$");
56 * Generic functions to read the internal coprocessor registers
58 * Currently these registers are :
66 mrc p15, 0, r0, c0, c0, 0
70 ENTRY(cpu_get_control)
75 ENTRY(cpu_read_cache_config)
76 mrc p15, 0, r0, c0, c0, 1
78 END(cpu_read_cache_config)
80 ENTRY(cpu_faultstatus)
81 mrc p15, 0, r0, c5, c0, 0
85 ENTRY(cpu_faultaddress)
86 mrc p15, 0, r0, c6, c0, 0
91 * Generic functions to write the internal coprocessor registers
94 * Currently these registers are
96 * c3 - Domain Access Control
98 * All other registers are CPU architecture specific
102 mcr p15, 0, r0, c3, c0, 0
107 * Generic functions to read/modify/write the internal coprocessor registers
110 * Currently these registers are
113 * All other registers are CPU architecture specific
116 ENTRY(cpufunc_control)
117 mrc CP15_SCTLR(r3) /* Read the control register */
118 bic r2, r3, r0 /* Clear bits */
119 eor r2, r2, r1 /* XOR bits */
122 teq r2, r3 /* Only write if there is a change */
123 mcrne CP15_SCTLR(r2) /* Write new control register */
124 mov r0, r3 /* Return old value */
133 * other potentially useful software functions are:
134 * clean D cache entry and flush I cache entry
135 * for the moment use cache_purgeID_E
138 /* Random odd functions */
141 * Function to get the offset of a stored program counter from the
142 * instruction doing the store. This offset is defined to be the same
143 * for all STRs and STMs on a given implementation. Code based on
144 * section 2.4.3 of the ARM ARM (2nd Ed.), with modifications to work
145 * in 26-bit modes as well.
147 ENTRY(get_pc_str_offset)
149 stmfd sp!, {fp, ip, lr, pc}
152 mov r1, pc /* R1 = addr of following STR */
154 str pc, [sp] /* [SP] = . + offset */
157 ldmdb fp, {fp, sp, pc}
158 END(get_pc_str_offset)
160 /* Allocate and lock a cacheline for the specified address. */
162 #define CPWAIT_BRANCH \
165 mrc p15, 0, r2, c2, c0, 0; \
169 ENTRY(arm_lock_cache_line)
170 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
172 mcr p15, 0, r1, c9, c2, 0 /* Enable data cache lock mode */
174 mcr p15, 0, r0, c7, c2, 5 /* Allocate the cache line */
175 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
178 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
179 mcr p15, 0, r1, c9, c2, 0 /* Disable data cache lock mode */
182 END(arm_lock_cache_line)