1 /* $NetBSD: cpufunc_asm.S,v 1.12 2003/09/06 09:14:52 rearnsha Exp $ */
4 * Copyright (c) 1997,1998 Mark Brinicombe.
5 * Copyright (c) 1997 Causality Limited
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Causality Limited.
19 * 4. The name of Causality Limited may not be used to endorse or promote
20 * products derived from this software without specific prior written
23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * RiscBSD kernel project
39 * Assembly functions for CPU / MMU / TLB specific operations
45 #include <machine/asm.h>
46 __FBSDID("$FreeBSD$");
56 * Generic functions to read the internal coprocessor registers
58 * Currently these registers are :
66 mrc p15, 0, r0, c0, c0, 0
71 mrc p15, 0, r0, c0, c0, 0
75 ENTRY(cpu_get_control)
76 mrc p15, 0, r0, c1, c0, 0
80 ENTRY(cpu_read_cache_config)
81 mrc p15, 0, r0, c0, c0, 1
83 END(cpu_read_cache_config)
85 ENTRY(cpufunc_faultstatus)
86 mrc p15, 0, r0, c5, c0, 0
88 END(cpufunc_faultstatus)
90 ENTRY(cpufunc_faultaddress)
91 mrc p15, 0, r0, c6, c0, 0
93 END(cpufunc_faultaddress)
96 * Generic functions to write the internal coprocessor registers
99 * Currently these registers are
101 * c3 - Domain Access Control
103 * All other registers are CPU architecture specific
106 #if 0 /* See below. */
107 ENTRY(cpufunc_control)
108 mcr p15, 0, r0, c1, c0, 0
113 ENTRY(cpufunc_domains)
114 mcr p15, 0, r0, c3, c0, 0
119 * Generic functions to read/modify/write the internal coprocessor registers
122 * Currently these registers are
125 * All other registers are CPU architecture specific
128 ENTRY(cpufunc_control)
129 mrc p15, 0, r3, c1, c0, 0 /* Read the control register */
130 bic r2, r3, r0 /* Clear bits */
131 eor r2, r2, r1 /* XOR bits */
134 teq r2, r3 /* Only write if there is a change */
135 mcrne p15, 0, r2, c1, c0, 0 /* Write new control register */
136 mov r0, r3 /* Return old value */
145 * other potentially useful software functions are:
146 * clean D cache entry and flush I cache entry
147 * for the moment use cache_purgeID_E
150 /* Random odd functions */
153 * Function to get the offset of a stored program counter from the
154 * instruction doing the store. This offset is defined to be the same
155 * for all STRs and STMs on a given implementation. Code based on
156 * section 2.4.3 of the ARM ARM (2nd Ed.), with modifications to work
157 * in 26-bit modes as well.
159 ENTRY(get_pc_str_offset)
161 stmfd sp!, {fp, ip, lr, pc}
164 mov r1, pc /* R1 = addr of following STR */
166 str pc, [sp] /* [SP] = . + offset */
169 ldmdb fp, {fp, sp, pc}
170 END(get_pc_str_offset)
172 /* Allocate and lock a cacheline for the specified address. */
174 #define CPWAIT_BRANCH \
177 mrc p15, 0, r2, c2, c0, 0; \
181 ENTRY(arm_lock_cache_line)
182 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
184 mcr p15, 0, r1, c9, c2, 0 /* Enable data cache lock mode */
186 mcr p15, 0, r0, c7, c2, 5 /* Allocate the cache line */
187 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
190 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
191 mcr p15, 0, r1, c9, c2, 0 /* Disable data cache lock mode */
194 END(arm_lock_cache_line)