1 /* $NetBSD: cpufunc_asm.S,v 1.12 2003/09/06 09:14:52 rearnsha Exp $ */
4 * Copyright (c) 1997,1998 Mark Brinicombe.
5 * Copyright (c) 1997 Causality Limited
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Causality Limited.
19 * 4. The name of Causality Limited may not be used to endorse or promote
20 * products derived from this software without specific prior written
23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * RiscBSD kernel project
39 * Assembly functions for CPU / MMU / TLB specific operations
45 #include <machine/asm.h>
46 __FBSDID("$FreeBSD$");
56 * Generic functions to write the internal coprocessor registers
58 * Currently these registers are
60 * c3 - Domain Access Control
62 * All other registers are CPU architecture specific
66 mcr p15, 0, r0, c3, c0, 0
71 * Generic functions to read/modify/write the internal coprocessor registers
74 * Currently these registers are
77 * All other registers are CPU architecture specific
80 ENTRY(cpufunc_control)
81 mrc CP15_SCTLR(r3) /* Read the control register */
82 bic r2, r3, r0 /* Clear bits */
83 eor r2, r2, r1 /* XOR bits */
86 teq r2, r3 /* Only write if there is a change */
87 mcrne CP15_SCTLR(r2) /* Write new control register */
88 mov r0, r3 /* Return old value */
94 * other potentially useful software functions are:
95 * clean D cache entry and flush I cache entry
96 * for the moment use cache_purgeID_E
99 /* Random odd functions */
101 /* Allocate and lock a cacheline for the specified address. */
103 #define CPWAIT_BRANCH \
106 mrc p15, 0, r2, c2, c0, 0; \
110 ENTRY(arm_lock_cache_line)
111 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
113 mcr p15, 0, r1, c9, c2, 0 /* Enable data cache lock mode */
115 mcr p15, 0, r0, c7, c2, 5 /* Allocate the cache line */
116 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
119 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
120 mcr p15, 0, r1, c9, c2, 0 /* Disable data cache lock mode */
123 END(arm_lock_cache_line)