1 /* $NetBSD: cpufunc_asm_arm10.S,v 1.1 2003/09/06 09:12:29 rearnsha Exp $ */
4 * Copyright (c) 2002 ARM Limited
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19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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31 * ARM10 assembly functions for CPU / MMU / TLB specific operations
35 #include <machine/asm.h>
36 __FBSDID("$FreeBSD$");
39 * Functions to set the MMU Translation Table Base register
41 * We need to clean and flush the cache as it uses virtual
42 * addresses that are about to change.
46 bl _C_LABEL(arm10_idcache_wbinv_all)
49 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
51 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
58 ENTRY(arm10_tlb_flushID_SE)
59 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
60 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
62 END(arm10_tlb_flushID_SE)
64 ENTRY(arm10_tlb_flushI_SE)
65 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
67 END(arm10_tlb_flushI_SE)
70 * Cache operations. For the entire cache we use the set/index
78 ENTRY_NP(arm10_icache_sync_range)
79 ldr ip, .Larm10_line_size
81 bcs .Larm10_icache_sync_all
88 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
89 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
93 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
95 END(arm10_icache_sync_range)
97 ENTRY_NP(arm10_icache_sync_all)
98 .Larm10_icache_sync_all:
100 * We assume that the code here can never be out of sync with the
101 * dcache, so that we can safely flush the Icache and fall through
102 * into the Dcache cleaning code.
104 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
105 /* Fall through to clean Dcache. */
108 ldr ip, .Larm10_cache_data
109 ldmia ip, {s_max, i_max, s_inc, i_inc}
113 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
115 bhs .Lnext_index /* Next index */
116 subs s_max, s_max, s_inc
117 bhs .Lnext_set /* Next set */
118 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
120 END(arm10_icache_sync_all)
123 .word _C_LABEL(arm_pdcache_line_size)
125 ENTRY(arm10_dcache_wb_range)
126 ldr ip, .Larm10_line_size
128 bcs .Larm10_dcache_wb
135 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
139 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
141 END(arm10_dcache_wb_range)
143 ENTRY(arm10_dcache_wbinv_range)
144 ldr ip, .Larm10_line_size
146 bcs .Larm10_dcache_wbinv_all
153 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
156 bhi .Larm10_wbinv_next
157 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
159 END(arm10_dcache_wbinv_range)
162 * Note, we must not invalidate everything. If the range is too big we
163 * must use wb-inv of the entire cache.
165 ENTRY(arm10_dcache_inv_range)
166 ldr ip, .Larm10_line_size
168 bcs .Larm10_dcache_wbinv_all
175 mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */
179 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
181 END(arm10_dcache_inv_range)
183 ENTRY(arm10_idcache_wbinv_range)
184 ldr ip, .Larm10_line_size
186 bcs .Larm10_idcache_wbinv_all
192 .Larm10_id_wbinv_next:
193 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
194 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
197 bhi .Larm10_id_wbinv_next
198 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
200 END(arm10_idcache_wbinv_range)
202 ENTRY_NP(arm10_idcache_wbinv_all)
203 .Larm10_idcache_wbinv_all:
205 * We assume that the code here can never be out of sync with the
206 * dcache, so that we can safely flush the Icache and fall through
207 * into the Dcache purging code.
209 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
210 /* Fall through to purge Dcache. */
212 EENTRY(arm10_dcache_wbinv_all)
213 .Larm10_dcache_wbinv_all:
214 ldr ip, .Larm10_cache_data
215 ldmia ip, {s_max, i_max, s_inc, i_inc}
219 mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
221 bhs .Lnext_index_inv /* Next index */
222 subs s_max, s_max, s_inc
223 bhs .Lnext_set_inv /* Next set */
224 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
226 EEND(arm10_dcache_wbinv_all)
227 END(arm10_idcache_wbinv_all)
230 .word _C_LABEL(arm10_dcache_sets_max)
235 * These is the CPU-specific parts of the context switcher cpu_switch()
236 * These functions actually perform the TTB reload.
238 * NOTE: Special calling convention
239 * r1, r4-r13 must be preserved
241 ENTRY(arm10_context_switch)
243 * We can assume that the caches will only contain kernel addresses
244 * at this point. So no need to flush them again.
246 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
247 mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */
248 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
250 /* Paranoia -- make sure the pipeline is empty. */
255 END(arm10_context_switch)
259 /* XXX The following macros should probably be moved to asm.h */
260 #define _DATA_OBJECT(x) .globl x; .type x,_ASM_TYPE_OBJECT; x:
261 #define C_OBJECT(x) _DATA_OBJECT(_C_LABEL(x))
264 * Parameters for the cache cleaning code. Note that the order of these
265 * four variables is assumed in the code above. Hence the reason for
266 * declaring them in the assembler file.
269 C_OBJECT(arm10_dcache_sets_max)
271 C_OBJECT(arm10_dcache_index_max)
273 C_OBJECT(arm10_dcache_sets_inc)
275 C_OBJECT(arm10_dcache_index_inc)