1 /* $NetBSD: cpufunc_asm_arm11.S,v 1.2 2005/12/11 12:16:41 christos Exp $ */
4 * Copyright (c) 2002, 2005 ARM Limited
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19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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31 * ARM11 assembly functions for CPU / MMU / TLB specific operations
33 * XXX We make no attempt at present to take advantage of the v6 memroy
34 * architecture or physically tagged cache.
37 #include <machine/asm.h>
38 __FBSDID("$FreeBSD$");
41 * Functions to set the MMU Translation Table Base register
43 * We need to clean and flush the cache as it uses virtual
44 * addresses that are about to change.
47 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
49 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
50 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
57 ENTRY(arm11_tlb_flushID_SE)
58 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
59 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
60 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
62 END(arm11_tlb_flushID_SE)
64 ENTRY(arm11_tlb_flushI_SE)
65 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
66 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
68 END(arm11_tlb_flushI_SE)
73 * These is the CPU-specific parts of the context switcher cpu_switch()
74 * These functions actually perform the TTB reload.
76 * NOTE: Special calling convention
77 * r1, r4-r13 must be preserved
79 ENTRY(arm11_context_switch)
81 * We can assume that the caches will only contain kernel addresses
82 * at this point. So no need to flush them again.
84 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
85 mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */
86 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
88 /* Paranoia -- make sure the pipeline is empty. */
93 END(arm11_context_switch)
98 ENTRY(arm11_tlb_flushID)
99 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
100 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
102 END(arm11_tlb_flushID)
104 ENTRY(arm11_tlb_flushI)
105 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
106 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
108 END(arm11_tlb_flushI)
110 ENTRY(arm11_tlb_flushD)
111 mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */
112 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
114 END(arm11_tlb_flushD)
116 ENTRY(arm11_tlb_flushD_SE)
117 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
118 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
120 END(arm11_tlb_flushD_SE)
125 ENTRY(arm11_drain_writebuf)
126 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
128 END(arm11_drain_writebuf)
130 ENTRY_NP(arm11_sleep)
132 mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */