1 /* $NetBSD: cpufunc_asm_arm11.S,v 1.2 2005/12/11 12:16:41 christos Exp $ */
4 * Copyright (c) 2002, 2005 ARM Limited
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the company may not be used to endorse or promote
16 * products derived from this software without specific prior written
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * ARM11 assembly functions for CPU / MMU / TLB specific operations
33 * XXX We make no attempt at present to take advantage of the v6 memroy
34 * architecture or physically tagged cache.
37 #include <machine/asm.h>
38 __FBSDID("$FreeBSD$");
43 ENTRY(arm11_tlb_flushID_SE)
44 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
45 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
46 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
48 END(arm11_tlb_flushID_SE)
53 * These is the CPU-specific parts of the context switcher cpu_switch()
54 * These functions actually perform the TTB reload.
56 * NOTE: Special calling convention
57 * r1, r4-r13 must be preserved
59 ENTRY(arm11_context_switch)
61 * We can assume that the caches will only contain kernel addresses
62 * at this point. So no need to flush them again.
64 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
65 mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */
66 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
68 /* Paranoia -- make sure the pipeline is empty. */
73 END(arm11_context_switch)
78 ENTRY(arm11_tlb_flushID)
79 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
80 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
82 END(arm11_tlb_flushID)
84 ENTRY(arm11_tlb_flushD)
85 mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */
86 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
90 ENTRY(arm11_tlb_flushD_SE)
91 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
92 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
94 END(arm11_tlb_flushD_SE)
99 ENTRY(arm11_drain_writebuf)
100 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
102 END(arm11_drain_writebuf)