1 /* $NetBSD: cpufunc_asm_arm11x6.S,v 1.1 2012/07/21 12:19:15 skrll Exp $ */
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40 * modification, are permitted provided that the following conditions
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62 #include <machine/asm.h>
63 __FBSDID("$FreeBSD$");
68 #define Invalidate_I_cache(Rtmp1, Rtmp2) \
69 mcr p15, 0, Rtmp1, c7, c5, 0 /* Invalidate Entire I cache */
74 * Erratum 411920 in ARM1136 (fixed in r1p4)
75 * Erratum 415045 in ARM1176 (fixed in r0p5?)
77 * - value of arg 'reg' Should Be Zero
79 #define Invalidate_I_cache(Rtmp1, Rtmp2) \
80 mov Rtmp1, #0; /* SBZ */ \
83 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
84 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
85 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
86 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
102 #define Flush_D_cache(reg) \
103 mov reg, #0; /* SBZ */ \
104 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
105 mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */
107 #define Flush_D_cache(reg) \
108 1: mov reg, #0; /* SBZ */ \
109 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
110 mrc p15, 0, reg, C7, C10, 6;/* Read Cache Dirty Status Register */ \
111 ands reg, reg, #01; /* Check if it is clean */ \
112 bne 1b; /* loop if not */ \
113 mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */
116 ENTRY(arm11x6_setttb)
118 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
119 mcr p15, 0, r1, c8, c7, 0 /* invalidate I+D TLBs */
120 mcr p15, 0, r1, c7, c10, 4 /* drain write buffer */
124 ENTRY_NP(arm11x6_idcache_wbinv_all)
126 Invalidate_I_cache(r0, r1)
128 END(arm11x6_idcache_wbinv_all)
130 ENTRY_NP(arm11x6_dcache_wbinv_all)
133 END(arm11x6_dcache_wbinv_all)
135 ENTRY_NP(arm11x6_icache_sync_all)
137 Invalidate_I_cache(r0, r1)
139 END(arm11x6_icache_sync_all)
141 ENTRY_NP(arm11x6_flush_prefetchbuf)
142 mcr p15, 0, r0, c7, c5, 4 /* Flush Prefetch Buffer */
144 END(arm11x6_flush_prefetchbuf)
146 ENTRY_NP(arm11x6_icache_sync_range)
149 /* Erratum ARM1136 371025, workaround #2 */
150 /* Erratum ARM1176 371367 */
151 mrs r2, cpsr /* save the CPSR */
152 cpsid ifa /* disable interrupts (irq,fiq,abort) */
154 mcr p15, 0, r3, c13, c0, 0 /* write FCSE (uTLB invalidate) */
155 mcr p15, 0, r3, c7, c5, 4 /* flush prefetch buffer */
157 mcr p15, 0, r3, c7, c13, 1 /* prefetch I-cache line */
158 mcrr p15, 0, r1, r0, c5 /* invalidate I-cache range */
159 msr cpsr_cx, r2 /* local_irq_restore */
168 mcrr p15, 0, r1, r0, c12 /* clean and invalidate D cache range */ /* XXXNH */
169 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
171 END(arm11x6_icache_sync_range)
173 ENTRY_NP(arm11x6_idcache_wbinv_range)
176 /* Erratum ARM1136 371025, workaround #2 */
177 /* Erratum ARM1176 371367 */
178 mrs r2, cpsr /* save the CPSR */
179 cpsid ifa /* disable interrupts (irq,fiq,abort) */
181 mcr p15, 0, r3, c13, c0, 0 /* write FCSE (uTLB invalidate) */
182 mcr p15, 0, r3, c7, c5, 4 /* flush prefetch buffer */
184 mcr p15, 0, r3, c7, c13, 1 /* prefetch I-cache line */
185 mcrr p15, 0, r1, r0, c5 /* invalidate I-cache range */
186 msr cpsr_cx, r2 /* local_irq_restore */
195 mcrr p15, 0, r1, r0, c14 /* clean and invalidate D cache range */
196 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
198 END(arm11x6_idcache_wbinv_range)
201 * Preload the cache before issuing the WFI by conditionally disabling the
202 * mcr intstructions the first time around the loop. Ensure the function is
208 ENTRY_NP(arm11x6_sleep)
214 mcreq p15, 0, r0, c7, c10, 4 /* data sync barrier */
215 mcreq p15, 0, r0, c7, c0, 4 /* wait for interrupt */