1 /* $NetBSD: cpufunc_asm_arm8.S,v 1.2 2001/11/11 00:47:49 thorpej Exp $ */
4 * Copyright (c) 1997 ARM Limited
5 * Copyright (c) 1997 Causality Limited
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35 * ARM8 assembly functions for CPU / MMU / TLB specific operations
39 #include <machine/asm.h>
40 __FBSDID("$FreeBSD$");
42 ENTRY(arm8_clock_config)
43 mrc p15, 0, r3, c15, c0, 0 /* Read the clock register */
44 bic r2, r3, #0x11 /* turn off dynamic clocking
46 mcr p15, 0, r2, c15, c0, 0 /* Write clock register */
48 bic r2, r3, r0 /* Clear bits */
49 eor r2, r2, r1 /* XOR bits */
50 bic r2, r2, #0x10 /* clear the L bit */
52 bic r1, r2, #0x01 /* still keep dynamic clocking off */
53 mcr p15, 0, r1, c15, c0, 0 /* Write clock register */
58 mcr p15, 0, r2, c15, c0, 0 /* Write clock register */
59 mov r0, r3 /* Return old value */
63 * Functions to set the MMU Translation Table Base register
65 * We need to clean and flush the cache as it uses virtual
66 * addresses that are about to change.
70 orr r1, r3, #(I32_bit | F32_bit)
73 stmfd sp!, {r0-r3, lr}
74 bl _C_LABEL(arm8_cache_cleanID)
75 ldmfd sp!, {r0-r3, lr}
76 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
79 mcr p15, 0, r0, c2, c0, 0
81 /* If we have updated the TTB we must flush the TLB */
82 mcr p15, 0, r0, c8, c7, 0
84 /* For good measure we will flush the IDC as well */
85 mcr p15, 0, r0, c7, c7, 0
87 /* Make sure that pipeline is emptied */
97 ENTRY(arm8_tlb_flushID)
98 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
101 ENTRY(arm8_tlb_flushID_SE)
102 mcr p15, 0, r0, c8, c7, 1 /* flush I+D tlb single entry */
108 ENTRY(arm8_cache_flushID)
109 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
112 ENTRY(arm8_cache_flushID_E)
113 mcr p15, 0, r0, c7, c7, 1 /* flush I+D single entry */
116 ENTRY(arm8_cache_cleanID)
120 mcr p15, 0, r2, c7, c11, 1
122 mcr p15, 0, r2, c7, c11, 1
124 mcr p15, 0, r2, c7, c11, 1
126 mcr p15, 0, r2, c7, c11, 1
128 mcr p15, 0, r2, c7, c11, 1
130 mcr p15, 0, r2, c7, c11, 1
132 mcr p15, 0, r2, c7, c11, 1
134 mcr p15, 0, r2, c7, c11, 1
136 mcr p15, 0, r2, c7, c11, 1
138 mcr p15, 0, r2, c7, c11, 1
140 mcr p15, 0, r2, c7, c11, 1
142 mcr p15, 0, r2, c7, c11, 1
144 mcr p15, 0, r2, c7, c11, 1
146 mcr p15, 0, r2, c7, c11, 1
148 mcr p15, 0, r2, c7, c11, 1
150 mcr p15, 0, r2, c7, c11, 1
152 adds r0, r0, #0x04000000
157 ENTRY(arm8_cache_cleanID_E)
158 mcr p15, 0, r0, c7, c11, 1 /* clean I+D single entry */
161 ENTRY(arm8_cache_purgeID)
165 * Clean and invalidate entry will not invalidate the entry
166 * if the line was already clean. (mcr p15, 0, rd, c7, 15, 1)
168 * Instead of using the clean and invalidate entry operation
169 * use a separate clean and invalidate entry operations.
171 * mcr p15, 0, rd, c7, c11, 1
172 * mcr p15, 0, rd, c7, c7, 1
178 orr r2, r3, #(I32_bit | F32_bit)
182 mcr p15, 0, r2, c7, c11, 1
183 mcr p15, 0, r2, c7, c7, 1
185 mcr p15, 0, r2, c7, c11, 1
186 mcr p15, 0, r2, c7, c7, 1
188 mcr p15, 0, r2, c7, c11, 1
189 mcr p15, 0, r2, c7, c7, 1
191 mcr p15, 0, r2, c7, c11, 1
192 mcr p15, 0, r2, c7, c7, 1
194 mcr p15, 0, r2, c7, c11, 1
195 mcr p15, 0, r2, c7, c7, 1
197 mcr p15, 0, r2, c7, c11, 1
198 mcr p15, 0, r2, c7, c7, 1
200 mcr p15, 0, r2, c7, c11, 1
201 mcr p15, 0, r2, c7, c7, 1
203 mcr p15, 0, r2, c7, c11, 1
204 mcr p15, 0, r2, c7, c7, 1
206 mcr p15, 0, r2, c7, c11, 1
207 mcr p15, 0, r2, c7, c7, 1
209 mcr p15, 0, r2, c7, c11, 1
210 mcr p15, 0, r2, c7, c7, 1
212 mcr p15, 0, r2, c7, c11, 1
213 mcr p15, 0, r2, c7, c7, 1
215 mcr p15, 0, r2, c7, c11, 1
216 mcr p15, 0, r2, c7, c7, 1
218 mcr p15, 0, r2, c7, c11, 1
219 mcr p15, 0, r2, c7, c7, 1
221 mcr p15, 0, r2, c7, c11, 1
222 mcr p15, 0, r2, c7, c7, 1
224 mcr p15, 0, r2, c7, c11, 1
225 mcr p15, 0, r2, c7, c7, 1
227 mcr p15, 0, r2, c7, c11, 1
228 mcr p15, 0, r2, c7, c7, 1
230 adds r0, r0, #0x04000000
236 ENTRY(arm8_cache_purgeID_E)
240 * Clean and invalidate entry will not invalidate the entry
241 * if the line was already clean. (mcr p15, 0, rd, c7, 15, 1)
243 * Instead of using the clean and invalidate entry operation
244 * use a separate clean and invalidate entry operations.
246 * mcr p15, 0, rd, c7, c11, 1
247 * mcr p15, 0, rd, c7, c7, 1
250 orr r2, r3, #(I32_bit | F32_bit)
252 mcr p15, 0, r0, c7, c11, 1 /* clean I+D single entry */
253 mcr p15, 0, r0, c7, c7, 1 /* flush I+D single entry */
260 * These is the CPU-specific parts of the context switcher cpu_switch()
261 * These functions actually perform the TTB reload.
263 * NOTE: Special calling convention
264 * r1, r4-r13 must be preserved
266 ENTRY(arm8_context_switch)
267 /* For good measure we will flush the IDC as well */
268 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
271 mcr p15, 0, r0, c2, c0, 0
273 /* If we have updated the TTB we must flush the TLB */
274 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
277 /* For good measure we will flush the IDC as well */
278 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
281 /* Make sure that pipeline is emptied */