1 /* $NetBSD: cpufunc_asm_arm9.S,v 1.3 2004/01/26 15:54:16 rearnsha Exp $ */
4 * Copyright (c) 2001, 2004 ARM Limited
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31 * ARM9 assembly functions for CPU / MMU / TLB specific operations
34 #include <machine/asm.h>
35 __FBSDID("$FreeBSD$");
38 * Functions to set the MMU Translation Table Base register
40 * We need to clean and flush the cache as it uses virtual
41 * addresses that are about to change.
45 bl _C_LABEL(arm9_idcache_wbinv_all)
48 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
50 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
56 ENTRY(arm9_tlb_flushID_SE)
57 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
58 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
62 * Cache operations. For the entire cache we use the set/index
70 ENTRY_NP(arm9_icache_sync_range)
71 ldr ip, .Larm9_line_size
73 bcs .Larm9_icache_sync_all
80 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
81 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
87 ENTRY_NP(arm9_icache_sync_all)
88 .Larm9_icache_sync_all:
90 * We assume that the code here can never be out of sync with the
91 * dcache, so that we can safely flush the Icache and fall through
92 * into the Dcache cleaning code.
94 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
95 /* Fall through to clean Dcache. */
98 ldr ip, .Larm9_cache_data
99 ldmia ip, {s_max, i_max, s_inc, i_inc}
103 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
105 tst ip, i_max /* Index 0 is last one */
106 bne .Lnext_index /* Next index */
107 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
108 subs s_max, s_max, s_inc
109 bpl .Lnext_set /* Next set */
113 .word _C_LABEL(arm_pdcache_line_size)
115 ENTRY(arm9_dcache_wb_range)
116 ldr ip, .Larm9_line_size
125 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
131 ENTRY(arm9_dcache_wbinv_range)
132 ldr ip, .Larm9_line_size
134 bcs .Larm9_dcache_wbinv_all
141 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
144 bpl .Larm9_wbinv_next
148 * Note, we must not invalidate everything. If the range is too big we
149 * must use wb-inv of the entire cache.
151 ENTRY(arm9_dcache_inv_range)
152 ldr ip, .Larm9_line_size
154 bcs .Larm9_dcache_wbinv_all
161 mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */
167 ENTRY(arm9_idcache_wbinv_range)
168 ldr ip, .Larm9_line_size
170 bcs .Larm9_idcache_wbinv_all
176 .Larm9_id_wbinv_next:
177 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
178 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
181 bpl .Larm9_id_wbinv_next
184 ENTRY_NP(arm9_idcache_wbinv_all)
185 .Larm9_idcache_wbinv_all:
187 * We assume that the code here can never be out of sync with the
188 * dcache, so that we can safely flush the Icache and fall through
189 * into the Dcache purging code.
191 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
194 ENTRY(arm9_dcache_wbinv_all)
195 .Larm9_dcache_wbinv_all:
196 ldr ip, .Larm9_cache_data
197 ldmia ip, {s_max, i_max, s_inc, i_inc}
201 mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
203 tst ip, i_max /* Index 0 is last one */
204 bne .Lnext_index_inv /* Next index */
205 mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
206 subs s_max, s_max, s_inc
207 bpl .Lnext_set_inv /* Next set */
211 .word _C_LABEL(arm9_dcache_sets_max)
216 * These is the CPU-specific parts of the context switcher cpu_switch()
217 * These functions actually perform the TTB reload.
219 * NOTE: Special calling convention
220 * r1, r4-r13 must be preserved
222 ENTRY(arm9_context_switch)
224 * We can assume that the caches will only contain kernel addresses
225 * at this point. So no need to flush them again.
227 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
228 mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */
229 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
231 /* Paranoia -- make sure the pipeline is empty. */
239 /* XXX The following macros should probably be moved to asm.h */
240 #define _DATA_OBJECT(x) .globl x; .type x,_ASM_TYPE_OBJECT; x:
241 #define C_OBJECT(x) _DATA_OBJECT(_C_LABEL(x))
244 * Parameters for the cache cleaning code. Note that the order of these
245 * four variables is assumed in the code above. Hence the reason for
246 * declaring them in the assembler file.
249 C_OBJECT(arm9_dcache_sets_max)
251 C_OBJECT(arm9_dcache_index_max)
253 C_OBJECT(arm9_dcache_sets_inc)
255 C_OBJECT(arm9_dcache_index_inc)