1 /* $NetBSD: cpufunc_asm_arm9.S,v 1.3 2004/01/26 15:54:16 rearnsha Exp $ */
4 * Copyright (c) 2001, 2004 ARM Limited
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31 * ARM9 assembly functions for CPU / MMU / TLB specific operations
34 #include <machine/asm.h>
35 __FBSDID("$FreeBSD$");
38 * Functions to set the MMU Translation Table Base register
40 * We need to clean and flush the cache as it uses virtual
41 * addresses that are about to change.
45 bl _C_LABEL(arm9_idcache_wbinv_all)
48 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
50 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
57 ENTRY(arm9_tlb_flushID_SE)
58 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
59 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
61 END(arm9_tlb_flushID_SE)
64 * Cache operations. For the entire cache we use the set/index
72 ENTRY_NP(arm9_icache_sync_range)
73 ldr ip, .Larm9_line_size
75 bcs .Larm9_icache_sync_all
82 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
83 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
88 END(arm9_icache_sync_range)
90 ENTRY_NP(arm9_icache_sync_all)
91 .Larm9_icache_sync_all:
93 * We assume that the code here can never be out of sync with the
94 * dcache, so that we can safely flush the Icache and fall through
95 * into the Dcache cleaning code.
97 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
98 /* Fall through to clean Dcache. */
101 ldr ip, .Larm9_cache_data
102 ldmia ip, {s_max, i_max, s_inc, i_inc}
106 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
108 bhs .Lnext_index /* Next index */
109 subs s_max, s_max, s_inc
110 bhs .Lnext_set /* Next set */
112 END(arm9_icache_sync_all)
115 .word _C_LABEL(arm_pdcache_line_size)
117 ENTRY(arm9_dcache_wb_range)
118 ldr ip, .Larm9_line_size
127 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
132 END(arm9_dcache_wb_range)
134 ENTRY(arm9_dcache_wbinv_range)
135 ldr ip, .Larm9_line_size
137 bcs .Larm9_dcache_wbinv_all
144 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
147 bhi .Larm9_wbinv_next
149 END(arm9_dcache_wbinv_range)
152 * Note, we must not invalidate everything. If the range is too big we
153 * must use wb-inv of the entire cache.
155 ENTRY(arm9_dcache_inv_range)
156 ldr ip, .Larm9_line_size
158 bcs .Larm9_dcache_wbinv_all
165 mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */
170 END(arm9_dcache_inv_range)
172 ENTRY(arm9_idcache_wbinv_range)
173 ldr ip, .Larm9_line_size
175 bcs .Larm9_idcache_wbinv_all
181 .Larm9_id_wbinv_next:
182 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
183 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
186 bhi .Larm9_id_wbinv_next
188 END(arm9_idcache_wbinv_range)
190 ENTRY_NP(arm9_idcache_wbinv_all)
191 .Larm9_idcache_wbinv_all:
193 * We assume that the code here can never be out of sync with the
194 * dcache, so that we can safely flush the Icache and fall through
195 * into the Dcache purging code.
197 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
200 EENTRY(arm9_dcache_wbinv_all)
201 .Larm9_dcache_wbinv_all:
202 ldr ip, .Larm9_cache_data
203 ldmia ip, {s_max, i_max, s_inc, i_inc}
207 mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
209 bhs .Lnext_index_inv /* Next index */
210 subs s_max, s_max, s_inc
211 bhs .Lnext_set_inv /* Next set */
213 EEND(arm9_dcache_wbinv_all)
214 END(arm9_idcache_wbinv_all)
217 .word _C_LABEL(arm9_dcache_sets_max)
222 * These is the CPU-specific parts of the context switcher cpu_switch()
223 * These functions actually perform the TTB reload.
225 * NOTE: Special calling convention
226 * r1, r4-r13 must be preserved
228 ENTRY(arm9_context_switch)
230 * We can assume that the caches will only contain kernel addresses
231 * at this point. So no need to flush them again.
233 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
234 mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */
235 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
237 /* Paranoia -- make sure the pipeline is empty. */
242 END(arm9_context_switch)
246 /* XXX The following macros should probably be moved to asm.h */
247 #define _DATA_OBJECT(x) .globl x; .type x,_ASM_TYPE_OBJECT; x:
248 #define C_OBJECT(x) _DATA_OBJECT(_C_LABEL(x))
251 * Parameters for the cache cleaning code. Note that the order of these
252 * four variables is assumed in the code above. Hence the reason for
253 * declaring them in the assembler file.
256 C_OBJECT(arm9_dcache_sets_max)
258 C_OBJECT(arm9_dcache_index_max)
260 C_OBJECT(arm9_dcache_sets_inc)
262 C_OBJECT(arm9_dcache_index_inc)