1 /* $NetBSD: cpufunc_asm_armv5_ec.S,v 1.1 2007/01/06 00:50:54 christos Exp $ */
4 * Copyright (c) 2002, 2005 ARM Limited
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31 * ARMv5 assembly functions for manipulating caches.
32 * These routines can be used by any core that supports both the set/index
33 * operations and the test and clean operations for efficiently cleaning the
34 * entire DCache. If a core does not have the test and clean operations, but
35 * does have the set/index operations, use the routines in cpufunc_asm_armv5.S.
36 * This source was derived from that file.
39 #include <machine/asm.h>
40 __FBSDID("$FreeBSD$");
43 * Functions to set the MMU Translation Table Base register
45 * We need to clean and flush the cache as it uses virtual
46 * addresses that are about to change.
48 ENTRY(armv5_ec_setttb)
50 * Some other ARM ports save registers on the stack, call the
51 * idcache_wbinv_all function and then restore the registers from the
52 * stack before setting the TTB. I observed that this caused a
53 * problem when the old and new translation table entries' buffering
54 * bits were different. If I saved the registers in other registers
55 * or invalidated the caches when I returned from idcache_wbinv_all,
56 * it worked fine. If not, I ended up executing at an invalid PC.
57 * For armv5_ec_settb, the idcache_wbinv_all is simple enough, I just
58 * do it directly and entirely avoid the problem.
60 mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */
61 1: mrc p15, 0, r15, c7, c14, 3 /* Test, clean and invalidate DCache */
62 bne 1b /* More to do? */
63 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
65 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
67 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
72 * Cache operations. For the entire cache we use the enhanced cache
76 ENTRY_NP(armv5_ec_icache_sync_range)
77 ldr ip, .Larmv5_ec_line_size
79 bcs .Larmv5_ec_icache_sync_all
81 sub r1, r1, #1 /* Don't overrun */
87 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
88 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
92 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
94 END(armv5_ec_icache_sync_range)
96 ENTRY_NP(armv5_ec_icache_sync_all)
97 .Larmv5_ec_icache_sync_all:
99 * We assume that the code here can never be out of sync with the
100 * dcache, so that we can safely flush the Icache and fall through
101 * into the Dcache cleaning code.
103 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
104 /* Fall through to clean Dcache. */
106 .Larmv5_ec_dcache_wb:
108 mrc p15, 0, r15, c7, c10, 3 /* Test and clean (don't invalidate) */
109 bne 1b /* More to do? */
110 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
112 END(armv5_ec_icache_sync_all)
114 .Larmv5_ec_line_size:
115 .word _C_LABEL(arm_pdcache_line_size)
117 ENTRY(armv5_ec_dcache_wb_range)
118 ldr ip, .Larmv5_ec_line_size
120 bcs .Larmv5_ec_dcache_wb
122 sub r1, r1, #1 /* Don't overrun */
128 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
132 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
134 END(armv5_ec_dcache_wb_range)
136 ENTRY(armv5_ec_dcache_wbinv_range)
137 ldr ip, .Larmv5_ec_line_size
139 bcs .Larmv5_ec_dcache_wbinv_all
141 sub r1, r1, #1 /* Don't overrun */
147 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
151 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
153 END(armv5_ec_dcache_wbinv_range)
156 * Note, we must not invalidate everything. If the range is too big we
157 * must use wb-inv of the entire cache.
159 ENTRY(armv5_ec_dcache_inv_range)
160 ldr ip, .Larmv5_ec_line_size
162 bcs .Larmv5_ec_dcache_wbinv_all
164 sub r1, r1, #1 /* Don't overrun */
170 mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */
174 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
176 END(armv5_ec_dcache_inv_range)
178 ENTRY(armv5_ec_idcache_wbinv_range)
179 ldr ip, .Larmv5_ec_line_size
181 bcs .Larmv5_ec_idcache_wbinv_all
183 sub r1, r1, #1 /* Don't overrun */
189 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
190 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
194 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
196 END(armv5_ec_idcache_wbinv_range)
198 ENTRY_NP(armv5_ec_idcache_wbinv_all)
199 .Larmv5_ec_idcache_wbinv_all:
201 * We assume that the code here can never be out of sync with the
202 * dcache, so that we can safely flush the Icache and fall through
203 * into the Dcache purging code.
205 mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */
206 /* Fall through to purge Dcache. */
207 END(armv5_ec_idcache_wbinv_all)
209 ENTRY(armv5_ec_dcache_wbinv_all)
210 .Larmv5_ec_dcache_wbinv_all:
211 1: mrc p15, 0, r15, c7, c14, 3 /* Test, clean and invalidate DCache */
212 bne 1b /* More to do? */
213 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
215 END(armv5_ec_dcache_wbinv_all)