1 /* $NetBSD: cpufunc_asm_armv5_ec.S,v 1.1 2007/01/06 00:50:54 christos Exp $ */
4 * Copyright (c) 2002, 2005 ARM Limited
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19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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31 * ARMv5 assembly functions for manipulating caches.
32 * These routines can be used by any core that supports both the set/index
33 * operations and the test and clean operations for efficiently cleaning the
34 * entire DCache. If a core does not have the test and clean operations, but
35 * does have the set/index operations, use the routines in cpufunc_asm_armv5.S.
36 * This source was derived from that file.
39 #include <machine/asm.h>
40 __FBSDID("$FreeBSD$");
42 #ifndef ELF_TRAMPOLINE
44 * Functions to set the MMU Translation Table Base register
46 * We need to clean and flush the cache as it uses virtual
47 * addresses that are about to change.
49 ENTRY(armv5_ec_setttb)
51 * Some other ARM ports save registers on the stack, call the
52 * idcache_wbinv_all function and then restore the registers from the
53 * stack before setting the TTB. I observed that this caused a
54 * problem when the old and new translation table entries' buffering
55 * bits were different. If I saved the registers in other registers
56 * or invalidated the caches when I returned from idcache_wbinv_all,
57 * it worked fine. If not, I ended up executing at an invalid PC.
58 * For armv5_ec_settb, the idcache_wbinv_all is simple enough, I just
59 * do it directly and entirely avoid the problem.
61 mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */
62 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 /* Test, clean and invalidate DCache */
63 bne 1b /* More to do? */
64 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
66 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
68 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
73 * Cache operations. For the entire cache we use the enhanced cache
77 ENTRY_NP(armv5_ec_icache_sync_range)
78 ldr ip, .Larmv5_ec_line_size
80 bcs .Larmv5_ec_icache_sync_all
82 sub r1, r1, #1 /* Don't overrun */
88 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
89 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
93 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
96 .Larmv5_ec_icache_sync_all:
98 * We assume that the code here can never be out of sync with the
99 * dcache, so that we can safely flush the Icache and fall through
100 * into the Dcache cleaning code.
102 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
103 /* Fall through to clean Dcache. */
105 .Larmv5_ec_dcache_wb:
107 mrc p15, 0, APSR_nzcv, c7, c10, 3 /* Test and clean (don't invalidate) */
108 bne 1b /* More to do? */
109 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
111 END(armv5_ec_icache_sync_range)
113 .Larmv5_ec_line_size:
114 .word _C_LABEL(arm_pdcache_line_size)
116 ENTRY(armv5_ec_dcache_wb_range)
117 ldr ip, .Larmv5_ec_line_size
119 bcs .Larmv5_ec_dcache_wb
121 sub r1, r1, #1 /* Don't overrun */
127 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
131 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
133 END(armv5_ec_dcache_wb_range)
135 ENTRY(armv5_ec_dcache_wbinv_range)
136 ldr ip, .Larmv5_ec_line_size
138 bcs .Larmv5_ec_dcache_wbinv_all
140 sub r1, r1, #1 /* Don't overrun */
146 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
150 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
152 END(armv5_ec_dcache_wbinv_range)
155 * Note, we must not invalidate everything. If the range is too big we
156 * must use wb-inv of the entire cache.
158 ENTRY(armv5_ec_dcache_inv_range)
159 ldr ip, .Larmv5_ec_line_size
161 bcs .Larmv5_ec_dcache_wbinv_all
163 sub r1, r1, #1 /* Don't overrun */
169 mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */
173 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
175 END(armv5_ec_dcache_inv_range)
177 ENTRY(armv5_ec_idcache_wbinv_range)
178 ldr ip, .Larmv5_ec_line_size
180 bcs .Larmv5_ec_idcache_wbinv_all
182 sub r1, r1, #1 /* Don't overrun */
188 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
189 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
193 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
195 END(armv5_ec_idcache_wbinv_range)
196 #endif /* !ELF_TRAMPOLINE */
198 ENTRY_NP(armv5_ec_idcache_wbinv_all)
199 .Larmv5_ec_idcache_wbinv_all:
201 * We assume that the code here can never be out of sync with the
202 * dcache, so that we can safely flush the Icache and fall through
203 * into the Dcache purging code.
205 mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */
206 /* Fall through to purge Dcache. */
207 END(armv5_ec_idcache_wbinv_all)
209 #ifndef ELF_TRAMPOLINE
210 ENTRY(armv5_ec_dcache_wbinv_all)
211 .Larmv5_ec_dcache_wbinv_all:
212 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 /* Test, clean and invalidate DCache */
213 bne 1b /* More to do? */
214 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
216 END(armv5_ec_dcache_wbinv_all)