1 /* $NetBSD: cpufunc_asm_armv5_ec.S,v 1.1 2007/01/06 00:50:54 christos Exp $ */
4 * Copyright (c) 2002, 2005 ARM Limited
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31 * ARMv5 assembly functions for manipulating caches.
32 * These routines can be used by any core that supports both the set/index
33 * operations and the test and clean operations for efficiently cleaning the
34 * entire DCache. If a core does not have the test and clean operations, but
35 * does have the set/index operations, use the routines in cpufunc_asm_armv5.S.
36 * This source was derived from that file.
39 #include <machine/asm.h>
40 __FBSDID("$FreeBSD$");
43 * Functions to set the MMU Translation Table Base register
45 * We need to clean and flush the cache as it uses virtual
46 * addresses that are about to change.
48 ENTRY(armv5_ec_setttb)
50 * Some other ARM ports save registers on the stack, call the
51 * idcache_wbinv_all function and then restore the registers from the
52 * stack before setting the TTB. I observed that this caused a
53 * problem when the old and new translation table entries' buffering
54 * bits were different. If I saved the registers in other registers
55 * or invalidated the caches when I returned from idcache_wbinv_all,
56 * it worked fine. If not, I ended up executing at an invalid PC.
57 * For armv5_ec_settb, the idcache_wbinv_all is simple enough, I just
58 * do it directly and entirely avoid the problem.
60 mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */
61 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 /* Test, clean and invalidate DCache */
62 bne 1b /* More to do? */
63 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
65 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
67 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
72 * Cache operations. For the entire cache we use the enhanced cache
76 ENTRY_NP(armv5_ec_icache_sync_range)
77 ldr ip, .Larmv5_ec_line_size
79 bcs .Larmv5_ec_icache_sync_all
81 sub r1, r1, #1 /* Don't overrun */
87 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
88 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
92 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
95 .Larmv5_ec_icache_sync_all:
97 * We assume that the code here can never be out of sync with the
98 * dcache, so that we can safely flush the Icache and fall through
99 * into the Dcache cleaning code.
101 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
102 /* Fall through to clean Dcache. */
104 .Larmv5_ec_dcache_wb:
106 mrc p15, 0, APSR_nzcv, c7, c10, 3 /* Test and clean (don't invalidate) */
107 bne 1b /* More to do? */
108 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
110 END(armv5_ec_icache_sync_range)
112 .Larmv5_ec_line_size:
113 .word _C_LABEL(arm_pdcache_line_size)
115 ENTRY(armv5_ec_dcache_wb_range)
116 ldr ip, .Larmv5_ec_line_size
118 bcs .Larmv5_ec_dcache_wb
120 sub r1, r1, #1 /* Don't overrun */
126 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
130 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
132 END(armv5_ec_dcache_wb_range)
134 ENTRY(armv5_ec_dcache_wbinv_range)
135 ldr ip, .Larmv5_ec_line_size
137 bcs .Larmv5_ec_dcache_wbinv_all
139 sub r1, r1, #1 /* Don't overrun */
145 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
149 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
151 END(armv5_ec_dcache_wbinv_range)
154 * Note, we must not invalidate everything. If the range is too big we
155 * must use wb-inv of the entire cache.
157 ENTRY(armv5_ec_dcache_inv_range)
158 ldr ip, .Larmv5_ec_line_size
160 bcs .Larmv5_ec_dcache_wbinv_all
162 sub r1, r1, #1 /* Don't overrun */
168 mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */
172 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
174 END(armv5_ec_dcache_inv_range)
176 ENTRY(armv5_ec_idcache_wbinv_range)
177 ldr ip, .Larmv5_ec_line_size
179 bcs .Larmv5_ec_idcache_wbinv_all
181 sub r1, r1, #1 /* Don't overrun */
187 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
188 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
192 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
194 END(armv5_ec_idcache_wbinv_range)
196 ENTRY_NP(armv5_ec_idcache_wbinv_all)
197 .Larmv5_ec_idcache_wbinv_all:
199 * We assume that the code here can never be out of sync with the
200 * dcache, so that we can safely flush the Icache and fall through
201 * into the Dcache purging code.
203 mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */
204 /* Fall through to purge Dcache. */
205 END(armv5_ec_idcache_wbinv_all)
207 ENTRY(armv5_ec_dcache_wbinv_all)
208 .Larmv5_ec_dcache_wbinv_all:
209 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 /* Test, clean and invalidate DCache */
210 bne 1b /* More to do? */
211 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
213 END(armv5_ec_dcache_wbinv_all)