1 /* $NetBSD: cpufunc_asm_armv6.S,v 1.4 2010/12/10 02:06:22 bsh Exp $ */
4 * Copyright (c) 2002, 2005 ARM Limited
5 * Portions Copyright (c) 2007 Microsoft
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32 * ARMv6 assembly functions for manipulating caches.
33 * These routines can be used by any core that supports the mcrr address
41 #include <machine/asm.h>
46 * Functions to set the MMU Translation Table Base register
48 * We need to clean and flush the cache as it uses virtual
49 * addresses that are about to change.
52 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
54 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
56 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
64 /* LINTSTUB: void armv6_dcache_wb_range(vaddr_t, vsize_t); */
65 ENTRY(armv6_dcache_wb_range)
68 mcrr p15, 0, r1, r0, c12 /* clean D cache range */
69 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
71 END(armv6_dcache_wb_range)
73 /* LINTSTUB: void armv6_dcache_wbinv_range(vaddr_t, vsize_t); */
74 ENTRY(armv6_dcache_wbinv_range)
77 mcrr p15, 0, r1, r0, c14 /* clean and invaliate D cache range */
78 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
80 END(armv6_dcache_wbinv_range)
83 * Note, we must not invalidate everything. If the range is too big we
84 * must use wb-inv of the entire cache.
86 * LINTSTUB: void armv6_dcache_inv_range(vaddr_t, vsize_t);
88 ENTRY(armv6_dcache_inv_range)
91 mcrr p15, 0, r1, r0, c6 /* invaliate D cache range */
92 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
94 END(armv6_dcache_inv_range)
96 /* LINTSTUB: void armv6_idcache_wbinv_all(void); */
97 ENTRY_NP(armv6_idcache_wbinv_all)
99 * We assume that the code here can never be out of sync with the
100 * dcache, so that we can safely flush the Icache and fall through
101 * into the Dcache purging code.
103 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
106 mcr p15, 0, r0, c7, c14, 0 /* clean & invalidate D cache */
107 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
109 END(armv6_idcache_wbinv_all)
111 ENTRY(armv6_idcache_inv_all)
113 mcr p15, 0, r0, c7, c7, 0 /* invalidate all I+D cache */
115 END(armv6_idcache_inv_all)